Sub-threshold Leakage
Modeling and Reduction
Techniques
James Kao1,3
Siva Narendra2,3
Anantha Chandrakasan3
1Silicon
Labs
2Intel
Labs
3Massachusetts
Institute of Technology
Outline
Technology scaling and motivation
Sub-threshold leakage modeling
Sub-threshold leakage reduction
2
Moore’s Law on scaling
3
Scaling of dimensions
Gate
1
Tox
Source
L
Body
Drain
1
Gate
0.7 Tox
Source
0.7 L
Body
1
Delay = 1
Freq = 1
0.49
Drain
0.7
0.7
Delay ≈ 0.7
1
Freq ≈
= 1.43
0 .7
4
Channel length (um)
0.7X in
3.6 years
1
0.7X in
2 years
0.1
July-02
July-92
July-82
1e+8
July-72
0.01
2.1X in
2 years
Introduction date
1e+7
1e+6
1e+5
Requires die size growth
or same die size
3.3X in
3.6 years
1e+4
July-02
July-92
July-82
1e+3
July-72
Channel length (um)
Number
of logic
logic transistors
transistors
Number of
10
Introduction date
5
From early 90s to Present:
2X in
2 years
1e+9
100e+6
1.7X in
3.6 years
10e+6
July-02
July-92
July-82
10
July-72
1e+6
ε
2
Power ∝ Area × × VDD
×F
t
1
~ 1 .0 ×
× 1 2 × 2 ≈ 2 .9
0 .7
1
~ 1 .0 ×
× 0 .7 2 × 2 ≈ 1 .4
0 .7
Introduction date
0.7X in
2 years
1
Delay ∝
July-02
July-92
July-82
0.1
July-72
Supply voltage (V)
Core frequency (Hz)
Supply voltage (V)
10e+9
Introduction date
1
ION
=
1
( VDD − VT )α
VDD scaling requires
VT scaling
6
To continue scaling…
Dimensions including L and TOX have
to reduce
VDD has to reduce to control switching
power increase and oxide reliability
VT has to reduce to maintain
performance increase
7
−V
IOFF ∝ 10
T
S
S ~ 85 mV / decade
VDD ↓ ⇒
VT↓
IOFF ↑↑
8
10
Switching
54%
42%
18% Present
4%
0%
0%
0%
Power trend
15
…
5
0
1
0
0
8
0
%
6
0
%
4
0
%
Leakage
Total
2
0
Sub-threshold
leakage
0.01
1.4X
0.1
%
0
%
%
- 2
0
%
- 4
0
%
- 6
0
%
1
Channel length (um)
Necessary to estimate and reduce sub-threshold
leakage power
9
L
D
Tox
Xj
L
Device ≈
ε
aspect
3 Tox si X j D
ratio
ε ox
Device aspect ratio
Device scaling
10
8
6
4
2
0
N-1
N N+1 N+2
Technology
generation
Short channel effects increase with scaling
10
Increasing
electron
energy
(NMOS)
n+
Barrier height
height
Barrier
Barrier
height
Barrier Lowering (BL)
Source (n+)
L
p
Channel of length L
Xd
Short L
n+
Xd
Drain (n+)
Long L
L↓ ⇒
VT↓
IOFF ↑↑
11
D
S
Increase Drain
voltage
Barrier height
Barrier height
Drain Induced BL (DIBL)
D
S
Increase Drain
voltage
Long L
Short L
VDS↑ ⇒
VT↓
IOFF ↑↑
12
Impact of variation in L
VT (Volts)
BL (VDSÆ0)
DIBL (VDS=VDD)
VTLIN (VDSÆ0)
VTSAT (VDS=VDD)
Channel length (um)
∆L Î ∆VT Î ∆ION & ∆IOFF
13
Short Channel MOS Vt
Vt = Vfb + 2φ p +
λb
Cox
2qNε s (| 2φp | +Vsb ) − λdVds
Vt-roll-off factor
H. C. Poon et al., IEDM, pp. 156-159, 1973

 Xj
2W

− 1
λb = 1 − 1 +

 L
Xj


DIBL equation
K. K. Ng et al., IEEE TED, pp. 1895-1897, Oct. 1993


L
λd = 

−2
+
+
+
µ
µ
µ
µ
2
.
2
m
(
T
0
.
012
m
)
(
W
0
.
15
m
)
(
X
2
.
9
m
)


ox
sd
j
−2 . 7
14
Sub-threshold leakage
If the current scaling trend continues subthreshold leakage power expected to be ~50%
of the total power.
Î Accurate prediction of chip leakage power
Î Techniques to reduce chip leakage power
15
Estimation requirements
Require to include within-die variations in
Channel length Standby leakage
Supply voltage
Active & burn-in leakage
Temperature
16
Leakage modeling
Prior techniques
Lower bound:
Assumes all devices in the die are nominal L
I leak -l =
wp
kp
I
o
p
+
wn o
In
kn
Upper bound:
Assumes all devices in the die are minimum L
I leak -u =
wp
kp
I
3σ
off − p
+
wn 3σ
I off −n
kn
17
New model
Includes within-die variation
o
I leak
I w
1
=
k σ 2π
l max
∫ e
−( l − µ ) 2
2σ 2
( µ −l )
e λ
dl
l min
σ2
l max−−(µl − µ )σ
µ − l min
σ
2
2
erf ( z ) → 1 if z > 1 and
,µ − l ) −σ −
+
(
o
l max 2σ
2σ 2
2
I w using
1 error function
After simplification
properties, 2 2λ
k
oσ
σ2
2π
I w 2λ2
⇒ I leak =
e
o k
e 2λ
∫
e
2σ
e λ
e 2λ
d
l min
σ2
2
I w
1
λ
2
=
e
k σ 2π
IOFF
=
I3σ 2
σ I
 l −µ
+
l max − 
ο

a e-L/λ
σ
λ
2
2


e
dl
∫
l min
L (µm)
18
Applications…
A macroscopic standard
deviation (σ) representing
parameter variation in a chip
 k I leak 
σ = λ 2 ln

o
w I 
I leak −w =
I op w p
kp
σ p2
e
2λ p 2
σ n2
+
I no wn 2λn2
e
kn
Leakage
estimation
Depends on parameters that can be estimated
19
Measurement results
Number of samples
0.18 um 32-bit microprocessors (n=960)
500
µ: 0.65
Ileak-u σ: 0.27
400
300
µ: 1.04
Ileak-w σ: 0.3
200
Ileak-l µ: 6.5
100
σ: 3.8
0
0.1
1
10
100
Ratio of measured to
calculated leakage
50% of the samples within ±20% of the measured leakage
Compared 11% and 0.2% of the samples using other techniques
20
Stack effect
For a stack of two devices
Vdd
Istack
Vdd
Idevice
VX < Vdd
Vdd
Drain
Source
Istack
Drain
Source
Idevice
VX < Vdd
21
Stack effect factor model
X=
I device
w
= α 1−α 10
I stack w w
u l
λ V
= 10
d dd (1−α )
I stack
S
λ V
α
d dd (1−α )
S
1−α
=when
wu wwl =Iw
1 =w
u
l
where α ≈
λd – DIBL
−λ V
d dd (1−α )
10 S
λ
d
1+ 2 λ
d
S – Sub-threshold swing
Stack effect factor can be predicted
based on fundamental device parameters
22
Model verification
0.18 µm device measurements; zero body bias
 1+ λ
d dd 
d
S  1+ 2 λ
d

λ V
X = 10




= 10U
23
Idevice vs. Istack
Normalized two
leakage
Normalized
twostack
stack
leakage
0.18 µm device measurements
100000
100000
30 C and 80C
C
O
O
10000
10000
80 C
1000
1000
100
100
30 C
10
10
1
1
1
1
10
10
100
1000 10000
10000 100000
100 1000
100000
Normalized single
device
leakage
Normalized
single
device
leakage
Leakage of a two stack increases
at a slower rate
24
Summary
Scaling trend indicate sub-threshold leakage
power expected to be ~50% of the total power
Sub-threshold leakage power models should
include within-die parameter variation including
L, Temperature, Vcc, and device connectivity
Reduction in impact of parameter variation and
sub-threshold leakage are essential for scaling
25