Lecture 240 Cascode Op Amps (3/28/10)
Page 240-1
LECTURE 240 – CASCODE OP AMPS
LECTURE ORGANIZATION
Outline
• Lecture Organization
• Single Stage Cascode Op Amps
• Two Stage Cascode Op Amps
• Summary
CMOS Analog Circuit Design, 2nd Edition Reference
Pages 293-310
CMOS Analog Circuit Design
Lecture 240 Cascode Op Amps (3/28/10)
© P.E. Allen - 2010
Page 240-2
Cascode Op Amps
Why cascode op amps?
• Control of the frequency behavior
• Can get more gain by increasing the output resistance of a stage
• In the past section, PSRR of the two-stage op amp was insufficient for many
applications
• A two-stage op amp can become unstable for large load capacitors (if nulling resistor
is not used)
• The cascode op amp leads to wider ICMR and/or smaller power supply requirements
Where Should the Cascode Technique be Used?
• First stage Good noise performance
Requires level translation to second stage
Degrades the Miller compensation
• Second stage Self compensating
Increases the efficiency of the Miller compensation
Increases PSRR
CMOS Analog Circuit Design
© P.E. Allen - 2010
Lecture 240 Cascode Op Amps (3/28/10)
Page 240-3
SINGLE STAGE CASCODE OP AMPS
Simple Single Stage Cascode Op Amp
VDD
M3
VDD
Implementation of the M3
floating voltage VBias
which must equal
MB3
2VON + VT.
VPBias2
MC3
M4
VPBias2
MC4
MC3
vo1
M4
MB4
MC4
MB5
MC2
MC1
M1
M2
VBias
+v
vin
+ 2
in
2+
VNBias1
-
MC1
M1
M5
VSS
-
+v
+
VBias
MB1
MC2
M2
MB2
-
in
2+
VNBias1
-
vin + 2
M5
VSS
060627-01
Rout of the first stage is RI (gmC2rdsC2rds2)||(gmC4rdsC4rds4)
vo1
Voltage gain = vin = gm1RI
[The gain is increased by approximately 0.5(gMCrdsC)]
As a single stage op amp, the compensation capacitor becomes the load capacitor.
CMOS Analog Circuit Design
Lecture 240 Cascode Op Amps (3/28/10)
© P.E. Allen - 2010
Page 240-4
Example 240-1 Single-Stage, Cascode Op Amp Performance
Assume that all W/L ratios are 10 μm/1 μm, and that IDS1 = IDS2 = 50 μA of single
stage op amp. Find the voltage gain of this op amp and the value of CI if GB = 10 MHz.
Use KN’ = 120μA/V2, KP’ = 25μA/V2, VTN = 0.5V, VTP = -0.5V, N = 0.06V-1 and P =
0.08V-1.
Solution
The device transconductances are
gm1 = gm2 = gmI = 346.4 μS
gmC1 = gmC2 = 346.4μS
gmC3 = gmC4 = 158.1 μS.
The output resistance of the NMOS and PMOS devices is 0.333 M and 0.25 M,
respectively.
RI = 7.86 M
Av(0) = 2,722 V/V.
For a unity-gain bandwidth of 10 MHz, the value of CI is 5.51 pF.
What happens if a 100pF capacitor is attached to this op amp?
GB goes from 10MHz to 0.551MHz.
CMOS Analog Circuit Design
© P.E. Allen - 2010
Lecture 240 Cascode Op Amps (3/28/10)
Page 240-5
Enhanced Gain, Single Stage, Cascode Op Amp
VDD
VDD
M8
M7
M8
M7
M15
-A
M5
M6
M5
M4
M2
M1
+
vIN
−
M3
-A
-A
M16
VDD
VPB1
vOUT
M3
M6
VNB1
VDD
M13
M14
M11
M12
M4
M2
M1
+
vIN
−
vOUT
M9
VNB1
VNB1
M9
M10
060627-02
From inspection, we can write the voltage gain as,
vOUT
where Rout = (Ards6gm6rds8)|| (Ards2gm4rds4)
Av = vIN = gm1Rout
Since A gmrds/2 the voltage gain would be equal to 100,000 to 500,000.
Output is not optimized for maximum signal swing.
CMOS Analog Circuit Design
© P.E. Allen - 2010
Lecture 240 Cascode Op Amps (3/28/10)
Page 240-6
TWO-STAGE, CASCODE OP AMPS
Two-Stage Op Amp with a Cascoded First-Stage
Current
VDD
M3
M4
MT2
MB3
MB4
MC3
ID6
M6
MC4
R
VT6
MT1
Cc
vo1
vout
MB5
MC1
M1
+
VBias
MB1
-v
in
2 +
MC2
VSG6 VSG6 =
Volts
= VSD4 VSD4+VSDC4
M2
MB2
+
VBias
-
W6/L6 W6’/L6’<< W6/L6
M5
vin +
- 2
M7
VSS
• MT1 and MT2 are required for level shifting
from the first-stage to the second.
• The PSRR+ is improved by the presence of MT1
p3 p2
• Internal loop pole at the gate of M6 may cause
the Miller compensation to fail.
• The voltage gain of this op amp could easily be 100,000V/V
CMOS Analog Circuit Design
070427-01
jω
p1
z1
σ
Fig. 6.5-2A
© P.E. Allen - 2010
Lecture 240 Cascode Op Amps (3/28/10)
Page 240-7
Two-Stage Op Amp with a Cascode Second-Stage
Av = gmIgmIIRIRII
where gmI = gm1 = gm2,
and
VDD
gmII = gm6,
M6
1
2
RI = gds2+gds4 = (2+4)ID5
RII = (gmC6rdsC6rds6)||(gmC7rdsC7rds7)
M3
Rz
vin
+
M1
+
VBias
-
Comments:
• The second-stage gain has greatly
increased improving the Miller compensation
•
•
•
•
M4
M2
VBP
Cc
MC6
VBN
MC7
vout
CL
M7
M5
VSS
Fig. 6.5-3
The overall gain is approximately (gmrds)3 or very large
Output pole, p2, is approximately the same if Cc is constant
The zero RHP is the same if Cc is constant
PSRR is poor unless the Miller compensation is removed (then the op amp becomes
self compensated)
CMOS Analog Circuit Design
© P.E. Allen - 2010
Lecture 240 Cascode Op Amps (3/28/10)
Page 240-8
A Balanced, Two-Stage Op Amp using a Cascode Output Stage
g
VDD
gm2gm6 vin
m1gm8 vin
vout = gm3 2 + gm4 2 RII
M6
M4
gm1 gm2
= 2 + 2 kvin RII = gm1·k·RII vin
M8 VPB2
M3
M7
where
vout
RII = (gm7rds7rds6)||(gm12rds12rds11)
M1
M2
VNB2 M9
vin
CL
M12
and
+
gm8 gm6
M5
M10
M11
k
=
+
gm3 = gm4
V
NB1
-
VSS
060627-03
This op amp is balanced because the
drain-to-ground loads for M1 and M2 are identical.
TABLE 1 - Design Relationships for Balanced, Cascode Output Stage Op Amp.
Iout
gm1gm8
1 gm1gm8 gm2gm6
Slew rate = CL
GB = gm3CL
Av = 2 gm3 + gm4 RII
I I 5 1/2
5 1/2
V in(max) = VDD 3 |VTO3|(max) +VT1(min)
V in(min) = VS S + VDS5 + 1 + VT1(min)
CMOS Analog Circuit Design
© P.E. Allen - 2010
Lecture 240 Cascode Op Amps (3/28/10)
Page 240-9
Example 240-2 Design of Balanced, Cascoded Output Stage Op Amp
Design a balanced, cascoded output stage op amp using the procedure outlined
above. The specifications of the design are as follows:
V DD = 2.5 V (VSS = 0)
Slew rate = 5 V/μs with a 50 pF load
GB = 10 MHz with a 25 pF load Av 5000
Input CMR = 1V to +2 V
0.5V < Output swing < 2 V
Use KN’=120μA/V2, KP’= 25μA/V2, VTN = |VTP| = 0.5V, N = 0.06V-1, and P =
0.08V-1and let all device lengths be 0.5 μm.
Solution
While numerous approaches can be taken, we shall follow one based on the above
specifications. The steps will be numbered to help illustrate the procedure.
1.) The first step will be to find the maximum source/sink current. This is found from the
slew rate.
Isource/Isink = CL slew rate = 50 pF(5 V/μs) = 250 μA
2.) Next some W/L constraints based on the maximum output source/sink current are
developed. Under dynamic conditions, all of I5 will flow in M4; thus we can write
Max. Iout(source) = (S6/S4)I5 and Max. Iout(sink) = (S8/S3)I5
The maximum output sinking current is equal to the maximum output sourcing current if
S3 = S4, S6 = S8, and S10 = S11
CMOS Analog Circuit Design
Lecture 240 Cascode Op Amps (3/28/10)
© P.E. Allen - 2010
Page 240-10
Example 240-2 - Continued
3.) Choose I5 as 100 μA. This current (which can be changed later) gives
S6 = 2.5S4 and S8 = 2.5S3
Note that S8 could equal S3 if S11 = 2.5S10. This would minimize the power dissipation.
4.) Next design for +0.5V output capability. We shall assume that the output must
source or sink the 250μA at the peak values of output. First consider the negative output
peak. Since there is 0.5V difference between VSS(0V) and the minimum output, let
V DS11(sat) = VDS12(sat) = 0.25 V (we continue to ignore the bulk effects). Under the
maximum negative peak assume that I11 = I12 = 250 μA. Therefore
2I11
2I12
500μA
K'NS11 =
K'NS12 =
(120μA/V2)S11
which gives S11 = S12 = 67 and S9 = S10 = 67. For a maximum output voltage of 2V, we
get
2I6
2I7
500μA
0.25 =
=
=
K'PS6
K'PS7
(25μA/V2)S6
which gives S6 = S7 = S8 = 320 and S3 = S4 = (320/2.5) = 128.
0.25 =
CMOS Analog Circuit Design
© P.E. Allen - 2010
Lecture 240 Cascode Op Amps (3/28/10)
Page 240-11
Example 240-2 - Continued
5.) Now we must consider the possibility of conflict among the specifications.
First consider the input CMR. S3 has already been designed as 67. Using ICMR
relationship, we find that S3 should be at least 8. A larger value of S3 will give a higher
value of Vin(max) so that we continue to use S3 = 67 which gives Vin(max) = 2.32V.
Next, check to see if the larger W/L causes a pole below the gainbandwidth.
Assuming a Cox of 6fF/μm2 gives the first-stage pole of
-gm3
- 2K’PS3I3
p3 = Cgs3+Cgs8 = (0.667)(W3L3+W 8L8)Cox = 3.125x109 rads/sec or 497 MHz
which is much greater than 10GB.
6.) Next we find gm1 (gm2). There are two ways of calculating gm1.
(a.) The first is from the Av specification. The gain is
Av = (gm1/2gm4)(gm6 + gm8) RII
Note, a current gain of k can be introduced by making S6/S4 (S8/S3 = S11/S3) equal to k.
gm6 gm11
2KP’·S 6·I6
=
=
gm4 gm3
2KP’·S 4·I4 = k
Calculating the various transconductances we get gm4 = 566 μS, gm6 = gm7 = gm8 = 1414
μS, gm11 = gm12 = 1414 μS, rds6 = rd7 = 100 k, and rds11 = rds12 = 133 k. Assuming
that the gain Av must be greater than 5000 and k = 2.5 gives gm1 > 221 μS.
CMOS Analog Circuit Design
Lecture 240 Cascode Op Amps (3/28/10)
© P.E. Allen - 2010
Page 240-12
Example 240-2 - Continued
(b.) The second method of finding gm1 is from the GB specifications. Multiplying the
gain by the dominant pole (1/CIIRII) gives
gm1(gm6+gm8)
GB =
2gm4CL
Assuming that CL= 25 pF and using the specified GB gives gm1 = 628 μS.
Since this is greater than 221μS, we choose gm1 = gm2 = 628μS. Knowing I5 gives S1 =
S2 = 32.9 33.
8.) The next step is to check that S1 and S2 are large enough to meet the +1V input CMR
specification. Use the saturation formula we find that VDS5 is 0.341 V. This gives S5 = 15.
The gain becomes Av = 14,182V/V and GB = 10 MHz for a 25 pF load. We shall assume
that exceeding the specifications in this area is not detrimental to the performance of the
op amp.
9.) Knowing the currents and W/L values, the bias voltages VNB1, VNB2 and VPB2 can be
designed.
The W/L values resulting from this design procedure are shown below. The power
dissipation for this design is seen to be 350μA·2.5V = 0.875 mW.
S1 = S2 = 33
S3 = S4 = 128
S5 = 15
S6 = S7 = S8 = 320
S9 = S10 = S11 = S12 = 67
CMOS Analog Circuit Design
© P.E. Allen - 2010
Lecture 240 Cascode Op Amps (3/28/10)
;;;
;;
Page 240-13
Technological Implications of the Cascode Configuration
A
A
B
C
D
;;;;;;;
B
Thin
oxide
Poly I
C
Poly II
n-channel
n+
n+
p substrate/well
D
Fig. 6.5-5
If a double poly CMOS process is available, inter-node parasitics can be minimized.
As an alternative, one should keep the drain/source between the transistors to a minimum
area.
A
A
Minimum Poly
separation
B
D
C
;;;;;;;;
B
Thin
oxide
Poly I
Poly I
n+ n-channel n+ n-channel
C
n+
p substrate/well
D
Fig. 6.5-5A
CMOS Analog Circuit Design
© P.E. Allen - 2010
Lecture 240 Cascode Op Amps (3/28/10)
Page 240-14
Input Common Mode Range for Two Types of Differential Amplifier Loads
VDD-VSG3+VTN
+
VSG3
Input
- M3
Common
Mode
M1
Range
VSS+VDS5+VGS1
+
VBias
-
VDD-VSD3+VTN
VDD
+
VSD4
M4 M2
M5 vicm
VSS
Differential amplifier with
a current mirror load.
VDD
+
V
Input SD3
Common - M3
Mode
Range
M1
VSS+VDS5+VGS1
+
VBias
-
+
VSD4
M4 VBP
M2
M5 vicm
VSS
Differential amplifier with
Fig. 6.5-6
current source loads.
In order to improve the ICMR, it is desirable to use current source (sink) loads without
losing half the gain.
The resulting solution is the folded cascode op amp.
CMOS Analog Circuit Design
© P.E. Allen - 2010
Lecture 240 Cascode Op Amps (3/28/10)
Page 240-15
The Folded Cascode Op Amp
VDD
VPB1
I4
I5
M4
I1
+
vIN
−
I2
I3
RB
VPB2
I7
M6
M1 M2
M3
VNB1
RA
I6
M5
M7
vOUT
VNB2
M8
M9
M10
M11
CL
060628-04
Comments:
• I4 and I5, should be designed so that I6 and I7 never become zero (i.e. I4=I5=1.5I3)
• This amplifier is nearly balanced (would be exactly if RA was equal to RB)
• Self compensating
• Poor noise performance, the gain occurs at the output so all intermediate transistors
contribute to the noise along with the input transistors. (Some first stage gain can be
achieved if RA and RB are greater than gm1 or gm2.
CMOS Analog Circuit Design
© P.E. Allen - 2010
Lecture 240 Cascode Op Amps (3/28/10)
Small-Signal Analysis of the Folded Cascode Op Amp
Model:
gm6vgs6
RA
Recalling what we
i10
learned about the
gm1vin
g
m2vin
r
resistance looking into 2
rds1 rds4 vgs6 ds6 1
2
gm10
the source of the
+
cascode transistor;
Page 240-16
gm7vgs7
RB
rds2 rds5
i7
vgs7 rds7 i
10
+
RII
+
vout
-
060628-02
rds6+(1/gm10) 1
rds7+RII
RII
RA = 1+gm6rds6 gm6 and RB = 1+gm7rds7 gm7rds7 where RII gm9rds9rds11
The voltage transfer function can be found as follows. The current i10 is written as
-gm1(rds1||rds4)vin -gm1vin
i10 = 2[RA+(rds1||rds4)] 2
and the current i7 can be expressed as
gm2(rds2||rds5)vin
gm2vin
gm2vin
RII(gds2+gds5)
i7 = RII
=
where
k
=
= RII(gds2+gds5) 2(1+k)
gm7rds7
2gm7rds7+(rds2||rds5) 2
1+ gm7rds7 The output voltage, vout, is equal to the sum of i7 and i10 flowing through Rout. Thus,
2+k vout gm1
gm2 R
=
+
=
vin 2 2(1+k) out 2+2k gmIRout
CMOS Analog Circuit Design
© P.E. Allen - 2010
Lecture 240 Cascode Op Amps (3/28/10)
Page 240-17
Intuitive Analysis of the Folded Cascode Op Amp
Assume that a voltage of V is applied. We
know that
RA(M6) 1/gm6 and RB(M7) rds
The currents flowing to the output are,
gm1V gm2V
2 + 4
The output resistance is approximately,
Rout (gm9rds9rds11)||[ gm7rds7(rds2||rds5)]
gmrds2
3 Therefore, the approximate voltage gain is,
vout gm1 gm2
gm 2rds2
3gm vin = 2 + 4 Rout 4 Rout = 4 While the analysis is simpler than small signal analysis, the value of k defined in the
previous slide is 1.
CMOS Analog Circuit Design
Lecture 240 Cascode Op Amps (3/28/10)
© P.E. Allen - 2010
Page 240-18
Frequency Response of the Folded Cascode Op Amp
The frequency response of the folded cascode op amp is determined primarily by the
output pole which is given as
2+k -1
pout = R 'C
where
R
’
=
out
2+2kRout
out out
where Cout is all the capacitance connected from the output of the op amp to ground.
All other poles must be greater than GB = gm1/Cout. The approximate expressions for
each pole is
1.) Pole at node A:
pA - gm6/(Cgs+ 2Cdb)
2.) Pole at node B:
pB - gm7/(Cgs+ 2Cdb)
3.) Pole at drain of M6:
p6 -gm10/(2Cgs+ 2Cdb)
4.) Pole at source of M8:
p8 -(gm8rds8gm10)/(Cgs+ Cdb)
5.) Pole at source of M9:
p9 -gm9/(Cgs+ Cdb)
where the approximate expressions are found by the reciprocal product of the resistance
and parasitic capacitance seen to ground from a given node. One might feel that because
RB is approximately rds that this pole also might be small. However, at frequencies
where this pole has influence, Cout, causes Rout to be much smaller making pB also nondominant.
CMOS Analog Circuit Design
© P.E. Allen - 2010
Lecture 240 Cascode Op Amps (3/28/10)
Page 240-19
Example 240-3 - Folded Cascode, CMOS Op Amp
Assume that all gmN = gmP = 100μS, rdsN = 2M, rdsP = 1M, and CL = 10pF. Find all
of the small-signal performance values for the folded-cascode op amp.
0.4x109(0.3x10-6)
k=
= 1.2
RII = 0.4G, RA = 10k, and RB = 4M
100
vout 2+1.2
vin = 2+2.4 (100)(57.143) = 4,156V/V
Rout = RII ||[gm7rds7(rds5||rds2)] = 400M||[(100)(0.667M)] = 57.143M
1
1
|pout| = R C = 57.143M·10pF = 1,750 rads/sec. 278Hz GB = 1.21MHz
out out
CMOS Analog Circuit Design
© P.E. Allen - 2010
Lecture 240 Cascode Op Amps (3/28/10)
Page 240-20
PSRR of the Folded Cascode Op Amp
Consider the following circuit used to model the PSRR-:
VDD
R
Vss
Cgd11
VGSG9
Cgd9
M9
Vss
Vss
VGS11
rds9
Vout
Cgd9
Vss
M11
Cout
rds11
Vss
Rout
+
Vout
-
Fig. 6.5-9A
This model assumes that gate, source and drain of M11 and the gate and source of M9 all
vary with VSS.
We shall examine Vout/V ss rather than PSRR-. (Small Vout/V ss will lead to large PSRR-.)
The transfer function of Vout/V ss can be found as
V out
sCgd9Rout
V ss sCoutRout+1 for Cgd9 < Cout
The approximate PSRR- is sketched on the next page.
CMOS Analog Circuit Design
© P.E. Allen - 2010
Lecture 240 Cascode Op Amps (3/28/10)
Page 240-21
Frequency Response of the PSRR- of the Folded Cascode Op Amp
dB
|PSRR-|
|Avd(ω)|
1
Cgd9Rout
Dominant
pole frequency
0dB
Cgd9
Cout
GB
Vout
Vss
Other sources of Vss injection, i.e. rds9
log10(ω)
Fig. 6.5-10A
We see that the PSRR of the cascode op amp is much better than the two-stage op amp
without any modifications to improve the PSRR.
CMOS Analog Circuit Design
© P.E. Allen - 2010
Lecture 240 Cascode Op Amps (3/28/10)
Page 240-22
Design Approach for the Folded-Cascode Op Amp
Step
Relationship
1 Slew Rate
2 Bias currents in
output cascodes
3 Maximum output
voltage,
vout(max)
4 Minimum output
voltage, vout(min)
5
6
7
8
9
Design Equation/Constraint
I3 = SR·CL
I4 = I5 = 1.2I3 to 1.5I3
2I5
2I7
S5=
,
S
=
, (S4=S5 and S6= S7)
7
KP’VSD72
KP’VSD52
2I9
2I11
, S9=
, (S10=S11and S8=S9)
S11=
2
KN’VDS11
KN’VDS92
gm1
gm12 GB2CL2
GB = C
S
=S
=
1 2 KN’I3 = KN’I3
L
Minimum input
2I3
CM
S3 =
2
KN’ Vin(min)-VSS- (I3/KN’S1)-VT1
Maximum input
2I4
CM
S4 = S5 =K ’ V -V (max)+V 2
P DD in
T1
Differential
vout gm1
gm2 2+k Voltage Gain
vin = 2 +2(1+k)Rout = 2+2k gmIRout
Power dissipation Pdiss = (VDD-VSS)(I3+I10+I11)
CMOS Analog Circuit Design
Comments
Avoid zero current in
cascodes
VSD5(sat)=VSD7(sat)
= 0.5[VDD-Vout(max)]
VDS9(sat)=VDS11(sat)
= 0.5[Vout(min)-VSS]
S4 and S5 must meet or
exceed value in step 3
k=
RII(gds2+gds4)
gm7rds7
© P.E. Allen - 2010
Lecture 240 Cascode Op Amps (3/28/10)
Page 240-23
Example 240-4 Design of a Folded-Cascode Op Amp
Design a folded-cascode op amp if the slew rate is 10V/μs, the load capacitor is 10pF, the
maximum and minimum output voltages are 2V and 0.5V for a 2.5V power supply, the
GB is 10MHz, the minimum input common mode voltage is +1V and the maximum input
common mode voltage is 2.5V. The differential voltage gain should be greater than
3,000V/V and the power dissipation should be less than 5mW. Use KN’=120μA/V2,
KP’= 25μA/V2, VTN = |VTP| = 0.5V, N = 0.06V-1, and P = 0.08V-1. Let L = 0.5 μm.
Solution
Following the approach outlined above we obtain the following results.
I3 = SR·CL = 10x106·10-11 = 100μA
Select I4 = I5 = 125μA.
Next, we see that the value of 0.5(VDD-V out(max)) is 0.5V/2 or 0.25V. Thus,
2·125μA
2·125·16
S4 = S5 = 25μA/V2·(0.25V)2 = 25 = 160
and assuming worst case currents in M6 and M7 gives,
2·125μA
2·125·16
S6 = S7 = 25μA/V2(0.25V)2 = 25 = 160
The value of 0.5(Vout(min)-|VSS|) is 0.25V which gives the value of S8, S9, S10 and S11 as
2·I8
2·125
S8 = S9 = S10 = S11 = K ’V 2 = 120·(0.25)2 = 20
N DS8
CMOS Analog Circuit Design
Lecture 240 Cascode Op Amps (3/28/10)
© P.E. Allen - 2010
Page 240-24
Example 240-4 - Continued
In step 5, the value of GB gives S1 and S2 as
GB2·CL2 (20x106)2(10-11)2
S1 = S2 = KN’I 3 = 120x10-6·100x10-6 = 32.9 33
The minimum input common mode voltage defines S3 as
2I3
200x10-6
S3 =
=
= 14.3 15
I3
100
2 120x10-61.0+02
-0.5
KN’ V in(min)-VSS- KN’S 1-VT1
120·33
We need to check that the values of S4 and S5 are large enough to satisfy the maximum
input common mode voltage. The maximum input common mode voltage of 2.5 requires
2I4
2·125μA
S4 = S5 K ’[V -V (max)+V ]2 = 25x10-6μA/V2[0.5V]2 = 40
P
DD in
T1
which is less than 160. In fact, with S4 = S5 = 160, the maximum input common mode
voltage is 2.75V.
The power dissipation is found to be
Pdiss = 2.5V(125μA+125μA) = 0.625mW
CMOS Analog Circuit Design
© P.E. Allen - 2010
Lecture 240 Cascode Op Amps (3/28/10)
Page 240-25
Example 240-4 - Continued
The small-signal voltage gain requires the following values to evaluate:
S4, S5:
gm = 2·125·25·160 = 1000μS and gds = 125x10-6·0.08 = 10μS
S6, S7:
gm = 2·75·25·1600 = 774.6μS
S8, S9, S10, S11:
S1, S2:
Thus,
and gds = 75x10-6·0.08 = 6μS
gm = 2·75·120·20 = 600μS and gds = 75x10-6·0.06 = 4.5μS
gmI = 2·50·120·33 = 629μS and gds = 50x10-6(0.06) = 3μS
1 1 RII gm9rds9rds11 = (600μS) 4.5μS4.5μS = 29.63M
1 1
Rout 29.63M||(774.6μS)6μS10μS+3μS = 7.44M
RII(gds2+gds4) 7.44M(3μS+10μS)(6μS)
k = gm7rds7 =
= 0.75
774.6μS
The small-signal, differential-input, voltage gain is
2+k 2+0.75
Avd = 2+2k gmIRout = 2+1.5 0.629x10-3·7.44x106 = (0.786)(4680) = 3,678 V/V
The gain is slightly larger than the specified 3,000 V/V.
CMOS Analog Circuit Design
Lecture 240 Cascode Op Amps (3/28/10)
© P.E. Allen - 2010
Page 240-26
Comments on Folded Cascode Op Amps
• Good PSRR
• Good ICMR
• Self compensated
• Can cascade an output stage to get extremely high gain with lower output resistance
(use Miller compensation in this case)
• Need first stage gain for good noise performance
• Widely used in telecommunication circuits where large dynamic range is required
CMOS Analog Circuit Design
© P.E. Allen - 2010
Lecture 240 Cascode Op Amps (3/28/10)
Page 240-27
Enhanced-Gain, Folded Cascode Op Amps
If more gain is needed, the folded cascode op
amp can be enhanced to boost the output
impedance even higher as follows.
VDD
M11
M10
VPB1
M3
-A
+
vIN
−
M8
M9
M6
M7
M1 M2
vOUT
-A
-A
Voltage gain = gm1Rout,
M4
VNB1
M5
where
060718-03
Rout [Ards7gm7(rds1||rds5)]||
(Ards9gm9rds11)
Since A gmrds the voltage gain would be in the range of 100,000 to 500,000.
Note that to achieve maximum output swing, it will be necessary to make sure that M5
and M11 are biased with VDS = VDS(sat).
CMOS Analog Circuit Design
© P.E. Allen - 2010
Lecture 240 Cascode Op Amps (3/28/10)
Page 240-28
What are the Enhancement Amplifiers?
Requirements:
1.) Need a gain of gmrds.
2.) Must be able to set the dc voltage at its input to get wide-output voltage swing.
Possible Enhancement Amplifiers:
VDD
vin
-A
VPB1
vin
M4
VPB2M5 vin
vout
vout
VDD
VNB1
M2
-A
VDD
-VSD(Sat)
vout
M6
M3
vout
VNB2
M1
M6
VPB1
vin
M1
M5
VNB1
M2
VDS(Sat)
M4
M3
060718-05
CMOS Analog Circuit Design
© P.E. Allen - 2010
Lecture 240 Cascode Op Amps (3/28/10)
Page 240-29
Enhanced-Gain, Folded Cascode Op Amp
Detailed realization:
CMOS Analog Circuit Design
© P.E. Allen - 2010
Lecture 240 Cascode Op Amps (3/28/10)
Page 240-30
Frequency Response of the Enhanced Gain Cascode Op Amps
Normally, the frequency response of the cascode op amps would have one dominant pole
at the output. The frequency response would be,
R
gm1Rout
gm1Rout
out(1/sCout) Av(s) = gm1Rout+1/sCout = sRoutCout+1 =
s
1-p1
If the amplifier used to boost the output resistance had no frequency dependence then the
frequency response would be as follows.
Gain (db)
100dB
Enhanced Gain Cascode Op Amp
80dB
60dB Normal Cascode
Op Amp
40dB
0dB
CMOS Analog Circuit Design
|p1(enh)| |p1|
GB
log10ω
060629-02
© P.E. Allen - 2010
Lecture 240 Cascode Op Amps (3/28/10)
Page 240-31
Frequency Response of the Enhanced Gain Cascode Op Amp – Continued
• Does the pole in the feedback amplifier A have an influence?
Although the output resistance can be modeled as,
1- s p2Ao
Rout’ RoutAo
s 1-p2 it has no influence on the frequency response because Cout has shorted out any
influence a change in Rout might have.
• Higher order poles come from a diversion of the current flow in the op amp to ground
rather than the intended destination of the current to the output. These poles that
divert the current are:
- Pole at the source of M6 (Agm6/C6) - Pole at the source of M7 (Agm7/C7)
- Pole at the source of M9 (Agm9/C6)
- Pole at the drain of M8 (gm10/C8)
- Pole at the drain of M10 (gm8rds8gm10/C10)
Note that the enhancement amplifiers cause most of the higher-order poles to be moved
out by |A|. However, each of the enhancement amplifiers introduce a pole at their output
which is approximately -1/[rds(Cgs+2Cdb+2Cgd)]. These poles become the dominant
poles that limit GB.
CMOS Analog Circuit Design
Lecture 240 Cascode Op Amps (3/28/10)
© P.E. Allen - 2010
Page 240-32
SUMMARY
• Cascode op amps give additional flexibility to the two-stage op amp
- Increase the gain
- Control the dominant and nondominant poles
• Enhanced gain, cascode amplifiers provide additional gain and are used when high
gains are needed
• Folded cascode amplifier is an attractive alternate to the two-stage op amp
- Wider ICMR
- Self compensating
- Good PSRR
CMOS Analog Circuit Design
© P.E. Allen - 2010