Talk1: Overview of Power Devices and Technology Trends
Talk 2: Devices and Technologies for HVIC
Prof. Florin Udrea
Cambridge University
Taiwan, January 2010
F. Udrea
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Outline
Talk 1: Overview of Power Devices and Technology Trends
• Power Diodes
• Power MOSFETs
• IGBTs
• Super-junction Theorem, Technologies, and Applications
Talk 2: Devices and Technologies for HVIC
• RESURF Concept and Devices
• RESURF Other Forms
• BCD, HVCMOS, and SOI Technology Concepts and Applications
Q&A
F. Udrea
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HV.DC
Motor control
UPS
100M
Robot, Welding machine
Electric traction
Capacity (VA)
10M
Thyristor
1M
Auto
GTO
100K
Refrigerator
10K
IGBTs
MOSFET
Modules
1K
Switching
Power supply
TRIAC
100
Washing
machine
Air conditioner
Microwave
HVIC & PIC
MOSFET
VCR/DVD Power
supply for audio
10
10
F. Udrea
100
1K
10K
Operation frequency (Hz)
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100K
1M
3
The Power MOSFET
TheThe power MOSFFET is based on a classical low-power MOSFET with an additional drift region to support high
voltages. The current flow occurs solely by transport of majority carriers (in this case electrons) and consequently
does not lead to storage of excess carrier charge (plasma) as in the case of power bipolar devices (BJTs, thyristors).
This allows high switching speed, however at the expense of a relatively high on-state resistance.
The first power MOS transistor, fabricated in late 70’s, was the V-groove MOSFET. The channel was formed on the
side of an etch formed by selective chemical etching along one of the natural silicon crystal planes.
Gate
Source
n+
Source
n+
p -well
p -well
n- drift region
n+
Drain
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The Power MOSFET
RDSON is made up of the series combination of all the parts of the device between the source and drain where there is
a voltage drop due to the electron current flow. Some of these components are negligible in some voltage ranges.
Note that not all the components shown are linear (for example the JFET resistance or the channel and accumulation
layer resistances are voltage dependent), but in the linear region of operation, and for a first order approximation, we
can assume that these components behave as ‘resistors’.
RDS(ON) = Rs + Rn+ + Rch + Ra + RJFET + Rdrift + Rsub
+
RS
Source
Gate
n+
p well
Rch
n+
Ra
Rn+
Source
RJFET
p well
unipolar conduction
electron drift
n- drift region
Rdrift
Rsub
n+
Drain
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+
5
The Power MOSFET
As a switch, in the on-state, the power MOSFET should operate in the linear region where the on-state resistance is
minimal. Operation in the saturation region is highly undesirable, as the on-state losses would be too high with no
gain in current capability
Note that the saturation in the MOS theory refers to the saturation of the current (that is pinch-off of the channel). In
bipolar saturation refers to the voltage, more precisely the minimum collector-emitter voltage. The two ‘saturation
terms’ cannot be more different!
Saturation
Quasi-Linear
VGS5
Linear
VGS5 > VGS4 etc.
VGS4
VGS3
VGS2
VGS1
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≈
0
VGS > VGS(th)
VBR
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VDS
6
The Power MOSFET
The table below shows the approximate contribution of each of these resistances for two extreme devices, one
designed for a 30V and one designed for 600 V device. In general the package resistance Rs, the source resistance
Rn+ and the silicon substrate resistance Rsub, are negligible, but their effect in low-voltage, high current devices can
still be significant. The channel resistance Rch and the accumulation layer resistance Ra, play an important role,
especially for the low-voltage devices. These resistances are voltage dependent and they can only be assumed to be
constant in the linear region of the MOSFET. Once the drain voltage increases, and the device moves into the quasilinear and saturation regions, these resistance increase very significantly. The percentage values given below are
only valid for the linear region. Rdrift (which in the table below includes RJFET) is very important for both low voltage
(e.g. 30V) and high voltage devices (e.g. 600 V) but it is by far the single highest resistance in high voltage
structures.
RDS(on)
VDS=30V
VDS=600V
RS=7%
RS=0.5%
Rn+=6%
Rn+=0.5%
Rch=28%
Rch=1.5%
Ra=23%
Ra=0.5%
R*drift=29%
R*drift=96.5%
Rsub=7%
Rsub=0.5%
* RJFET is included in Rdrift
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The famous-infamous limit of silicon
The specific drift resistance is given by the drift of electrons through the n- drift layer.
Therefore, it can be calculated as:
Rspecific−drift =
VBR =
σ
=
Wd
qµ n N D
2
ε rε 0ξcritical
Rspecific−drift =
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Wd
Wcritical =
2qN D
4VBR
2
3
µ n ε r ε 0ξ critical
Wcritical =
2ε rε 0VBR 1
q
ND
1
2
2VBR
ξcritical
2.5
≈ 8.3 × 10 −9 VBR
Silicon
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Superjunction – A super-concept for
super-low on-state resistance
Rspecific−drift −sup erjunction =
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4 wVBR
2
µnε r ε 0ξ critical
≈ 1.98 × 10 −1 w5 / 4VBR
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Silicon −sup erjunction
9
Superjunction – A super-concept for
super-low on-state resistance
Rspecific−drift −sup erjunction =
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4 wVBR
2
µnε r ε 0ξ critical
≈ 1.98 × 10 −1 w5 / 4VBR
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Silicon −sup erjunction
10
The Cool MOS – based on
super-junction concept
Gate
Source
Source
n+
n+
p well
p
p well
n
p
w = 5 -10 um
n+
Drain
The doping of the n drift layer is
one order of magnitude higher
than in a classical power MOSFET
(e.g. 5e15cm-3 for 600V)
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The trench MOSFET
The trench MOSFET is a variant of a power MOSFET features vertical channels. The n+ sources are self-aligned to
the trench and the overall dimensions of the cell can be made much smaller than in the classical power DMOSFET.
That means that the channel density is considerably larger than in the classical power DMOSFET. This yields a
smaller channel resistance and as a result a smaller on-state resistance. The advantage of a smaller on-state resistance
is even more prominent at lower voltage ratings (e.g. 30V, 60V, 100V) where the channel resistance represents a very
significant contribution of the overall on-state resistance. Besides this, the current in the trench structure has a more
1D natural flow, avoiding bends and removing the parasitic JFET effect.
Channel
Source
Source
n+
p -well
n+
Rch ≅
L
( Z / A) µ ch Cox (VG − VT )
p -well
Gate
n- drift region
n+
Drain
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The IGBT equivalent circuit
The IGBT has within its structure three MOS- bipolar devices:
(i) The cascade MOSFET - PIN diode
(ii) MOS base current controlled - wide base PNP transistor
(iii) Parasitic MOS turn-on thyristor - must be always suppressed
Gate
Source/Cathode
Source/Cathode
n+
n+
p well
p well
p+
n- drift region
p+
Anode
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Trench IGBT Layout- Stripe or Hex ?
Hexagonal IGBT
Stripe IGBT
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Trench IGBT Cross Sections
SEM
Schematic
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The Hexagonal Trench Structure
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The Carriers Stored Gate Biploar
Transistor (CSGBT)
Hitachi’s variant of an IGBT which uses a trench structure with
enhanced PIN diode effect to increase the injection of electrons at
the cathode side thus improving the plasma distribution and
reducing the on-state losses considerably.
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The Field Stop (or Soft Punch-Through), PT and
NPT structures
PT - IGBT
NPT - IGBT
Gate
Source/Cathode
SPT - IGBT
Gate
Source/Cathode
n+
n+
n+
100µm
n- drift
100µm
15µm
p well
p well
p well
region
n buffer
Gate
Source/Cathode
n- drift
region
190µm
1- 2 µm
n- buffer – field stop
1µm
P transparent anode
(c)
250µm
p+ (substrate)
1µm
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(a)
P transparent anode
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The Field Stop (or Soft Punch-Through), PT and
NPT comparison
Structure
PT -IGBT
NPT -IGBT
SPT - IGBT
thin
thick
Thin
Epitaxial
Float zone (FZ)
Float Zone (FZ)
Buffer Layer
Thick and highly doped
N/A
Thin and lowly doped
P+ anode injector
Thick and highly doped
(whole substrate)
Thin and relatively lowly
doped
Thin and relatively lowly
doped
Lifetime killing
Injection efficiency
Injection efficiency
On-state losses
low
medium
low
Switching losses
high
medium
low
Turn-off tail
short
long
short
high
low
low
negative (mostly)
positive
positive
circuit
medium
large
large
bias
narrow
large
Large
Drift layer thickness
Wafer type (for 600 V
and 1.2 kV)
Bipolar gain control
Voltage overshoot
some applications)
(in
Temperature coefficient
SCSOA (short
conditions)
RBSOA (reverse
conditions)
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The trade-off between on-state voltage and turn-off energy losses for 1.2 kV DMOS
PT IGBT, the Trench IGBT and the Trench SPT IGBT.
30
25
Trench PT IGBT
E (mJ/cm 2)
20
Trench NPT IGBT
Trench SPT IGBT
15
DMOS PT IGBT
10
5
0
1
2
3
4
5
6
7
8
Anode Voltage (V)
@ J A = 100 A/cm2
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Evolution of Devices for Power/HV ICs
Power Capability
Vertical
IGBT
SUPERJUNCTION
LIGBT
Vertical
DMOS
RESURF
LDMOSFET
SOI LDMOS
& LIGBT
LDMOSFET
Lateral
MOS with
LDD
70s
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Evolution of
Power ICs
80s
80s & 90s
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90s
00
21
Example of a HVIC in motor control applications
– Hitachi ECN 3067
6 IGBTs ( 3 LS and 3 HS)
6 free-wheeling diodes
( 3 LS and 3 HS)
6 IGBTs and 6 anti-parallel diodes
integrated in one chip
Integrated Controller
containing:
PWM controller
Under voltage detection
Overcurrent protection
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2
)
Super-junction, BCD and Power IC Technologies
SOIPower
- SIMOX
technology
IC
Specific On-Resistance (mohm-cm
1000
100
High Voltage
Vertical Superjunction
10
Technology
Technologies
Si Limit
Lateral
Superjunction [39]
LIGBT [42]
BCD
Technologies
1
Low Voltage
Vertical Superjunction
0.1
10
100
1000
10000
Breakdown Voltage (V)
Si Limit
SJ (Philips '
02) [26]
SJ (Mitsubishi '
00) [28]
SJ (Fuji Electric '
05) [30]
SJ (Toshiba '
06) [32]
SJ (Fuji Electric '
06) [34]
SJ (Takaya '
05) [36]
Vertical RESURF MOSFET, ISPSD 04 [38]
BCD PMOS, Philips '
06 [2]
BCD (Renesas Semi 06) [3]
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Double
RESURF (ISPSD '
00) [17]
LIGBT (Letavic '
06) [42]
SJ (Denso '
06) [25]
SJ (Shindengen '
03) [27]
SJ (Infineon '
04) [29]
SJ (Toshiba '
04) [31]
SJ (Toyota '
04) [33]
Super 3D MOSFET (Denso '
06) [35]
UMOSFET, Miura '
05 [37]
Lateral SJ (Infineon '
06) [39]
BCD NMOS, Philips '
06 [2]
JI (Hardikar '
04) [16]
Course SampleThin Film SOI LDMOSFET (Letavic '
067) [41]
23
CMOS Line-Width (Micron)
BCD linewidth for different voltage rating
1
0.8
0.6
Atmel '02
SMARTIS
BCD Technologies
SOI-BCD
Toyota'04
Alcatel'02
Philips '02
A-BCD3
Toshiba'03
STM-BCD6'98
0.4
SOI-BCD
0.2
Philips '06
A-BCD9
TI-LBC6'01
0
0
50
Renesas Semi '06
100
150
200
250
300
Breakdown Voltage(V)
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A-BCD9, NMOS, Philips '
06 [2]
SOI-BCD, Renesas Semi '
06 [3]
BCD4, NMOS,Toyota '
04 [4]
BCD6, NMOS [5]
BCD6, NMOS [6]
BCD5, NMOS [7]
BCD6, NMOS [8]
BCD6, NMOS [9]
SMARTIS-BCD4
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Smart Power Technology roadmap
technology node
R&D in advanced research
130
TI
180
STM
250
NXP
350
Atmel/X-FAB
Denso,
bulk
Renesas, Toshiba
500
SOI
bulk
SOI
R&D/targeted
production
600
10
50
100
120
150
voltage
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