AN946: PCI-Express 4.0 Jitter
Requirements
PCI-Express (PCIe) is a point-to-point serial communication
standard that supports 2.5 GB/s, 5 GB/s, 8 GB/s and 16 GB/s data rates. All of these standards require a 100 MHz ± 300 ppm reference clock (Refclk). Given the evolution and refinement of these
PCIe standards, 4.0 specifically, there has been the addition of
the 16 GB/s (base 4.0 standard), the removal of separate clock,
and expansion of Gen1 and Gen2 transfer functions that creates
additional requirements for the reference clocks to be used in the
system at all data rates. In particular, the peaking value for 2.5 G
and 5 G data rates has been lowered to 0.01 dB to be in alignment with the 8 G and 16 G data rates. This specification also increases the number of possible filter scenarios for Gen1 (2.5 G)
data rates. Currently, this document is based on the PCI-Express
Base Specification 4.0 rev. 0.5. Since the generation 4 PCI-Express specifications are still pending finalization, this documentation will undergo updates as appropriate.
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KEY POINTS
• Describes new PCIe Gen 4 Requirements
• Demonstrates how to determine the filter
functions to process your data for
compliance
• Provides recommended test setup to make
your measurements
Rev. 0.1
AN946: PCI-Express 4.0 Jitter Requirements
Clocking Architectures
1. Clocking Architectures
In the application note, "AN562: PCI Express 3.0 Jitter Requirements", there are three different clocking architectures supported by previous PCI-express specifications. Each one of these clocking architectures comes with very different jitter filtering characteristics which
will impact the overall jitter performance of the system. For the PCI-Express 4.0 specification, there are only two types of architectures
supported: Common Refclk (CC) and Independent Refclk.
Common Refclk Rx Architecture
PCIe
Device A
PCIe
Link
100 MHz
±300ppm
PCIe
Device B
Independent Refclk Rx Architecture
PCIe
Device A
100 MHz
±300ppm
PCIe
Link
PCIe
Device B
100 MHz
±300ppm
Figure 1.1. Clocking Architectures
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AN946: PCI-Express 4.0 Jitter Requirements
Filters Applied to Data
2. Filters Applied to Data
The PCI-Express specifications have traditionally specified multiple types of filtering to be applied to raw data. For Gen4, two types of
filtering are required. The first is edge filtering of the raw data, which minimizes jitter caused by the finite sampling rate of the test equipment. This filtering is typically implemented by applying a 5 GHz bandwidth filter to the data. The second type of filtering, which is the
primary topic of this application note, is through the use of PLL difference functions that are inherent in the combination of RX PLL, TX
PLL, and CDR that are part of the PCI-Express system. The proper use of these filters will yield the effective Refclk jitter as it appears
at the sample latch of the receiver.
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Rev. 0.1 | 2
AN946: PCI-Express 4.0 Jitter Requirements
Reference Clock Jitter Requirements
3. Reference Clock Jitter Requirements
PCI-Express has very strict requirements for bit error rate of the system that is directly impacted by the jitter of the system. This jitter
can be in the form of both random and deterministic components that originate from various parts of the system. The most direct and
complex contributor to the jitter in the system is the Refclk. As such, the PCI-Express standards impose specific performance requirements on the Refclk to ensure that bit errors in the system are minimized. Because the Refclk can have such a major impact on the
system, a Refclk with low jitter can easily improve the overall performance of the system.
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AN946: PCI-Express 4.0 Jitter Requirements
Reference Clock Jitter Requirements
3.1 Gen4 Common Clocked Requirements
In the common clocked architecture, the Refclk is distributed to both the transmitter and receiver of the two PCI-Express devices in the
system. In this case, the overall transfer function for the Refclk that impacts the amount of jitter appearing at the receiver latch is defined by the difference function between the transmitter and receiver PLLs multiplied by the receiver latch high pass characteristic. This
is further impacted by the transport delay difference between the two inputs to the RX and TX PLLs. Since the delay impacts the transfer function, thus affecting the jitter seen by the CDR, the delay should be applied to the TX PLL and the RX PLL transfer function
separately and the worst case jitter from the two scenarios would be the result.
Figure 3.1. Gen4 Common Clock Requirements
() ( ()
( ))
H s = H 1 s e −s.T − H 2 s
()
( ()
( ))
H 3 s H (s) = H 2 s e −s.T − H 1 s
()
H3 s
PCI-Express 4.0 revision 0.5 has modified the filter scenarios for 2.5 G and 5 G, bringing them in alignment with the minimum 0.01 dB
peaking seen in the 8 G and 16 G specifications.
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Rev. 0.1 | 4
AN946: PCI-Express 4.0 Jitter Requirements
Reference Clock Jitter Requirements
Table 3.1. PLL and CDR Characteristics for All Data Rates Based on the PCI-Express 4.0 Specification
The jitter specifications in the table below continue to be the same values given in past specifications. The most notable difference being that the Gen1 (2.5 GB/s) specification is expressed as a pk-pk value rather than an RMS like the rest of the generations of the
specifications. This is due to the combination of the PLL to CDR bandwidths that exist. In particular with the CDR bandwidth being low
at 1.5 MHz and the PLL bandwidths being equal or higher, then that allows SSC effects to pass through to the CDR as deterministic
jitter. So, in that case it makes more sense to specify the jitter in terms of pk-pk rather than RMS.
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Rev. 0.1 | 5
AN946: PCI-Express 4.0 Jitter Requirements
Reference Clock Jitter Requirements
Table 3.2. Jitter Limits for Common Clock Architecture
Data Rate
CC Jitter Limit
2.5 G
108 ps pk-pk
5.0 G
3.1 ps RMS
8.0 G
1.0 ps RMS
16.0 G
< 1.0 ps RMS
3.2 PCI-Express 4.0 Independent Refclk Requirements
Currently the PCI-Express 4.0 specification does not define the jitter transfer function and jitter limits for the Independent Refclk architecture. Instead, the approach taken is to allow the implementation and associated reference clock jitter and transfer function trade-offs
that impact the overall transmitter jitter to be handled by the implementer. However, to minimize potential issues related to the system
clock, Silicon Labs recommends that the maximum PLL BW and CDR filters be used as outlined in PCI-Express 3.1 specification to
filter the reference clock jitter and that this result be less than the common clock jitter budgets divided by sqrt(2). The reason for dividing
the limit by sqrt(2) is that if both the separate transmit and receive clocks each meet this rms jitter limit, then their combined rms jitter
(which adds as the sqrt of the sum of the squares) will be less than the maximum system budget for Refclk jitter listed above.
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Rev. 0.1 | 6
AN946: PCI-Express 4.0 Jitter Requirements
Spread Spectrum Clocking and Bit Rate Tolerance
4. Spread Spectrum Clocking and Bit Rate Tolerance
PCIe devices are specified to reliably transmit data when using a Refclk with a spread spectrum modulation rate of 30–33 kHz and
modulation amplitude of 0 to –0.5% (i.e., downspread 0.5% in reference to the carrier frequency). Because each PCIe device must
transmit within a bit rate of ±300 ppm of each other, the same Refclk must be supplied to both devices if SSC is used. In some system
implementations, separate clocking architecture will therefore not work if SSC is turned on unless both clocks are synchronized to a
common source. When the system is SRIS capable, the CDRs will be designed with loop filter characteristics such that the SSC can be
tracked independently by the receiver allowing for SRIS support. Using SSC is possible for the Separate Reflck, Common Clocked RX
Architecture, and Data Clocked RX Architecture. In addition to the SSC modulation rate and modulation amplitude, there is also a requirement for the maximum rate of change of the frequency on a Refclk with SSC active at 1250 ppm/µs. Refclks with the SSC active
will need to meet additional phase jitter requirements at low frequency as shown in the table below.
Table 4.1. Limits for Phase Jitter from the Reference Clock with SSC Active
Frequency
Maximum Peak-to-Peak Phase Jitter (ps)
30 kHz
25000
100 kHz
1000
500 kHz
25
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Rev. 0.1 | 7
AN946: PCI-Express 4.0 Jitter Requirements
Refclk Test Setup
5. Refclk Test Setup
The reference clock test setup as defined in the 3.1 specification assumes that only the reference clock generator is present. It takes
the approach of measuring with the worst case system degradation in place using a 12-inch differential trace that is terminated by two 2
pF capacitors.
Figure 5.1. Refclk Test Setup
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Rev. 0.1 | 8
AN946: PCI-Express 4.0 Jitter Requirements
A Typical PCI Express Application
6. A Typical PCI Express Application
Silicon Labs offers a variety of clock devices that allows for flexible PCIe Refclk distribution. For example, the Si5338 I2C Programmable Any-Frequency, Any-Output Quad Clock Generator is an ideal device for generating PCIe clocks:
• Compliant with PCI Express 4.0 and legacy standards (2.1, 1.1)
• PCI Express 4.0 jitter = 0.12 ps RMS (10x lower than the requirement)
• Generates up to four 100 MHz HCSL output clocks but is programmable with other frequencies and signal formats. This allows one
clock device to generate PCIe Refclks and other board clocks of different frequencies and signal formats.
• Output frequencies are programmable per output from 5 MHz to 710 MHz.
• Independent VDDO for each output clock enables integrated level translation.
• Output signal formats are programmable per output as HCSL, LVDS, LVPECL or LVCMOS.
• Excellent jitter performance allows Refclk generation for Common Refclk RX, Data Clocked RX, and Separate Clock Architectures.
• Spread spectrum can be enabled or disabled per output with programmable modulation rate and modulation amplitude per output.
• Built-in HCSL terminations.
• Small 4x4 mm package
A typical use of the Si5338 in a PCIe application is shown in the figure below. In this example the Si5338 replaces a 100 MHz clock
oscillator with spread spectrum, a 1:2 HCSL buffer, a 66.6667 MHz clock oscillator, and a 125 MHz clock oscillator.
Motherboard
Add-In Board
PCIe
Device
CPU
Si5338 Quad Clock Generator
25 MHz
XTAL
+/- 100ppm
OSC
PLL
MultiSynth 0
66.66 MHz
LVCMOS
MultiSynth 1
100 MHz HCSL
MultiSynth 2
100 MHz HCSL
MultiSynth 3
PCIe
Device
125 MHz
LVCMOS
Ethernet
Figure 6.1. PCIe Application Using the Si5338 as the Refclk Generator
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Rev. 0.1 | 9
AN946: PCI-Express 4.0 Jitter Requirements
PCI Express Compliance Report
Appendix 1. PCI Express Compliance Report
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Rev. 0.1 | 10
PCI Express Compliance Report
Page 1 of 37
Data File Overview
File Type
Time Domain Differential
Waveform File
C:\tmp\Si5338_SN001_waveform_85C_MinV.bin
Waveform File Creation Date 2015-11-17 14:58:37 GMT-06:00
Edge Filtering
On
Clock Frequency
100.001 MHz
Number of Edges
256,252
Sample Interval
50.000 ps
Average Threshold Voltage
-542.760 μV
Jitter Summary
#
Class
Data
Rate
Architecture Specs
PLL1
BW
PLL1
Peak
PLL2
BW
PLL2
Peak
CDR
BW
Specification
CDR
Peak HF RMS LF RMS Pk-Pk
Analysis Result
HF RMS
LF RMS
Pk-Pk
Compliance
Result
19.95 fs
554.60 fs
PASS
1
GEN1
2.5 Gb/s Common Clock 4.0
1.5 MHz 0.01 dB 1.5 MHz 0.01 dB 1.5 MHz 0 dB
86 ps
60.02 fs
2
GEN1
2.5 Gb/s Common Clock 4.0
1.5 MHz 3 dB
1.5 MHz 0.01 dB 1.5 MHz 0 dB
86 ps
239.81 fs 198.77 fs 2.38 ps
PASS
3
GEN1
2.5 Gb/s Common Clock 4.0
22 MHz
0.01 dB 1.5 MHz 0.01 dB 1.5 MHz 0 dB
86 ps
573.60 fs 217.55 fs 5.15 ps
PASS
4
GEN1
2.5 Gb/s Common Clock 4.0
22 MHz
3 dB
86 ps
648.02 fs 233.76 fs 6.21 ps
PASS
5
GEN1
2.5 Gb/s Common Clock 4.0
1.5 MHz 0.01 dB 1.5 MHz 3 dB
1.5 MHz 0 dB
86 ps
239.81 fs 198.77 fs 2.38 ps
PASS
6
GEN1
2.5 Gb/s Common Clock 4.0
1.5 MHz 3 dB
1.5 MHz 3 dB
1.5 MHz 0 dB
86 ps
44.52 fs
PASS
7
GEN1
2.5 Gb/s Common Clock 4.0
22 MHz
0.01 dB 1.5 MHz 3 dB
1.5 MHz 0 dB
86 ps
689.57 fs 374.97 fs 6.50 ps
PASS
8
GEN1
2.5 Gb/s Common Clock 4.0
22 MHz
3 dB
1.5 MHz 0 dB
86 ps
760.26 fs 391.11 fs 7.17 ps
PASS
9
1.5 MHz 0.01 dB 1.5 MHz 0 dB
1.5 MHz 3 dB
25.35 fs
436.04 fs
GEN1
2.5 Gb/s Common Clock 4.0
1.5 MHz 0.01 dB 22 MHz
0.01 dB 1.5 MHz 0 dB
86 ps
573.60 fs 217.55 fs 5.15 ps
PASS
10 GEN1
2.5 Gb/s Common Clock 4.0
1.5 MHz 3 dB
22 MHz
0.01 dB 1.5 MHz 0 dB
86 ps
689.57 fs 374.97 fs 6.50 ps
PASS
11 GEN1
2.5 Gb/s Common Clock 4.0
22 MHz
0.01 dB 22 MHz
0.01 dB 1.5 MHz 0 dB
86 ps
497.98 fs 25.20 fs
5.10 ps
PASS
12 GEN1
2.5 Gb/s Common Clock 4.0
22 MHz
3 dB
0.01 dB 1.5 MHz 0 dB
86 ps
574.72 fs 43.42 fs
5.60 ps
PASS
13 GEN1
2.5 Gb/s Common Clock 4.0
1.5 MHz 0.01 dB 22 MHz
3 dB
1.5 MHz 0 dB
86 ps
648.02 fs 233.76 fs 6.21 ps
PASS
14 GEN1
2.5 Gb/s Common Clock 4.0
1.5 MHz 3 dB
22 MHz
3 dB
1.5 MHz 0 dB
86 ps
760.26 fs 391.11 fs 7.17 ps
PASS
15 GEN1
2.5 Gb/s Common Clock 4.0
22 MHz
0.01 dB 22 MHz
3 dB
1.5 MHz 0 dB
86 ps
574.72 fs 43.42 fs
5.60 ps
PASS
16 GEN1
2.5 Gb/s Common Clock 4.0
22 MHz
3 dB
3 dB
1.5 MHz 0 dB
86 ps
471.16 fs 25.46 fs
4.30 ps
PASS
17 GEN2
5 Gb/s
Common Clock 4.0
5 MHz
0.01 dB 8 MHz
0.01 dB 1.5 MHz 0 dB
3.1 ps
3 ps
243.31 fs 21.73 fs
2.20 ps
PASS
18 GEN2
5 Gb/s
Common Clock 4.0
5 MHz
1 dB
8 MHz
0.01 dB 1.5 MHz 0 dB
3.1 ps
3 ps
254.15 fs 28.20 fs
2.26 ps
PASS
19 GEN2
5 Gb/s
Common Clock 4.0
16 MHz
0.01 dB 8 MHz
0.01 dB 1.5 MHz 0 dB
3.1 ps
3 ps
396.38 fs 20.42 fs
3.65 ps
PASS
20 GEN2
5 Gb/s
Common Clock 4.0
16 MHz
1 dB
0.01 dB 1.5 MHz 0 dB
3.1 ps
3 ps
364.73 fs 28.46 fs
3.27 ps
PASS
21 GEN2
5 Gb/s
Common Clock 4.0
5 MHz
0.01 dB 8 MHz
3 dB
1.5 MHz 0 dB
3.1 ps
3 ps
231.64 fs 40.62 fs
2.03 ps
PASS
22 GEN2
5 Gb/s
Common Clock 4.0
5 MHz
1 dB
8 MHz
3 dB
1.5 MHz 0 dB
3.1 ps
3 ps
226.18 fs 42.08 fs
2.25 ps
PASS
23 GEN2
5 Gb/s
Common Clock 4.0
16 MHz
0.01 dB 8 MHz
3 dB
1.5 MHz 0 dB
3.1 ps
3 ps
427.45 fs 20.70 fs
3.94 ps
PASS
24 GEN2
5 Gb/s
Common Clock 4.0
16 MHz
1 dB
3 dB
1.5 MHz 0 dB
3.1 ps
3 ps
399.43 fs 12.57 fs
3.69 ps
PASS
25 GEN2
5 Gb/s
Common Clock 4.0
5 MHz
0.01 dB 16 MHz
0.01 dB 1.5 MHz 0 dB
3.1 ps
3 ps
386.06 fs 30.95 fs
3.51 ps
PASS
26 GEN2
5 Gb/s
Common Clock 4.0
5 MHz
1 dB
16 MHz
0.01 dB 1.5 MHz 0 dB
3.1 ps
3 ps
393.96 fs 36.14 fs
3.54 ps
PASS
27 GEN2
5 Gb/s
Common Clock 4.0
16 MHz
0.01 dB 16 MHz
0.01 dB 1.5 MHz 0 dB
3.1 ps
3 ps
433.26 fs 11.25 fs
4.32 ps
PASS
28 GEN2
5 Gb/s
Common Clock 4.0
16 MHz
1 dB
0.01 dB 1.5 MHz 0 dB
3.1 ps
3 ps
441.61 fs 19.21 fs
4.29 ps
PASS
29 GEN2
5 Gb/s
Common Clock 4.0
5 MHz
0.01 dB 16 MHz
3 dB
1.5 MHz 0 dB
3.1 ps
3 ps
369.23 fs 40.40 fs
3.40 ps
PASS
30 GEN2
5 Gb/s
Common Clock 4.0
5 MHz
1 dB
16 MHz
3 dB
1.5 MHz 0 dB
3.1 ps
3 ps
391.07 fs 44.44 fs
3.63 ps
PASS
31 GEN2
5 Gb/s
Common Clock 4.0
16 MHz
0.01 dB 16 MHz
3 dB
1.5 MHz 0 dB
3.1 ps
3 ps
475.97 fs 20.60 fs
4.45 ps
PASS
32 GEN2
5 Gb/s
Common Clock 4.0
16 MHz
1 dB
3 dB
1.5 MHz 0 dB
3.1 ps
3 ps
429.51 fs 13.87 fs
3.95 ps
PASS
33 GEN3
8 Gb/s
Common Clock 3.1
4.0
2 MHz
0.01 dB 2 MHz
0.01 dB 10 MHz
0 dB
1 ps
63.94 fs
4.93 fs
572.50 fs
34 GEN3
8 Gb/s
Common Clock 3.1
4.0
2 MHz
2 dB
2 MHz
0.01 dB 10 MHz
0 dB
1 ps
71.63 fs
26.13 fs
693.36 fs
35 GEN3
8 Gb/s
Common Clock 3.1
4.0
4 MHz
0.01 dB 2 MHz
0.01 dB 10 MHz
0 dB
1 ps
117.69 fs 20.54 fs
22 MHz
22 MHz
8 MHz
8 MHz
16 MHz
16 MHz
Prepared by Silicon Labs PCIe Clock Jitter Tool v0.21 on 2015-11-17 15:19:35 GMT-06:00
Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc.
1.08 ps
PASS
PASS
PASS
PCI Express Compliance Report
Page 2 of 37
#
Class
Data
Rate
Architecture Specs
PLL1
BW
PLL1
Peak
PLL2
BW
2 MHz
Specification
CDR
Peak HF RMS LF RMS Pk-Pk
HF RMS
LF RMS
Pk-Pk
0.01 dB 10 MHz
0 dB
1 ps
97.40 fs
34.62 fs
898.37 fs
PLL2
Peak
CDR
BW
Analysis Result
Compliance
Result
36 GEN3
8 Gb/s
Common Clock 3.1
4.0
4 MHz
2 dB
37 GEN3
8 Gb/s
Common Clock 3.1
4.0
2 MHz
0.01 dB 2 MHz
1 dB
10 MHz
0 dB
1 ps
65.38 fs
14.58 fs
604.16 fs
38 GEN3
8 Gb/s
Common Clock 3.1
4.0
2 MHz
2 dB
2 MHz
1 dB
10 MHz
0 dB
1 ps
57.64 fs
15.96 fs
549.71 fs
39 GEN3
8 Gb/s
Common Clock 3.1
4.0
4 MHz
0.01 dB 2 MHz
1 dB
10 MHz
0 dB
1 ps
123.25 fs 28.35 fs
1.17 ps
40 GEN3
8 Gb/s
Common Clock 3.1
4.0
4 MHz
2 dB
1 dB
10 MHz
0 dB
1 ps
103.18 fs 39.49 fs
934.67 fs
41 GEN3
8 Gb/s
Common Clock 3.1
4.0
2 MHz
0.01 dB 5 MHz
0.01 dB 10 MHz
0 dB
1 ps
143.03 fs 24.01 fs
1.32 ps
42 GEN3
8 Gb/s
Common Clock 3.1
4.0
2 MHz
2 dB
5 MHz
0.01 dB 10 MHz
0 dB
1 ps
156.07 fs 41.49 fs
1.52 ps
43 GEN3
8 Gb/s
Common Clock 3.1
4.0
4 MHz
0.01 dB 5 MHz
0.01 dB 10 MHz
0 dB
1 ps
145.17 fs 9.04 fs
1.32 ps
44 GEN3
8 Gb/s
Common Clock 3.1
4.0
4 MHz
2 dB
0.01 dB 10 MHz
0 dB
1 ps
152.08 fs 17.79 fs
1.38 ps
45 GEN3
8 Gb/s
Common Clock 3.1
4.0
2 MHz
0.01 dB 5 MHz
1 dB
10 MHz
0 dB
1 ps
129.31 fs 30.67 fs
1.20 ps
46 GEN3
8 Gb/s
Common Clock 3.1
4.0
2 MHz
2 dB
5 MHz
1 dB
10 MHz
0 dB
1 ps
144.39 fs 44.61 fs
1.39 ps
47 GEN3
8 Gb/s
Common Clock 3.1
4.0
4 MHz
0.01 dB 5 MHz
1 dB
10 MHz
0 dB
1 ps
132.39 fs 15.07 fs
1.21 ps
48 GEN3
8 Gb/s
Common Clock 3.1
4.0
4 MHz
2 dB
1 dB
10 MHz
0 dB
1 ps
130.22 fs 11.11 fs
1.14 ps
49 GEN4
16 Gb/s
Common Clock 4.0
2 MHz
0.01 dB 2 MHz
0.01 dB 10 MHz
0 dB
1 ps
63.94 fs
4.93 fs
572.50 fs
PASS
50 GEN4
16 Gb/s
Common Clock 4.0
2 MHz
2 dB
2 MHz
0.01 dB 10 MHz
0 dB
1 ps
71.63 fs
26.13 fs
693.36 fs
PASS
51 GEN4
16 Gb/s
Common Clock 4.0
4 MHz
0.01 dB 2 MHz
0.01 dB 10 MHz
0 dB
1 ps
117.69 fs 20.54 fs
1.08 ps
PASS
52 GEN4
16 Gb/s
Common Clock 4.0
4 MHz
2 dB
0.01 dB 10 MHz
0 dB
1 ps
97.40 fs
34.62 fs
898.37 fs
PASS
53 GEN4
16 Gb/s
Common Clock 4.0
2 MHz
0.01 dB 2 MHz
1 dB
10 MHz
0 dB
1 ps
65.38 fs
14.58 fs
604.16 fs
PASS
54 GEN4
16 Gb/s
Common Clock 4.0
2 MHz
2 dB
2 MHz
1 dB
10 MHz
0 dB
1 ps
57.64 fs
15.96 fs
549.71 fs
PASS
55 GEN4
16 Gb/s
Common Clock 4.0
4 MHz
0.01 dB 2 MHz
1 dB
10 MHz
0 dB
1 ps
123.25 fs 28.35 fs
1.17 ps
PASS
56 GEN4
16 Gb/s
Common Clock 4.0
4 MHz
2 dB
1 dB
10 MHz
0 dB
1 ps
103.18 fs 39.49 fs
934.67 fs
PASS
57 GEN4
16 Gb/s
Common Clock 4.0
2 MHz
0.01 dB 5 MHz
0.01 dB 10 MHz
0 dB
1 ps
143.03 fs 24.01 fs
1.32 ps
PASS
58 GEN4
16 Gb/s
Common Clock 4.0
2 MHz
2 dB
5 MHz
0.01 dB 10 MHz
0 dB
1 ps
156.07 fs 41.49 fs
1.52 ps
PASS
59 GEN4
16 Gb/s
Common Clock 4.0
4 MHz
0.01 dB 5 MHz
0.01 dB 10 MHz
0 dB
1 ps
145.17 fs 9.04 fs
1.32 ps
PASS
60 GEN4
16 Gb/s
Common Clock 4.0
4 MHz
2 dB
0.01 dB 10 MHz
0 dB
1 ps
152.08 fs 17.79 fs
1.38 ps
PASS
61 GEN4
16 Gb/s
Common Clock 4.0
2 MHz
0.01 dB 5 MHz
1 dB
10 MHz
0 dB
1 ps
129.31 fs 30.67 fs
1.20 ps
PASS
62 GEN4
16 Gb/s
Common Clock 4.0
2 MHz
2 dB
5 MHz
1 dB
10 MHz
0 dB
1 ps
144.39 fs 44.61 fs
1.39 ps
PASS
63 GEN4
16 Gb/s
Common Clock 4.0
4 MHz
0.01 dB 5 MHz
1 dB
10 MHz
0 dB
1 ps
132.39 fs 15.07 fs
1.21 ps
PASS
64 GEN4
16 Gb/s
Common Clock 4.0
4 MHz
2 dB
1 dB
10 MHz
0 dB
1 ps
130.22 fs 11.11 fs
1.14 ps
PASS
2 MHz
5 MHz
5 MHz
2 MHz
2 MHz
5 MHz
5 MHz
PASS
PASS
PASS
PASS
PASS
PASS
PASS
PASS
PASS
PASS
PASS
PASS
PASS
(1) Spread Spectrum Clocking (SSC) separation is intended to remove the energy associated with the spread spectrum (30KHz-33KHz) in the low frequency range (0.01-1.5MHz)
specified by the PCI-Express Base Specification in order to define separate low frequency Rj and Dj components. This feature should be turned off for data sets that do not have
spread spectrum clocking.
Prepared by Silicon Labs PCIe Clock Jitter Tool v0.21 on 2015-11-17 15:19:35 GMT-06:00
Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc.
PCI Express Compliance Report
Page 3 of 37
Unfiltered Waveform Jitter Information vs. Time
Time Interval Error
Period
Cycle-to-Cycle
Reference Clock AC Specifications
Specification
Analysis Result
Test
Min
Max
Min
Max
Avg
Compliance
Result
Rising Edge Rate
.6 V/ns
4 V/ns
1.49 V/ns
1.57 V/ns
1.53 V/ns
PASS
Falling Edge Rate
.6 V/ns
4 V/ns
1.49 V/ns
1.57 V/ns
1.52 V/ns
PASS
Diff Input High
150 mV
225.70 mV
225.70 mV
225.70 mV
PASS
Diff Input Low
-150 mV
-225.70 mV -225.70 mV -225.70 mV
PASS
Average Clock Period Accuracy -300 ppm 2,800 ppm N/A
N/A
-10 ppm
PASS
Absolute Period
9.847 ns
10.203 ns
9.996 ns
10.004 ns
10.000 ns
PASS
Cycle to Cycle Jitter
150 ps
0.01 fs
7.50 ps
1.23 ps
PASS
Duty Cycle
40 %
60 %
49.5 %
50.0 %
49.9 %
PASS
Detailed Jitter Reports
In the pages that follow, jitter response is analyzed for each selected standard, architecture and filter parameter combination.
Prepared by Silicon Labs PCIe Clock Jitter Tool v0.21 on 2015-11-17 15:19:35 GMT-06:00
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PCI Express Compliance Report
Page 4 of 37
# Class Data Rate Architecture Specs PLL1 BW PLL1 Pk PLL2 BW PLL2 PK CDR BW CDR PK Delay SSC Separation
1 GEN1
2.5 Gb/s
Common Clock 4.0
1.5 MHz
0.01 dB
1.5 MHz
Specification
Analysis Compliance
Result
Result
Refclk HF RMS Jitter
60.023 fs
N/A
Refclk LF RMS Jitter
19.947 fs
N/A
554.597 fs
PASS
Test
Pk-pk Phase Jitter at BER 10^-6 86 ps
0.01 dB
1.5 MHz
Low Frequency Phase Jitter
0 dB
10 ns
N/A
High Frequency Phase Jitter
Filter Magnitude Responses
# Class Data Rate Architecture Specs PLL1 BW PLL1 Pk PLL2 BW PLL2 PK CDR BW CDR PK Delay SSC Separation
2 GEN1
2.5 Gb/s
Common Clock 4.0
1.5 MHz
3 dB
1.5 MHz
Specification
Analysis Compliance
Result
Result
Refclk HF RMS Jitter
239.806 fs
N/A
Refclk LF RMS Jitter
198.772 fs
N/A
Test
Pk-pk Phase Jitter at BER 10^-6 86 ps
2.381 ps
Low Frequency Phase Jitter
0.01 dB
1.5 MHz
0 dB
10 ns
N/A
PASS
High Frequency Phase Jitter
Filter Magnitude Responses
Prepared by Silicon Labs PCIe Clock Jitter Tool v0.21 on 2015-11-17 15:19:35 GMT-06:00
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PCI Express Compliance Report
Page 5 of 37
# Class Data Rate Architecture Specs PLL1 BW PLL1 Pk PLL2 BW PLL2 PK CDR BW CDR PK Delay SSC Separation
3 GEN1
2.5 Gb/s
Common Clock 4.0
22 MHz
0.01 dB
1.5 MHz
Specification
Analysis Compliance
Result
Result
Refclk HF RMS Jitter
573.602 fs
N/A
Refclk LF RMS Jitter
217.550 fs
N/A
Test
Pk-pk Phase Jitter at BER 10^-6 86 ps
5.154 ps
0.01 dB
1.5 MHz
0 dB
10 ns
N/A
PASS
Low Frequency Phase Jitter
High Frequency Phase Jitter
Filter Magnitude Responses
# Class Data Rate Architecture Specs PLL1 BW PLL1 Pk PLL2 BW PLL2 PK CDR BW CDR PK Delay SSC Separation
4 GEN1
2.5 Gb/s
Common Clock 4.0
22 MHz
3 dB
1.5 MHz
Specification
Analysis Compliance
Result
Result
Refclk HF RMS Jitter
648.024 fs
N/A
Refclk LF RMS Jitter
233.763 fs
N/A
Test
Pk-pk Phase Jitter at BER 10^-6 86 ps
6.212 ps
Low Frequency Phase Jitter
0.01 dB
1.5 MHz
0 dB
10 ns
N/A
PASS
High Frequency Phase Jitter
Filter Magnitude Responses
Prepared by Silicon Labs PCIe Clock Jitter Tool v0.21 on 2015-11-17 15:19:35 GMT-06:00
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PCI Express Compliance Report
Page 6 of 37
# Class Data Rate Architecture Specs PLL1 BW PLL1 Pk PLL2 BW PLL2 PK CDR BW CDR PK Delay SSC Separation
5 GEN1
2.5 Gb/s
Common Clock 4.0
1.5 MHz
0.01 dB
1.5 MHz
Specification
Analysis Compliance
Result
Result
Refclk HF RMS Jitter
239.806 fs
N/A
Refclk LF RMS Jitter
198.772 fs
N/A
Test
Pk-pk Phase Jitter at BER 10^-6 86 ps
2.381 ps
3 dB
1.5 MHz
0 dB
10 ns
N/A
PASS
Low Frequency Phase Jitter
High Frequency Phase Jitter
Filter Magnitude Responses
# Class Data Rate Architecture Specs PLL1 BW PLL1 Pk PLL2 BW PLL2 PK CDR BW CDR PK Delay SSC Separation
6 GEN1
2.5 Gb/s
Common Clock 4.0
1.5 MHz
3 dB
1.5 MHz
Specification
Analysis Compliance
Result
Result
Refclk HF RMS Jitter
44.524 fs
N/A
Refclk LF RMS Jitter
25.348 fs
N/A
436.036 fs
PASS
Test
Pk-pk Phase Jitter at BER 10^-6 86 ps
Low Frequency Phase Jitter
3 dB
1.5 MHz
0 dB
10 ns
N/A
High Frequency Phase Jitter
Filter Magnitude Responses
Prepared by Silicon Labs PCIe Clock Jitter Tool v0.21 on 2015-11-17 15:19:35 GMT-06:00
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PCI Express Compliance Report
Page 7 of 37
# Class Data Rate Architecture Specs PLL1 BW PLL1 Pk PLL2 BW PLL2 PK CDR BW CDR PK Delay SSC Separation
7 GEN1
2.5 Gb/s
Common Clock 4.0
22 MHz
0.01 dB
1.5 MHz
Specification
Analysis Compliance
Result
Result
Refclk HF RMS Jitter
689.567 fs
N/A
Refclk LF RMS Jitter
374.969 fs
N/A
Test
Pk-pk Phase Jitter at BER 10^-6 86 ps
6.495 ps
3 dB
1.5 MHz
0 dB
10 ns
N/A
PASS
Low Frequency Phase Jitter
High Frequency Phase Jitter
Filter Magnitude Responses
# Class Data Rate Architecture Specs PLL1 BW PLL1 Pk PLL2 BW PLL2 PK CDR BW CDR PK Delay SSC Separation
8 GEN1
2.5 Gb/s
Common Clock 4.0
22 MHz
3 dB
1.5 MHz
Specification
Analysis Compliance
Result
Result
Refclk HF RMS Jitter
760.260 fs
N/A
Refclk LF RMS Jitter
391.111 fs
N/A
Test
Pk-pk Phase Jitter at BER 10^-6 86 ps
7.166 ps
Low Frequency Phase Jitter
3 dB
1.5 MHz
0 dB
10 ns
N/A
PASS
High Frequency Phase Jitter
Filter Magnitude Responses
Prepared by Silicon Labs PCIe Clock Jitter Tool v0.21 on 2015-11-17 15:19:35 GMT-06:00
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PCI Express Compliance Report
Page 8 of 37
# Class Data Rate Architecture Specs PLL1 BW PLL1 Pk PLL2 BW PLL2 PK CDR BW CDR PK Delay SSC Separation
9 GEN1
2.5 Gb/s
Common Clock 4.0
1.5 MHz
0.01 dB
22 MHz
Specification
Analysis Compliance
Result
Result
Refclk HF RMS Jitter
573.602 fs
N/A
Refclk LF RMS Jitter
217.550 fs
N/A
Test
Pk-pk Phase Jitter at BER 10^-6 86 ps
5.154 ps
0.01 dB
1.5 MHz
0 dB
10 ns
N/A
PASS
Low Frequency Phase Jitter
High Frequency Phase Jitter
Filter Magnitude Responses
#
Class Data Rate Architecture Specs PLL1 BW PLL1 Pk PLL2 BW PLL2 PK CDR BW CDR PK Delay SSC Separation
10 GEN1
2.5 Gb/s
Common Clock 4.0
1.5 MHz
3 dB
22 MHz
Specification
Analysis Compliance
Result
Result
Refclk HF RMS Jitter
689.567 fs
N/A
Refclk LF RMS Jitter
374.969 fs
N/A
Test
Pk-pk Phase Jitter at BER 10^-6 86 ps
6.495 ps
Low Frequency Phase Jitter
0.01 dB
1.5 MHz
0 dB
10 ns
N/A
PASS
High Frequency Phase Jitter
Filter Magnitude Responses
Prepared by Silicon Labs PCIe Clock Jitter Tool v0.21 on 2015-11-17 15:19:35 GMT-06:00
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PCI Express Compliance Report
Page 9 of 37
#
Class Data Rate Architecture Specs PLL1 BW PLL1 Pk PLL2 BW PLL2 PK CDR BW CDR PK Delay SSC Separation
11 GEN1
2.5 Gb/s
Common Clock 4.0
22 MHz
0.01 dB
22 MHz
Specification
Analysis Compliance
Result
Result
Refclk HF RMS Jitter
497.976 fs
N/A
Refclk LF RMS Jitter
25.199 fs
N/A
5.101 ps
PASS
Test
Pk-pk Phase Jitter at BER 10^-6 86 ps
0.01 dB
1.5 MHz
Low Frequency Phase Jitter
0 dB
10 ns
N/A
High Frequency Phase Jitter
Filter Magnitude Responses
#
Class Data Rate Architecture Specs PLL1 BW PLL1 Pk PLL2 BW PLL2 PK CDR BW CDR PK Delay SSC Separation
12 GEN1
2.5 Gb/s
Common Clock 4.0
22 MHz
3 dB
22 MHz
Specification
Analysis Compliance
Result
Result
Refclk HF RMS Jitter
574.715 fs
N/A
Refclk LF RMS Jitter
43.418 fs
N/A
5.599 ps
PASS
Test
Pk-pk Phase Jitter at BER 10^-6 86 ps
Low Frequency Phase Jitter
0.01 dB
1.5 MHz
0 dB
10 ns
N/A
High Frequency Phase Jitter
Filter Magnitude Responses
Prepared by Silicon Labs PCIe Clock Jitter Tool v0.21 on 2015-11-17 15:19:35 GMT-06:00
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PCI Express Compliance Report
Page 10 of 37
#
Class Data Rate Architecture Specs PLL1 BW PLL1 Pk PLL2 BW PLL2 PK CDR BW CDR PK Delay SSC Separation
13 GEN1
2.5 Gb/s
Common Clock 4.0
1.5 MHz
0.01 dB
22 MHz
Specification
Analysis Compliance
Result
Result
Refclk HF RMS Jitter
648.024 fs
N/A
Refclk LF RMS Jitter
233.763 fs
N/A
Test
Pk-pk Phase Jitter at BER 10^-6 86 ps
6.212 ps
3 dB
1.5 MHz
0 dB
10 ns
N/A
PASS
Low Frequency Phase Jitter
High Frequency Phase Jitter
Filter Magnitude Responses
#
Class Data Rate Architecture Specs PLL1 BW PLL1 Pk PLL2 BW PLL2 PK CDR BW CDR PK Delay SSC Separation
14 GEN1
2.5 Gb/s
Common Clock 4.0
1.5 MHz
3 dB
22 MHz
Specification
Analysis Compliance
Result
Result
Refclk HF RMS Jitter
760.260 fs
N/A
Refclk LF RMS Jitter
391.111 fs
N/A
Test
Pk-pk Phase Jitter at BER 10^-6 86 ps
7.166 ps
Low Frequency Phase Jitter
3 dB
1.5 MHz
0 dB
10 ns
N/A
PASS
High Frequency Phase Jitter
Filter Magnitude Responses
Prepared by Silicon Labs PCIe Clock Jitter Tool v0.21 on 2015-11-17 15:19:35 GMT-06:00
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PCI Express Compliance Report
Page 11 of 37
#
Class Data Rate Architecture Specs PLL1 BW PLL1 Pk PLL2 BW PLL2 PK CDR BW CDR PK Delay SSC Separation
15 GEN1
2.5 Gb/s
Common Clock 4.0
22 MHz
0.01 dB
22 MHz
Specification
Analysis Compliance
Result
Result
Refclk HF RMS Jitter
574.715 fs
N/A
Refclk LF RMS Jitter
43.418 fs
N/A
5.599 ps
PASS
Test
Pk-pk Phase Jitter at BER 10^-6 86 ps
3 dB
1.5 MHz
Low Frequency Phase Jitter
0 dB
10 ns
N/A
High Frequency Phase Jitter
Filter Magnitude Responses
#
Class Data Rate Architecture Specs PLL1 BW PLL1 Pk PLL2 BW PLL2 PK CDR BW CDR PK Delay SSC Separation
16 GEN1
2.5 Gb/s
Common Clock 4.0
22 MHz
3 dB
22 MHz
Specification
Analysis Compliance
Result
Result
Refclk HF RMS Jitter
471.157 fs
N/A
Refclk LF RMS Jitter
25.460 fs
N/A
4.298 ps
PASS
Test
Pk-pk Phase Jitter at BER 10^-6 86 ps
Low Frequency Phase Jitter
3 dB
1.5 MHz
0 dB
10 ns
N/A
High Frequency Phase Jitter
Filter Magnitude Responses
Prepared by Silicon Labs PCIe Clock Jitter Tool v0.21 on 2015-11-17 15:19:35 GMT-06:00
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PCI Express Compliance Report
Page 12 of 37
#
Class Data Rate Architecture Specs PLL1 BW PLL1 Pk PLL2 BW PLL2 PK CDR BW CDR PK Delay SSC Separation
17 GEN2
5 Gb/s
Common Clock 4.0
5 MHz
0.01 dB
8 MHz
Specification
Analysis Compliance
Result
Result
Refclk HF RMS Jitter
3.1 ps
243.313 fs
PASS
Refclk LF RMS Jitter
3 ps
21.727 fs
PASS
2.198 ps
N/A
Test
Pk-pk Phase Jitter at BER 10^-6 0.01 dB
1.5 MHz
Low Frequency Phase Jitter
0 dB
12 ns
N/A
High Frequency Phase Jitter
Filter Magnitude Responses
#
Class Data Rate Architecture Specs PLL1 BW PLL1 Pk PLL2 BW PLL2 PK CDR BW CDR PK Delay SSC Separation
18 GEN2
5 Gb/s
Common Clock 4.0
5 MHz
1 dB
8 MHz
Specification
Analysis Compliance
Result
Result
Refclk HF RMS Jitter
3.1 ps
254.149 fs
PASS
Refclk LF RMS Jitter
3 ps
28.200 fs
PASS
2.257 ps
N/A
Test
Pk-pk Phase Jitter at BER 10^-6 Low Frequency Phase Jitter
0.01 dB
1.5 MHz
0 dB
12 ns
N/A
High Frequency Phase Jitter
Filter Magnitude Responses
Prepared by Silicon Labs PCIe Clock Jitter Tool v0.21 on 2015-11-17 15:19:35 GMT-06:00
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PCI Express Compliance Report
Page 13 of 37
#
Class Data Rate Architecture Specs PLL1 BW PLL1 Pk PLL2 BW PLL2 PK CDR BW CDR PK Delay SSC Separation
19 GEN2
5 Gb/s
Common Clock 4.0
16 MHz
0.01 dB
8 MHz
Specification
Analysis Compliance
Result
Result
Refclk HF RMS Jitter
3.1 ps
396.378 fs
PASS
Refclk LF RMS Jitter
3 ps
20.416 fs
PASS
3.651 ps
N/A
Test
Pk-pk Phase Jitter at BER 10^-6 0.01 dB
1.5 MHz
Low Frequency Phase Jitter
0 dB
12 ns
N/A
High Frequency Phase Jitter
Filter Magnitude Responses
#
Class Data Rate Architecture Specs PLL1 BW PLL1 Pk PLL2 BW PLL2 PK CDR BW CDR PK Delay SSC Separation
20 GEN2
5 Gb/s
Common Clock 4.0
16 MHz
1 dB
8 MHz
Specification
Analysis Compliance
Result
Result
Refclk HF RMS Jitter
3.1 ps
364.734 fs
PASS
Refclk LF RMS Jitter
3 ps
28.464 fs
PASS
3.266 ps
N/A
Test
Pk-pk Phase Jitter at BER 10^-6 Low Frequency Phase Jitter
0.01 dB
1.5 MHz
0 dB
12 ns
N/A
High Frequency Phase Jitter
Filter Magnitude Responses
Prepared by Silicon Labs PCIe Clock Jitter Tool v0.21 on 2015-11-17 15:19:35 GMT-06:00
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PCI Express Compliance Report
Page 14 of 37
#
Class Data Rate Architecture Specs PLL1 BW PLL1 Pk PLL2 BW PLL2 PK CDR BW CDR PK Delay SSC Separation
21 GEN2
5 Gb/s
Common Clock 4.0
5 MHz
0.01 dB
8 MHz
Specification
Analysis Compliance
Result
Result
Refclk HF RMS Jitter
3.1 ps
231.640 fs
PASS
Refclk LF RMS Jitter
3 ps
40.615 fs
PASS
2.029 ps
N/A
Test
Pk-pk Phase Jitter at BER 10^-6 3 dB
1.5 MHz
Low Frequency Phase Jitter
0 dB
12 ns
N/A
High Frequency Phase Jitter
Filter Magnitude Responses
#
Class Data Rate Architecture Specs PLL1 BW PLL1 Pk PLL2 BW PLL2 PK CDR BW CDR PK Delay SSC Separation
22 GEN2
5 Gb/s
Common Clock 4.0
5 MHz
1 dB
8 MHz
Specification
Analysis Compliance
Result
Result
Refclk HF RMS Jitter
3.1 ps
226.183 fs
PASS
Refclk LF RMS Jitter
3 ps
42.077 fs
PASS
2.251 ps
N/A
Test
Pk-pk Phase Jitter at BER 10^-6 Low Frequency Phase Jitter
3 dB
1.5 MHz
0 dB
12 ns
N/A
High Frequency Phase Jitter
Filter Magnitude Responses
Prepared by Silicon Labs PCIe Clock Jitter Tool v0.21 on 2015-11-17 15:19:35 GMT-06:00
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PCI Express Compliance Report
Page 15 of 37
#
Class Data Rate Architecture Specs PLL1 BW PLL1 Pk PLL2 BW PLL2 PK CDR BW CDR PK Delay SSC Separation
23 GEN2
5 Gb/s
Common Clock 4.0
16 MHz
0.01 dB
8 MHz
Specification
Analysis Compliance
Result
Result
Refclk HF RMS Jitter
3.1 ps
427.453 fs
PASS
Refclk LF RMS Jitter
3 ps
20.700 fs
PASS
3.944 ps
N/A
Test
Pk-pk Phase Jitter at BER 10^-6 3 dB
1.5 MHz
Low Frequency Phase Jitter
0 dB
12 ns
N/A
High Frequency Phase Jitter
Filter Magnitude Responses
#
Class Data Rate Architecture Specs PLL1 BW PLL1 Pk PLL2 BW PLL2 PK CDR BW CDR PK Delay SSC Separation
24 GEN2
5 Gb/s
Common Clock 4.0
16 MHz
1 dB
8 MHz
Specification
Analysis Compliance
Result
Result
Refclk HF RMS Jitter
3.1 ps
399.430 fs
PASS
Refclk LF RMS Jitter
3 ps
12.569 fs
PASS
3.692 ps
N/A
Test
Pk-pk Phase Jitter at BER 10^-6 Low Frequency Phase Jitter
3 dB
1.5 MHz
0 dB
12 ns
N/A
High Frequency Phase Jitter
Filter Magnitude Responses
Prepared by Silicon Labs PCIe Clock Jitter Tool v0.21 on 2015-11-17 15:19:35 GMT-06:00
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PCI Express Compliance Report
Page 16 of 37
#
Class Data Rate Architecture Specs PLL1 BW PLL1 Pk PLL2 BW PLL2 PK CDR BW CDR PK Delay SSC Separation
25 GEN2
5 Gb/s
Common Clock 4.0
5 MHz
0.01 dB
16 MHz
Specification
Analysis Compliance
Result
Result
Refclk HF RMS Jitter
3.1 ps
386.064 fs
PASS
Refclk LF RMS Jitter
3 ps
30.951 fs
PASS
3.507 ps
N/A
Test
Pk-pk Phase Jitter at BER 10^-6 0.01 dB
1.5 MHz
Low Frequency Phase Jitter
0 dB
12 ns
N/A
High Frequency Phase Jitter
Filter Magnitude Responses
#
Class Data Rate Architecture Specs PLL1 BW PLL1 Pk PLL2 BW PLL2 PK CDR BW CDR PK Delay SSC Separation
26 GEN2
5 Gb/s
Common Clock 4.0
5 MHz
1 dB
16 MHz
Specification
Analysis Compliance
Result
Result
Refclk HF RMS Jitter
3.1 ps
393.960 fs
PASS
Refclk LF RMS Jitter
3 ps
36.140 fs
PASS
3.538 ps
N/A
Test
Pk-pk Phase Jitter at BER 10^-6 Low Frequency Phase Jitter
0.01 dB
1.5 MHz
0 dB
12 ns
N/A
High Frequency Phase Jitter
Filter Magnitude Responses
Prepared by Silicon Labs PCIe Clock Jitter Tool v0.21 on 2015-11-17 15:19:35 GMT-06:00
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PCI Express Compliance Report
Page 17 of 37
#
Class Data Rate Architecture Specs PLL1 BW PLL1 Pk PLL2 BW PLL2 PK CDR BW CDR PK Delay SSC Separation
27 GEN2
5 Gb/s
Common Clock 4.0
16 MHz
0.01 dB
16 MHz
Specification
Analysis Compliance
Result
Result
Refclk HF RMS Jitter
3.1 ps
433.262 fs
PASS
Refclk LF RMS Jitter
3 ps
11.253 fs
PASS
4.319 ps
N/A
Test
Pk-pk Phase Jitter at BER 10^-6 0.01 dB
1.5 MHz
Low Frequency Phase Jitter
0 dB
12 ns
N/A
High Frequency Phase Jitter
Filter Magnitude Responses
#
Class Data Rate Architecture Specs PLL1 BW PLL1 Pk PLL2 BW PLL2 PK CDR BW CDR PK Delay SSC Separation
28 GEN2
5 Gb/s
Common Clock 4.0
16 MHz
1 dB
16 MHz
Specification
Analysis Compliance
Result
Result
Refclk HF RMS Jitter
3.1 ps
441.606 fs
PASS
Refclk LF RMS Jitter
3 ps
19.205 fs
PASS
4.289 ps
N/A
Test
Pk-pk Phase Jitter at BER 10^-6 Low Frequency Phase Jitter
0.01 dB
1.5 MHz
0 dB
12 ns
N/A
High Frequency Phase Jitter
Filter Magnitude Responses
Prepared by Silicon Labs PCIe Clock Jitter Tool v0.21 on 2015-11-17 15:19:35 GMT-06:00
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PCI Express Compliance Report
Page 18 of 37
#
Class Data Rate Architecture Specs PLL1 BW PLL1 Pk PLL2 BW PLL2 PK CDR BW CDR PK Delay SSC Separation
29 GEN2
5 Gb/s
Common Clock 4.0
5 MHz
0.01 dB
16 MHz
Specification
Analysis Compliance
Result
Result
Refclk HF RMS Jitter
3.1 ps
369.232 fs
PASS
Refclk LF RMS Jitter
3 ps
40.402 fs
PASS
3.396 ps
N/A
Test
Pk-pk Phase Jitter at BER 10^-6 3 dB
1.5 MHz
Low Frequency Phase Jitter
0 dB
12 ns
N/A
High Frequency Phase Jitter
Filter Magnitude Responses
#
Class Data Rate Architecture Specs PLL1 BW PLL1 Pk PLL2 BW PLL2 PK CDR BW CDR PK Delay SSC Separation
30 GEN2
5 Gb/s
Common Clock 4.0
5 MHz
1 dB
16 MHz
Specification
Analysis Compliance
Result
Result
Refclk HF RMS Jitter
3.1 ps
391.072 fs
PASS
Refclk LF RMS Jitter
3 ps
44.443 fs
PASS
3.630 ps
N/A
Test
Pk-pk Phase Jitter at BER 10^-6 Low Frequency Phase Jitter
3 dB
1.5 MHz
0 dB
12 ns
N/A
High Frequency Phase Jitter
Filter Magnitude Responses
Prepared by Silicon Labs PCIe Clock Jitter Tool v0.21 on 2015-11-17 15:19:35 GMT-06:00
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PCI Express Compliance Report
Page 19 of 37
#
Class Data Rate Architecture Specs PLL1 BW PLL1 Pk PLL2 BW PLL2 PK CDR BW CDR PK Delay SSC Separation
31 GEN2
5 Gb/s
Common Clock 4.0
16 MHz
0.01 dB
16 MHz
Specification
Analysis Compliance
Result
Result
Refclk HF RMS Jitter
3.1 ps
475.974 fs
PASS
Refclk LF RMS Jitter
3 ps
20.596 fs
PASS
4.454 ps
N/A
Test
Pk-pk Phase Jitter at BER 10^-6 3 dB
1.5 MHz
Low Frequency Phase Jitter
0 dB
12 ns
N/A
High Frequency Phase Jitter
Filter Magnitude Responses
#
Class Data Rate Architecture Specs PLL1 BW PLL1 Pk PLL2 BW PLL2 PK CDR BW CDR PK Delay SSC Separation
32 GEN2
5 Gb/s
Common Clock 4.0
16 MHz
1 dB
16 MHz
Specification
Analysis Compliance
Result
Result
Refclk HF RMS Jitter
3.1 ps
429.506 fs
PASS
Refclk LF RMS Jitter
3 ps
13.869 fs
PASS
3.949 ps
N/A
Test
Pk-pk Phase Jitter at BER 10^-6 Low Frequency Phase Jitter
3 dB
1.5 MHz
0 dB
12 ns
N/A
High Frequency Phase Jitter
Filter Magnitude Responses
Prepared by Silicon Labs PCIe Clock Jitter Tool v0.21 on 2015-11-17 15:19:35 GMT-06:00
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PCI Express Compliance Report
Page 20 of 37
#
Class Data Rate Architecture
33 GEN3
8 Gb/s
Specs
PLL1 BW PLL1 Pk PLL2 BW PLL2 PK CDR BW CDR PK Delay SSC Separation
Common Clock 3.1 · 4.0 2 MHz
0.01 dB
2 MHz
Specification
Analysis Compliance
Result
Result
Refclk HF RMS Jitter
1 ps
63.941 fs
PASS
Refclk LF RMS Jitter
4.934 fs
N/A
572.498 fs
N/A
Test
Pk-pk Phase Jitter at BER 10^-6 0.01 dB
10 MHz
Low Frequency Phase Jitter
0 dB
12 ns
Off (1)
High Frequency Phase Jitter
Filter Magnitude Responses
#
Class Data Rate Architecture
34 GEN3
8 Gb/s
Specs
PLL1 BW PLL1 Pk PLL2 BW PLL2 PK CDR BW CDR PK Delay SSC Separation
Common Clock 3.1 · 4.0 2 MHz
2 dB
2 MHz
Specification
Analysis Compliance
Result
Result
Refclk HF RMS Jitter
1 ps
71.633 fs
PASS
Refclk LF RMS Jitter
26.129 fs
N/A
693.363 fs
N/A
Test
Pk-pk Phase Jitter at BER 10^-6 Low Frequency Phase Jitter
0.01 dB
10 MHz
0 dB
12 ns
Off (1)
High Frequency Phase Jitter
Filter Magnitude Responses
Prepared by Silicon Labs PCIe Clock Jitter Tool v0.21 on 2015-11-17 15:19:35 GMT-06:00
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PCI Express Compliance Report
Page 21 of 37
#
Class Data Rate Architecture
35 GEN3
8 Gb/s
Specs
PLL1 BW PLL1 Pk PLL2 BW PLL2 PK CDR BW CDR PK Delay SSC Separation
Common Clock 3.1 · 4.0 4 MHz
0.01 dB
2 MHz
Specification
Analysis Compliance
Result
Result
Refclk HF RMS Jitter
1 ps
117.685 fs
PASS
Refclk LF RMS Jitter
20.538 fs
N/A
1.079 ps
N/A
Test
Pk-pk Phase Jitter at BER 10^-6 0.01 dB
10 MHz
Low Frequency Phase Jitter
0 dB
12 ns
Off (1)
High Frequency Phase Jitter
Filter Magnitude Responses
#
Class Data Rate Architecture
36 GEN3
8 Gb/s
Specs
PLL1 BW PLL1 Pk PLL2 BW PLL2 PK CDR BW CDR PK Delay SSC Separation
Common Clock 3.1 · 4.0 4 MHz
2 dB
2 MHz
Specification
Analysis Compliance
Result
Result
Refclk HF RMS Jitter
1 ps
97.395 fs
PASS
Refclk LF RMS Jitter
34.624 fs
N/A
898.365 fs
N/A
Test
Pk-pk Phase Jitter at BER 10^-6 Low Frequency Phase Jitter
0.01 dB
10 MHz
0 dB
12 ns
Off (1)
High Frequency Phase Jitter
Filter Magnitude Responses
Prepared by Silicon Labs PCIe Clock Jitter Tool v0.21 on 2015-11-17 15:19:35 GMT-06:00
Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc.
PCI Express Compliance Report
Page 22 of 37
#
Class Data Rate Architecture
37 GEN3
8 Gb/s
Specs
PLL1 BW PLL1 Pk PLL2 BW PLL2 PK CDR BW CDR PK Delay SSC Separation
Common Clock 3.1 · 4.0 2 MHz
0.01 dB
2 MHz
Specification
Analysis Compliance
Result
Result
Refclk HF RMS Jitter
1 ps
65.384 fs
PASS
Refclk LF RMS Jitter
14.578 fs
N/A
604.163 fs
N/A
Test
Pk-pk Phase Jitter at BER 10^-6 1 dB
10 MHz
Low Frequency Phase Jitter
0 dB
12 ns
Off (1)
High Frequency Phase Jitter
Filter Magnitude Responses
#
Class Data Rate Architecture
38 GEN3
8 Gb/s
Specs
PLL1 BW PLL1 Pk PLL2 BW PLL2 PK CDR BW CDR PK Delay SSC Separation
Common Clock 3.1 · 4.0 2 MHz
2 dB
2 MHz
Specification
Analysis Compliance
Result
Result
Refclk HF RMS Jitter
1 ps
57.641 fs
PASS
Refclk LF RMS Jitter
15.964 fs
N/A
549.708 fs
N/A
Test
Pk-pk Phase Jitter at BER 10^-6 Low Frequency Phase Jitter
1 dB
10 MHz
0 dB
12 ns
Off (1)
High Frequency Phase Jitter
Filter Magnitude Responses
Prepared by Silicon Labs PCIe Clock Jitter Tool v0.21 on 2015-11-17 15:19:35 GMT-06:00
Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc.
PCI Express Compliance Report
Page 23 of 37
#
Class Data Rate Architecture
39 GEN3
8 Gb/s
Specs
PLL1 BW PLL1 Pk PLL2 BW PLL2 PK CDR BW CDR PK Delay SSC Separation
Common Clock 3.1 · 4.0 4 MHz
0.01 dB
2 MHz
Specification
Analysis Compliance
Result
Result
Refclk HF RMS Jitter
1 ps
123.251 fs
PASS
Refclk LF RMS Jitter
28.354 fs
N/A
1.173 ps
N/A
Test
Pk-pk Phase Jitter at BER 10^-6 1 dB
10 MHz
Low Frequency Phase Jitter
0 dB
12 ns
Off (1)
High Frequency Phase Jitter
Filter Magnitude Responses
#
Class Data Rate Architecture
40 GEN3
8 Gb/s
Specs
PLL1 BW PLL1 Pk PLL2 BW PLL2 PK CDR BW CDR PK Delay SSC Separation
Common Clock 3.1 · 4.0 4 MHz
2 dB
2 MHz
Specification
Analysis Compliance
Result
Result
Refclk HF RMS Jitter
1 ps
103.177 fs
PASS
Refclk LF RMS Jitter
39.485 fs
N/A
934.670 fs
N/A
Test
Pk-pk Phase Jitter at BER 10^-6 Low Frequency Phase Jitter
1 dB
10 MHz
0 dB
12 ns
Off (1)
High Frequency Phase Jitter
Filter Magnitude Responses
Prepared by Silicon Labs PCIe Clock Jitter Tool v0.21 on 2015-11-17 15:19:35 GMT-06:00
Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc.
PCI Express Compliance Report
Page 24 of 37
#
Class Data Rate Architecture
41 GEN3
8 Gb/s
Specs
PLL1 BW PLL1 Pk PLL2 BW PLL2 PK CDR BW CDR PK Delay SSC Separation
Common Clock 3.1 · 4.0 2 MHz
0.01 dB
5 MHz
Specification
Analysis Compliance
Result
Result
Refclk HF RMS Jitter
1 ps
143.030 fs
PASS
Refclk LF RMS Jitter
24.010 fs
N/A
1.322 ps
N/A
Test
Pk-pk Phase Jitter at BER 10^-6 0.01 dB
10 MHz
Low Frequency Phase Jitter
0 dB
12 ns
Off (1)
High Frequency Phase Jitter
Filter Magnitude Responses
#
Class Data Rate Architecture
42 GEN3
8 Gb/s
Specs
PLL1 BW PLL1 Pk PLL2 BW PLL2 PK CDR BW CDR PK Delay SSC Separation
Common Clock 3.1 · 4.0 2 MHz
2 dB
5 MHz
Specification
Analysis Compliance
Result
Result
Refclk HF RMS Jitter
1 ps
156.069 fs
PASS
Refclk LF RMS Jitter
41.492 fs
N/A
1.518 ps
N/A
Test
Pk-pk Phase Jitter at BER 10^-6 Low Frequency Phase Jitter
0.01 dB
10 MHz
0 dB
12 ns
Off (1)
High Frequency Phase Jitter
Filter Magnitude Responses
Prepared by Silicon Labs PCIe Clock Jitter Tool v0.21 on 2015-11-17 15:19:35 GMT-06:00
Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc.
PCI Express Compliance Report
Page 25 of 37
#
Class Data Rate Architecture
43 GEN3
8 Gb/s
Specs
PLL1 BW PLL1 Pk PLL2 BW PLL2 PK CDR BW CDR PK Delay SSC Separation
Common Clock 3.1 · 4.0 4 MHz
0.01 dB
5 MHz
Specification
Analysis Compliance
Result
Result
Refclk HF RMS Jitter
1 ps
145.168 fs
Refclk LF RMS Jitter
9.037 fs
N/A
Pk-pk Phase Jitter at BER 10^-6 1.317 ps
N/A
Test
0.01 dB
10 MHz
0 dB
12 ns
Off (1)
PASS
Low Frequency Phase Jitter
High Frequency Phase Jitter
Filter Magnitude Responses
#
Class Data Rate Architecture
44 GEN3
8 Gb/s
Specs
PLL1 BW PLL1 Pk PLL2 BW PLL2 PK CDR BW CDR PK Delay SSC Separation
Common Clock 3.1 · 4.0 4 MHz
2 dB
5 MHz
Specification
Analysis Compliance
Result
Result
Refclk HF RMS Jitter
1 ps
152.081 fs
PASS
Refclk LF RMS Jitter
17.790 fs
N/A
1.382 ps
N/A
Test
Pk-pk Phase Jitter at BER 10^-6 Low Frequency Phase Jitter
0.01 dB
10 MHz
0 dB
12 ns
Off (1)
High Frequency Phase Jitter
Filter Magnitude Responses
Prepared by Silicon Labs PCIe Clock Jitter Tool v0.21 on 2015-11-17 15:19:35 GMT-06:00
Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc.
PCI Express Compliance Report
Page 26 of 37
#
Class Data Rate Architecture
45 GEN3
8 Gb/s
Specs
PLL1 BW PLL1 Pk PLL2 BW PLL2 PK CDR BW CDR PK Delay SSC Separation
Common Clock 3.1 · 4.0 2 MHz
0.01 dB
5 MHz
Specification
Analysis Compliance
Result
Result
Refclk HF RMS Jitter
1 ps
129.314 fs
PASS
Refclk LF RMS Jitter
30.673 fs
N/A
1.203 ps
N/A
Test
Pk-pk Phase Jitter at BER 10^-6 1 dB
10 MHz
Low Frequency Phase Jitter
0 dB
12 ns
Off (1)
High Frequency Phase Jitter
Filter Magnitude Responses
#
Class Data Rate Architecture
46 GEN3
8 Gb/s
Specs
PLL1 BW PLL1 Pk PLL2 BW PLL2 PK CDR BW CDR PK Delay SSC Separation
Common Clock 3.1 · 4.0 2 MHz
2 dB
5 MHz
Specification
Analysis Compliance
Result
Result
Refclk HF RMS Jitter
1 ps
144.391 fs
PASS
Refclk LF RMS Jitter
44.609 fs
N/A
1.394 ps
N/A
Test
Pk-pk Phase Jitter at BER 10^-6 Low Frequency Phase Jitter
1 dB
10 MHz
0 dB
12 ns
Off (1)
High Frequency Phase Jitter
Filter Magnitude Responses
Prepared by Silicon Labs PCIe Clock Jitter Tool v0.21 on 2015-11-17 15:19:35 GMT-06:00
Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc.
PCI Express Compliance Report
Page 27 of 37
#
Class Data Rate Architecture
47 GEN3
8 Gb/s
Specs
PLL1 BW PLL1 Pk PLL2 BW PLL2 PK CDR BW CDR PK Delay SSC Separation
Common Clock 3.1 · 4.0 4 MHz
0.01 dB
5 MHz
Specification
Analysis Compliance
Result
Result
Refclk HF RMS Jitter
1 ps
132.386 fs
PASS
Refclk LF RMS Jitter
15.069 fs
N/A
1.214 ps
N/A
Test
Pk-pk Phase Jitter at BER 10^-6 1 dB
10 MHz
Low Frequency Phase Jitter
0 dB
12 ns
Off (1)
High Frequency Phase Jitter
Filter Magnitude Responses
#
Class Data Rate Architecture
48 GEN3
8 Gb/s
Specs
PLL1 BW PLL1 Pk PLL2 BW PLL2 PK CDR BW CDR PK Delay SSC Separation
Common Clock 3.1 · 4.0 4 MHz
2 dB
5 MHz
Specification
Analysis Compliance
Result
Result
Refclk HF RMS Jitter
1 ps
130.223 fs
PASS
Refclk LF RMS Jitter
11.115 fs
N/A
1.143 ps
N/A
Test
Pk-pk Phase Jitter at BER 10^-6 Low Frequency Phase Jitter
1 dB
10 MHz
0 dB
12 ns
Off (1)
High Frequency Phase Jitter
Filter Magnitude Responses
Prepared by Silicon Labs PCIe Clock Jitter Tool v0.21 on 2015-11-17 15:19:35 GMT-06:00
Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc.
PCI Express Compliance Report
Page 28 of 37
#
Class Data Rate Architecture Specs PLL1 BW PLL1 Pk PLL2 BW PLL2 PK CDR BW CDR PK Delay SSC Separation
49 GEN4
16 Gb/s
Common Clock 4.0
2 MHz
0.01 dB
2 MHz
Specification
Analysis Compliance
Result
Result
Refclk HF RMS Jitter
1 ps
63.941 fs
PASS
Refclk LF RMS Jitter
4.934 fs
N/A
572.498 fs
N/A
Test
Pk-pk Phase Jitter at BER 10^-6 0.01 dB
10 MHz
Low Frequency Phase Jitter
0 dB
12 ns
N/A
High Frequency Phase Jitter
Filter Magnitude Responses
#
Class Data Rate Architecture Specs PLL1 BW PLL1 Pk PLL2 BW PLL2 PK CDR BW CDR PK Delay SSC Separation
50 GEN4
16 Gb/s
Common Clock 4.0
2 MHz
2 dB
2 MHz
Specification
Analysis Compliance
Result
Result
Refclk HF RMS Jitter
1 ps
71.633 fs
PASS
Refclk LF RMS Jitter
26.129 fs
N/A
693.363 fs
N/A
Test
Pk-pk Phase Jitter at BER 10^-6 Low Frequency Phase Jitter
0.01 dB
10 MHz
0 dB
12 ns
N/A
High Frequency Phase Jitter
Filter Magnitude Responses
Prepared by Silicon Labs PCIe Clock Jitter Tool v0.21 on 2015-11-17 15:19:35 GMT-06:00
Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc.
PCI Express Compliance Report
Page 29 of 37
#
Class Data Rate Architecture Specs PLL1 BW PLL1 Pk PLL2 BW PLL2 PK CDR BW CDR PK Delay SSC Separation
51 GEN4
16 Gb/s
Common Clock 4.0
4 MHz
0.01 dB
2 MHz
Specification
Analysis Compliance
Result
Result
Refclk HF RMS Jitter
1 ps
117.685 fs
PASS
Refclk LF RMS Jitter
20.538 fs
N/A
1.079 ps
N/A
Test
Pk-pk Phase Jitter at BER 10^-6 0.01 dB
10 MHz
Low Frequency Phase Jitter
0 dB
12 ns
N/A
High Frequency Phase Jitter
Filter Magnitude Responses
#
Class Data Rate Architecture Specs PLL1 BW PLL1 Pk PLL2 BW PLL2 PK CDR BW CDR PK Delay SSC Separation
52 GEN4
16 Gb/s
Common Clock 4.0
4 MHz
2 dB
2 MHz
Specification
Analysis Compliance
Result
Result
Refclk HF RMS Jitter
1 ps
97.395 fs
PASS
Refclk LF RMS Jitter
34.624 fs
N/A
898.365 fs
N/A
Test
Pk-pk Phase Jitter at BER 10^-6 Low Frequency Phase Jitter
0.01 dB
10 MHz
0 dB
12 ns
N/A
High Frequency Phase Jitter
Filter Magnitude Responses
Prepared by Silicon Labs PCIe Clock Jitter Tool v0.21 on 2015-11-17 15:19:35 GMT-06:00
Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc.
PCI Express Compliance Report
Page 30 of 37
#
Class Data Rate Architecture Specs PLL1 BW PLL1 Pk PLL2 BW PLL2 PK CDR BW CDR PK Delay SSC Separation
53 GEN4
16 Gb/s
Common Clock 4.0
2 MHz
0.01 dB
2 MHz
Specification
Analysis Compliance
Result
Result
Refclk HF RMS Jitter
1 ps
65.384 fs
PASS
Refclk LF RMS Jitter
14.578 fs
N/A
604.163 fs
N/A
Test
Pk-pk Phase Jitter at BER 10^-6 1 dB
10 MHz
Low Frequency Phase Jitter
0 dB
12 ns
N/A
High Frequency Phase Jitter
Filter Magnitude Responses
#
Class Data Rate Architecture Specs PLL1 BW PLL1 Pk PLL2 BW PLL2 PK CDR BW CDR PK Delay SSC Separation
54 GEN4
16 Gb/s
Common Clock 4.0
2 MHz
2 dB
2 MHz
Specification
Analysis Compliance
Result
Result
Refclk HF RMS Jitter
1 ps
57.641 fs
PASS
Refclk LF RMS Jitter
15.964 fs
N/A
549.708 fs
N/A
Test
Pk-pk Phase Jitter at BER 10^-6 Low Frequency Phase Jitter
1 dB
10 MHz
0 dB
12 ns
N/A
High Frequency Phase Jitter
Filter Magnitude Responses
Prepared by Silicon Labs PCIe Clock Jitter Tool v0.21 on 2015-11-17 15:19:35 GMT-06:00
Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc.
PCI Express Compliance Report
Page 31 of 37
#
Class Data Rate Architecture Specs PLL1 BW PLL1 Pk PLL2 BW PLL2 PK CDR BW CDR PK Delay SSC Separation
55 GEN4
16 Gb/s
Common Clock 4.0
4 MHz
0.01 dB
2 MHz
Specification
Analysis Compliance
Result
Result
Refclk HF RMS Jitter
1 ps
123.251 fs
PASS
Refclk LF RMS Jitter
28.354 fs
N/A
1.173 ps
N/A
Test
Pk-pk Phase Jitter at BER 10^-6 1 dB
10 MHz
Low Frequency Phase Jitter
0 dB
12 ns
N/A
High Frequency Phase Jitter
Filter Magnitude Responses
#
Class Data Rate Architecture Specs PLL1 BW PLL1 Pk PLL2 BW PLL2 PK CDR BW CDR PK Delay SSC Separation
56 GEN4
16 Gb/s
Common Clock 4.0
4 MHz
2 dB
2 MHz
Specification
Analysis Compliance
Result
Result
Refclk HF RMS Jitter
1 ps
103.177 fs
PASS
Refclk LF RMS Jitter
39.485 fs
N/A
934.670 fs
N/A
Test
Pk-pk Phase Jitter at BER 10^-6 Low Frequency Phase Jitter
1 dB
10 MHz
0 dB
12 ns
N/A
High Frequency Phase Jitter
Filter Magnitude Responses
Prepared by Silicon Labs PCIe Clock Jitter Tool v0.21 on 2015-11-17 15:19:35 GMT-06:00
Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc.
PCI Express Compliance Report
Page 32 of 37
#
Class Data Rate Architecture Specs PLL1 BW PLL1 Pk PLL2 BW PLL2 PK CDR BW CDR PK Delay SSC Separation
57 GEN4
16 Gb/s
Common Clock 4.0
2 MHz
0.01 dB
5 MHz
Specification
Analysis Compliance
Result
Result
Refclk HF RMS Jitter
1 ps
143.030 fs
PASS
Refclk LF RMS Jitter
24.010 fs
N/A
1.322 ps
N/A
Test
Pk-pk Phase Jitter at BER 10^-6 0.01 dB
10 MHz
Low Frequency Phase Jitter
0 dB
12 ns
N/A
High Frequency Phase Jitter
Filter Magnitude Responses
#
Class Data Rate Architecture Specs PLL1 BW PLL1 Pk PLL2 BW PLL2 PK CDR BW CDR PK Delay SSC Separation
58 GEN4
16 Gb/s
Common Clock 4.0
2 MHz
2 dB
5 MHz
Specification
Analysis Compliance
Result
Result
Refclk HF RMS Jitter
1 ps
156.069 fs
PASS
Refclk LF RMS Jitter
41.492 fs
N/A
1.518 ps
N/A
Test
Pk-pk Phase Jitter at BER 10^-6 Low Frequency Phase Jitter
0.01 dB
10 MHz
0 dB
12 ns
N/A
High Frequency Phase Jitter
Filter Magnitude Responses
Prepared by Silicon Labs PCIe Clock Jitter Tool v0.21 on 2015-11-17 15:19:35 GMT-06:00
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PCI Express Compliance Report
Page 33 of 37
#
Class Data Rate Architecture Specs PLL1 BW PLL1 Pk PLL2 BW PLL2 PK CDR BW CDR PK Delay SSC Separation
59 GEN4
16 Gb/s
Common Clock 4.0
4 MHz
0.01 dB
5 MHz
Specification
Analysis Compliance
Result
Result
Refclk HF RMS Jitter
1 ps
145.168 fs
Refclk LF RMS Jitter
9.037 fs
N/A
Pk-pk Phase Jitter at BER 10^-6 1.317 ps
N/A
Test
0.01 dB
10 MHz
0 dB
12 ns
N/A
PASS
Low Frequency Phase Jitter
High Frequency Phase Jitter
Filter Magnitude Responses
#
Class Data Rate Architecture Specs PLL1 BW PLL1 Pk PLL2 BW PLL2 PK CDR BW CDR PK Delay SSC Separation
60 GEN4
16 Gb/s
Common Clock 4.0
4 MHz
2 dB
5 MHz
Specification
Analysis Compliance
Result
Result
Refclk HF RMS Jitter
1 ps
152.081 fs
PASS
Refclk LF RMS Jitter
17.790 fs
N/A
1.382 ps
N/A
Test
Pk-pk Phase Jitter at BER 10^-6 Low Frequency Phase Jitter
0.01 dB
10 MHz
0 dB
12 ns
N/A
High Frequency Phase Jitter
Filter Magnitude Responses
Prepared by Silicon Labs PCIe Clock Jitter Tool v0.21 on 2015-11-17 15:19:35 GMT-06:00
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PCI Express Compliance Report
Page 34 of 37
#
Class Data Rate Architecture Specs PLL1 BW PLL1 Pk PLL2 BW PLL2 PK CDR BW CDR PK Delay SSC Separation
61 GEN4
16 Gb/s
Common Clock 4.0
2 MHz
0.01 dB
5 MHz
Specification
Analysis Compliance
Result
Result
Refclk HF RMS Jitter
1 ps
129.314 fs
PASS
Refclk LF RMS Jitter
30.673 fs
N/A
1.203 ps
N/A
Test
Pk-pk Phase Jitter at BER 10^-6 1 dB
10 MHz
Low Frequency Phase Jitter
0 dB
12 ns
N/A
High Frequency Phase Jitter
Filter Magnitude Responses
#
Class Data Rate Architecture Specs PLL1 BW PLL1 Pk PLL2 BW PLL2 PK CDR BW CDR PK Delay SSC Separation
62 GEN4
16 Gb/s
Common Clock 4.0
2 MHz
2 dB
5 MHz
Specification
Analysis Compliance
Result
Result
Refclk HF RMS Jitter
1 ps
144.391 fs
PASS
Refclk LF RMS Jitter
44.609 fs
N/A
1.394 ps
N/A
Test
Pk-pk Phase Jitter at BER 10^-6 Low Frequency Phase Jitter
1 dB
10 MHz
0 dB
12 ns
N/A
High Frequency Phase Jitter
Filter Magnitude Responses
Prepared by Silicon Labs PCIe Clock Jitter Tool v0.21 on 2015-11-17 15:19:35 GMT-06:00
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PCI Express Compliance Report
Page 35 of 37
#
Class Data Rate Architecture Specs PLL1 BW PLL1 Pk PLL2 BW PLL2 PK CDR BW CDR PK Delay SSC Separation
63 GEN4
16 Gb/s
Common Clock 4.0
4 MHz
0.01 dB
5 MHz
Specification
Analysis Compliance
Result
Result
Refclk HF RMS Jitter
1 ps
132.386 fs
PASS
Refclk LF RMS Jitter
15.069 fs
N/A
1.214 ps
N/A
Test
Pk-pk Phase Jitter at BER 10^-6 1 dB
10 MHz
Low Frequency Phase Jitter
0 dB
12 ns
N/A
High Frequency Phase Jitter
Filter Magnitude Responses
#
Class Data Rate Architecture Specs PLL1 BW PLL1 Pk PLL2 BW PLL2 PK CDR BW CDR PK Delay SSC Separation
64 GEN4
16 Gb/s
Common Clock 4.0
4 MHz
2 dB
5 MHz
Specification
Analysis Compliance
Result
Result
Refclk HF RMS Jitter
1 ps
130.223 fs
PASS
Refclk LF RMS Jitter
11.115 fs
N/A
1.143 ps
N/A
Test
Pk-pk Phase Jitter at BER 10^-6 Low Frequency Phase Jitter
1 dB
10 MHz
0 dB
12 ns
N/A
High Frequency Phase Jitter
Filter Magnitude Responses
Prepared by Silicon Labs PCIe Clock Jitter Tool v0.21 on 2015-11-17 15:19:35 GMT-06:00
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PCI Express Compliance Report
Page 36 of 37
Transfer Function Constants
H1
BW
H1
Peaking
H1
Omega
H1
Zeta
H2
BW
H2
Peaking
H2
Omega
H2
Zeta
H3
BW
H3
Peaking
H3
Omega
H3
Zeta
#
Class Architecture Specs
1
GEN1
Common Clock 4.0
1.5 MHz 0.01 dB
3.36000E+5 1.40000E+1 1.5 MHz 0.01 dB
3.36000E+5 1.40000E+1 1.5 MHz 0 dB
9.42478E+6 0.00000E+0 10 ns
2
GEN1
Common Clock 4.0
1.5 MHz 3 dB
5.09000E+6 5.40000E-1 1.5 MHz 0.01 dB
3.36000E+5 1.40000E+1 1.5 MHz 0 dB
9.42478E+6 0.00000E+0 10 ns
3
GEN1
Common Clock 4.0
22 MHz
0.01 dB
4.93000E+6 1.40000E+1 1.5 MHz 0.01 dB
3.36000E+5 1.40000E+1 1.5 MHz 0 dB
9.42478E+6 0.00000E+0 10 ns
4
GEN1
Common Clock 4.0
22 MHz
3 dB
7.46800E+7 5.40000E-1 1.5 MHz 0.01 dB
3.36000E+5 1.40000E+1 1.5 MHz 0 dB
9.42478E+6 0.00000E+0 10 ns
5
GEN1
Common Clock 4.0
1.5 MHz 0.01 dB
3.36000E+5 1.40000E+1 1.5 MHz 3 dB
5.09000E+6 5.40000E-1 1.5 MHz 0 dB
9.42478E+6 0.00000E+0 10 ns
6
GEN1
Common Clock 4.0
1.5 MHz 3 dB
5.09000E+6 5.40000E-1 1.5 MHz 3 dB
5.09000E+6 5.40000E-1 1.5 MHz 0 dB
9.42478E+6 0.00000E+0 10 ns
7
GEN1
Common Clock 4.0
22 MHz
0.01 dB
4.93000E+6 1.40000E+1 1.5 MHz 3 dB
5.09000E+6 5.40000E-1 1.5 MHz 0 dB
9.42478E+6 0.00000E+0 10 ns
8
GEN1
Common Clock 4.0
22 MHz
3 dB
7.46800E+7 5.40000E-1 1.5 MHz 3 dB
5.09000E+6 5.40000E-1 1.5 MHz 0 dB
9.42478E+6 0.00000E+0 10 ns
9
GEN1
Common Clock 4.0
1.5 MHz 0.01 dB
3.36000E+5 1.40000E+1 22 MHz
0.01 dB
4.93000E+6 1.40000E+1 1.5 MHz 0 dB
9.42478E+6 0.00000E+0 10 ns
10 GEN1
Common Clock 4.0
1.5 MHz 3 dB
5.09000E+6 5.40000E-1 22 MHz
0.01 dB
4.93000E+6 1.40000E+1 1.5 MHz 0 dB
9.42478E+6 0.00000E+0 10 ns
11 GEN1
Common Clock 4.0
22 MHz
0.01 dB
4.93000E+6 1.40000E+1 22 MHz
0.01 dB
4.93000E+6 1.40000E+1 1.5 MHz 0 dB
9.42478E+6 0.00000E+0 10 ns
12 GEN1
Common Clock 4.0
22 MHz
3 dB
7.46800E+7 5.40000E-1 22 MHz
0.01 dB
4.93000E+6 1.40000E+1 1.5 MHz 0 dB
9.42478E+6 0.00000E+0 10 ns
13 GEN1
Common Clock 4.0
1.5 MHz 0.01 dB
3.36000E+5 1.40000E+1 22 MHz
3 dB
7.46800E+7 5.40000E-1 1.5 MHz 0 dB
9.42478E+6 0.00000E+0 10 ns
14 GEN1
Common Clock 4.0
1.5 MHz 3 dB
5.09000E+6 5.40000E-1 22 MHz
3 dB
7.46800E+7 5.40000E-1 1.5 MHz 0 dB
9.42478E+6 0.00000E+0 10 ns
15 GEN1
Common Clock 4.0
22 MHz
0.01 dB
4.93000E+6 1.40000E+1 22 MHz
3 dB
7.46800E+7 5.40000E-1 1.5 MHz 0 dB
9.42478E+6 0.00000E+0 10 ns
16 GEN1
Common Clock 4.0
22 MHz
3 dB
7.46800E+7 5.40000E-1 22 MHz
3 dB
7.46800E+7 5.40000E-1 1.5 MHz 0 dB
9.42478E+6 0.00000E+0 10 ns
17 GEN2
Common Clock 4.0
5 MHz
0.01 dB
1.12000E+6 1.40000E+1 8 MHz
0.01 dB
1.79000E+6 1.40000E+1 1.5 MHz 0 dB
3.14159E+7 0.00000E+0 12 ns
18 GEN2
Common Clock 4.0
5 MHz
1 dB
1.10100E+7 1.16000E+0 8 MHz
0.01 dB
1.79000E+6 1.40000E+1 1.5 MHz 0 dB
3.14159E+7 0.00000E+0 12 ns
19 GEN2
Common Clock 4.0
16 MHz
0.01 dB
3.58000E+6 1.40000E+1 8 MHz
0.01 dB
1.79000E+6 1.40000E+1 1.5 MHz 0 dB
3.14159E+7 0.00000E+0 12 ns
20 GEN2
Common Clock 4.0
16 MHz
1 dB
3.52600E+7 1.16000E+0 8 MHz
0.01 dB
1.79000E+6 1.40000E+1 1.5 MHz 0 dB
3.14159E+7 0.00000E+0 12 ns
21 GEN2
Common Clock 4.0
5 MHz
0.01 dB
1.12000E+6 1.40000E+1 8 MHz
3 dB
2.88600E+7 5.40000E-1 1.5 MHz 0 dB
3.14159E+7 0.00000E+0 12 ns
22 GEN2
Common Clock 4.0
5 MHz
1 dB
1.10100E+7 1.16000E+0 8 MHz
3 dB
2.88600E+7 5.40000E-1 1.5 MHz 0 dB
3.14159E+7 0.00000E+0 12 ns
23 GEN2
Common Clock 4.0
16 MHz
0.01 dB
3.58000E+6 1.40000E+1 8 MHz
3 dB
2.88600E+7 5.40000E-1 1.5 MHz 0 dB
3.14159E+7 0.00000E+0 12 ns
24 GEN2
Common Clock 4.0
16 MHz
1 dB
3.52600E+7 1.16000E+0 8 MHz
3 dB
2.88600E+7 5.40000E-1 1.5 MHz 0 dB
3.14159E+7 0.00000E+0 12 ns
25 GEN2
Common Clock 4.0
5 MHz
0.01 dB
1.12000E+6 1.40000E+1 16 MHz
0.01 dB
3.58000E+6 1.40000E+1 1.5 MHz 0 dB
3.14159E+7 0.00000E+0 12 ns
26 GEN2
Common Clock 4.0
5 MHz
1 dB
1.10100E+7 1.16000E+0 16 MHz
0.01 dB
3.58000E+6 1.40000E+1 1.5 MHz 0 dB
3.14159E+7 0.00000E+0 12 ns
27 GEN2
Common Clock 4.0
16 MHz
0.01 dB
3.58000E+6 1.40000E+1 16 MHz
0.01 dB
3.58000E+6 1.40000E+1 1.5 MHz 0 dB
3.14159E+7 0.00000E+0 12 ns
28 GEN2
Common Clock 4.0
16 MHz
1 dB
3.52600E+7 1.16000E+0 16 MHz
0.01 dB
3.58000E+6 1.40000E+1 1.5 MHz 0 dB
3.14159E+7 0.00000E+0 12 ns
29 GEN2
Common Clock 4.0
5 MHz
0.01 dB
1.12000E+6 1.40000E+1 16 MHz
3 dB
5.37300E+7 5.40000E-1 1.5 MHz 0 dB
3.14159E+7 0.00000E+0 12 ns
30 GEN2
Common Clock 4.0
5 MHz
1 dB
1.10100E+7 1.16000E+0 16 MHz
3 dB
5.37300E+7 5.40000E-1 1.5 MHz 0 dB
3.14159E+7 0.00000E+0 12 ns
31 GEN2
Common Clock 4.0
16 MHz
0.01 dB
3.58000E+6 1.40000E+1 16 MHz
3 dB
5.37300E+7 5.40000E-1 1.5 MHz 0 dB
3.14159E+7 0.00000E+0 12 ns
32 GEN2
Common Clock 4.0
16 MHz
1 dB
3.52600E+7 1.16000E+0 16 MHz
3 dB
5.37300E+7 5.40000E-1 1.5 MHz 0 dB
3.14159E+7 0.00000E+0 12 ns
33 GEN3
Common Clock 3.1
4.0
2 MHz
0.01 dB
4.48000E+5 1.40000E+1 2 MHz
0.01 dB
4.48000E+5 1.40000E+1 10 MHz
0 dB
6.28319E+7 0.00000E+0 12 ns
34 GEN3
Common Clock 3.1
4.0
2 MHz
2 dB
6.02000E+6 7.30000E-1 2 MHz
0.01 dB
4.48000E+5 1.40000E+1 10 MHz
0 dB
6.28319E+7 0.00000E+0 12 ns
35 GEN3
Common Clock 3.1
4.0
4 MHz
0.01 dB
8.96000E+5 1.40000E+1 2 MHz
0.01 dB
4.48000E+5 1.40000E+1 10 MHz
0 dB
6.28319E+7 0.00000E+0 12 ns
36 GEN3
Common Clock 3.1
4.0
4 MHz
2 dB
1.20400E+7 7.30000E-1 2 MHz
0.01 dB
4.48000E+5 1.40000E+1 10 MHz
0 dB
6.28319E+7 0.00000E+0 12 ns
37 GEN3
Common Clock 3.1
4.0
2 MHz
0.01 dB
4.48000E+5 1.40000E+1 2 MHz
1 dB
4.62000E+6 1.15000E+0 10 MHz
0 dB
6.28319E+7 0.00000E+0 12 ns
38 GEN3
Common Clock 3.1
4.0
2 MHz
2 dB
6.02000E+6 7.30000E-1 2 MHz
1 dB
4.62000E+6 1.15000E+0 10 MHz
0 dB
6.28319E+7 0.00000E+0 12 ns
39 GEN3
Common Clock 3.1
4.0
4 MHz
0.01 dB
8.96000E+5 1.40000E+1 2 MHz
1 dB
4.62000E+6 1.15000E+0 10 MHz
0 dB
6.28319E+7 0.00000E+0 12 ns
40 GEN3
Common Clock 3.1
4.0
4 MHz
2 dB
1.20400E+7 7.30000E-1 2 MHz
1 dB
4.62000E+6 1.15000E+0 10 MHz
0 dB
6.28319E+7 0.00000E+0 12 ns
41 GEN3
Common Clock 3.1
4.0
2 MHz
0.01 dB
4.48000E+5 1.40000E+1 5 MHz
0.01 dB
1.12000E+6 1.40000E+1 10 MHz
0 dB
6.28319E+7 0.00000E+0 12 ns
Prepared by Silicon Labs PCIe Clock Jitter Tool v0.21 on 2015-11-17 15:19:35 GMT-06:00
Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc.
Delay
PCI Express Compliance Report
Page 37 of 37
42 GEN3
Common Clock 3.1
4.0
2 MHz
2 dB
6.02000E+6 7.30000E-1 5 MHz
0.01 dB
1.12000E+6 1.40000E+1 10 MHz
0 dB
6.28319E+7 0.00000E+0 12 ns
43 GEN3
Common Clock 3.1
4.0
4 MHz
0.01 dB
8.96000E+5 1.40000E+1 5 MHz
0.01 dB
1.12000E+6 1.40000E+1 10 MHz
0 dB
6.28319E+7 0.00000E+0 12 ns
44 GEN3
Common Clock 3.1
4.0
4 MHz
2 dB
1.20400E+7 7.30000E-1 5 MHz
0.01 dB
1.12000E+6 1.40000E+1 10 MHz
0 dB
6.28319E+7 0.00000E+0 12 ns
45 GEN3
Common Clock 3.1
4.0
2 MHz
0.01 dB
4.48000E+5 1.40000E+1 5 MHz
1 dB
1.15300E+7 1.15000E+0 10 MHz
0 dB
6.28319E+7 0.00000E+0 12 ns
46 GEN3
Common Clock 3.1
4.0
2 MHz
2 dB
6.02000E+6 7.30000E-1 5 MHz
1 dB
1.15300E+7 1.15000E+0 10 MHz
0 dB
6.28319E+7 0.00000E+0 12 ns
47 GEN3
Common Clock 3.1
4.0
4 MHz
0.01 dB
8.96000E+5 1.40000E+1 5 MHz
1 dB
1.15300E+7 1.15000E+0 10 MHz
0 dB
6.28319E+7 0.00000E+0 12 ns
48 GEN3
Common Clock 3.1
4.0
4 MHz
2 dB
1.20400E+7 7.30000E-1 5 MHz
1 dB
1.15300E+7 1.15000E+0 10 MHz
0 dB
6.28319E+7 0.00000E+0 12 ns
49 GEN4
Common Clock 4.0
2 MHz
0.01 dB
4.48000E+5 1.40000E+1 2 MHz
0.01 dB
4.48000E+5 1.40000E+1 10 MHz
0 dB
6.28319E+7 0.00000E+0 12 ns
50 GEN4
Common Clock 4.0
2 MHz
2 dB
6.02000E+6 7.30000E-1 2 MHz
0.01 dB
4.48000E+5 1.40000E+1 10 MHz
0 dB
6.28319E+7 0.00000E+0 12 ns
51 GEN4
Common Clock 4.0
4 MHz
0.01 dB
8.96000E+5 1.40000E+1 2 MHz
0.01 dB
4.48000E+5 1.40000E+1 10 MHz
0 dB
6.28319E+7 0.00000E+0 12 ns
52 GEN4
Common Clock 4.0
4 MHz
2 dB
1.20400E+7 7.30000E-1 2 MHz
0.01 dB
4.48000E+5 1.40000E+1 10 MHz
0 dB
6.28319E+7 0.00000E+0 12 ns
53 GEN4
Common Clock 4.0
2 MHz
0.01 dB
4.48000E+5 1.40000E+1 2 MHz
1 dB
4.62000E+6 1.15000E+0 10 MHz
0 dB
6.28319E+7 0.00000E+0 12 ns
54 GEN4
Common Clock 4.0
2 MHz
2 dB
6.02000E+6 7.30000E-1 2 MHz
1 dB
4.62000E+6 1.15000E+0 10 MHz
0 dB
6.28319E+7 0.00000E+0 12 ns
55 GEN4
Common Clock 4.0
4 MHz
0.01 dB
8.96000E+5 1.40000E+1 2 MHz
1 dB
4.62000E+6 1.15000E+0 10 MHz
0 dB
6.28319E+7 0.00000E+0 12 ns
56 GEN4
Common Clock 4.0
4 MHz
2 dB
1.20400E+7 7.30000E-1 2 MHz
1 dB
4.62000E+6 1.15000E+0 10 MHz
0 dB
6.28319E+7 0.00000E+0 12 ns
57 GEN4
Common Clock 4.0
2 MHz
0.01 dB
4.48000E+5 1.40000E+1 5 MHz
0.01 dB
1.12000E+6 1.40000E+1 10 MHz
0 dB
6.28319E+7 0.00000E+0 12 ns
58 GEN4
Common Clock 4.0
2 MHz
2 dB
6.02000E+6 7.30000E-1 5 MHz
0.01 dB
1.12000E+6 1.40000E+1 10 MHz
0 dB
6.28319E+7 0.00000E+0 12 ns
59 GEN4
Common Clock 4.0
4 MHz
0.01 dB
8.96000E+5 1.40000E+1 5 MHz
0.01 dB
1.12000E+6 1.40000E+1 10 MHz
0 dB
6.28319E+7 0.00000E+0 12 ns
60 GEN4
Common Clock 4.0
4 MHz
2 dB
1.20400E+7 7.30000E-1 5 MHz
0.01 dB
1.12000E+6 1.40000E+1 10 MHz
0 dB
6.28319E+7 0.00000E+0 12 ns
61 GEN4
Common Clock 4.0
2 MHz
0.01 dB
4.48000E+5 1.40000E+1 5 MHz
1 dB
1.15300E+7 1.15000E+0 10 MHz
0 dB
6.28319E+7 0.00000E+0 12 ns
62 GEN4
Common Clock 4.0
2 MHz
2 dB
6.02000E+6 7.30000E-1 5 MHz
1 dB
1.15300E+7 1.15000E+0 10 MHz
0 dB
6.28319E+7 0.00000E+0 12 ns
63 GEN4
Common Clock 4.0
4 MHz
0.01 dB
8.96000E+5 1.40000E+1 5 MHz
1 dB
1.15300E+7 1.15000E+0 10 MHz
0 dB
6.28319E+7 0.00000E+0 12 ns
64 GEN4
Common Clock 4.0
4 MHz
2 dB
1.20400E+7 7.30000E-1 5 MHz
1 dB
1.15300E+7 1.15000E+0 10 MHz
0 dB
6.28319E+7 0.00000E+0 12 ns
Prepared by Silicon Labs PCIe Clock Jitter Tool v0.21 on 2015-11-17 15:19:35 GMT-06:00
Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc.
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