Strip Technology and HVMPAS
Ivan Perić for HVCMOS collaboration*
HVCMOS collaboration:
Bonn:
Malte Backhaus, Tomasz Hemperek, Fabian Hügging, Hans Krüger
CERN:
Lingxin Meng, Daniel Münstermann
CPPM:
Marlon Barbero, Frederic Bompard, Patrick Breugnon, Jean-Claude Clemens, Denis
Fougeron, Patrick Pangaud, Alexandre Rozanov
LBNL:
Maurice Garcia-Sciveres
Heodelberg:
Christan Kreidl, Ivan Perić
Vertex 2012, Ivan Peric
1
Overview
•
•
•
High-Voltage CMOS Sensors - introduction
Summary of the old results
High-Voltage CMOS Sensors for ATLAS
Vertex 2012, Ivan Peric
High-voltage CMOS pixel detectors
or “smart diode arrays”
Vertex 2012, Ivan Peric
3
HV CMOS detectors
•
•
•
•
•
The distinguishable property of HV CMOS sensors is that the CMOS pixel electronics is placed
inside the sensor diode.
This allows:
1) Construction of pixel arrays without insensitive regions.
2) High reverse biasing of the sensor diodes.
3) Fast charge collection based on drift.
Vertex 2012, Ivan Peric
HV CMOS detectors
•
•
We start with a low voltage process:
PMOS and NMOS transistors are placed inside their shallow wells.
PMOS
NMOS
Shallow n-well
Shallow p-well
Vertex 2012, Ivan Peric
HV CMOS detectors
•
A deep n-well surrounds the electronics of every pixel.
PMOS
NMOS
deep n-well
Vertex 2012, Ivan Peric
HV CMOS detectors
•
The deep n-wells isolate the pixel electronics from the p-type substrate.
PMOS
NMOS
deep n-well
p-substrate
Vertex 2012, Ivan Peric
HV CMOS detectors
•
•
•
Since the pixel-transistors do not “see” the substrate potential, the substrate can be biased low
without damaging the transistors.
In this way the depletion zones in the volume around the n-wells are formed.
=> Potential minima for electrons
PMOS
NMOS
deep n-well
Potential energy (e-)
Depletion zone
p-substrate
Vertex 2012, Ivan Peric
HV CMOS detectors
•
•
•
•
Since the pixel-transistors do not “see” the substrate potential, the substrate can be biased low
without damaging the transistors.
In this way the depletion zones in the volume around the n-wells are formed.
=> Potential minima for electrons
Charge collection occurs by drift
PMOS
NMOS
deep n-well
Drift
Depletion zone
p-substrate
Vertex 2012, Ivan Peric
Potential energy (e-)
HV CMOS detectors
•
•
Collected charge causes a voltage change in the n-well.
This signal is sensed by the amplifier – placed in the n-well.
P-substrate
PMOS
NMOS
G
S
D
holes
electrons
N-well
Vertex 2012, Ivan Peric
P-well
HV CMOS detectors
•
•
Collected charge causes a voltage change in the n-well.
This signal is sensed by the amplifier – placed in the n-well.
P-substrate
Vertex 2012, Ivan Peric
HV CMOS detectors
•
•
Collected charge causes a voltage change in the n-well.
This signal is sensed by the amplifier – placed in the n-well.
P-substrate
Vertex 2012, Ivan Peric
HV CMOS detectors
•
Maximizing of the depleted regions improves performances (less capacitance and noise, more
signal) – the best results can be achieved in high-voltage technologies.
PMOS
NMOS
deep n-well
Potential energy (e-)
Depletion zone
p-substrate
Vertex 2012, Ivan Peric
HV CMOS detectors
•
Example AMS 350nm HVCMOS: Typical reverse bias voltage is 60 V and the depleted region
depth ~15 m.
PMOS
NMOS
deep n-well
60V
Depletion zone
Vertex 2012, Ivan Peric
~15µm
HV CMOS detectors
•
•
Example AMS 350nm HVCMOS: Typical reverse bias voltage is 60 V and the depleted region
depth ~15 m.
20cm substrate resistance -> acceptor density ~ 1015 cm-3
PMOS
NMOS
deep n-well
60V
Depletion zone
Vertex 2012, Ivan Peric
~15µm
HV CMOS detectors
•
•
•
Since the sensor diodes are equipped with electronics we call them “smart” and the structure
“smart diode array”.
The structure can be designed also in LV processes that have a deep n-well that surrounds both
types of shallow wells entirely.
An example of such a LV technology is UMC 180nm.
Smart diode
PMOS
NMOS
deep n-well
60V
Depletion zone
Vertex 2012, Ivan Peric
~15µm
CMOS pixel flavors
•
CMOS pixel flavors:
Standard MAPS
INMAPS
„HVMAPS“ – HVCMOS or SDA
TWELL MAPS
Vertex 2012, Ivan Peric
17
A “smart diode” layout
40 µm
Vertex 2012, Ivan Peric
Layout example: intelligent diode
40 µm
Vertex 2012, Ivan Peric
Project results
Vertex 2012, Ivan Peric
20
Project history
2006
„Proof of principle“ phase
350nm AMS HV technology
1) Simple (4T) integrating pixels with pulsed reset and rolling shutter RO
(Possible applications: ILC, transmission electron microscopy, etc.)
2) Pixels with complex CMOS-based pixel electronics
(Possible applications: CLIC, LHC, CBM, etc.)
3) CCPDs based on a pixel sensor implemented as a smart diode array
Vertex 2012, Ivan Peric
Project history
Efficiency at TB: ~98% (probably due
to rolling shutter effects
Seed pixel SNR 27, seed signal
1200e, cluster 2000e
The type 1 chip HVPixelM:
Simple (4T) integrating pixels with pulsed reset and
rolling shutter RO
21x21 µm pixel size
Vertex 2012, Ivan Peric
Spatial resolution
3-3.8µm
Project history
Signals and noise of a CAPSENSE
pixel after 1015neq/cm2
Efficiency - window 800ns
1.0
0.8
Efficiency
Detection efficiency vs. amplitude
CAPPIX/CAPSENSE edgeless CCPD
50x50 µm pixel size
0.6
0.4
0.2
0.0
0
500
1000
1500
Signal [e]
Vertex 2012, Ivan Peric
2000
New projects
65nm UMCLV technology
2006
„Proof of principle“ phase
180nm AMS HV technology
350nm AMS HV technology
Applications:
1) Transmission electron microscopy
integrating pixels with pulsed reset and
rolling shutter RO – in-pixel CDS
2) Mu3e experiment at PSI
Monolithic CMOS pixels with CSA
3) ATLAS (and CLIC)
CCPDs based on smart sensors
Vertex 2012, Ivan Peric
Technology issues – crosstalk
• Capacitive feedback into the sensor (n-well)
• Many important circuits do not cause problems: charge sensitive amplifier, simple shaper, tune
DAC, SRAM but…
• “Active” (clocked) CMOS logic gates and sometimes comparators cause large crosstalk
• Possibility 1: Implement the circuits only using NMOST: effects on radiation tolerance, layout area,
power consumption, etc.
• Possibility 2: Place the active digital circuits on the chip periphery or on separate chip.
• Possibility 3: Isolate PMOST from n-well using an additional standard technology feature – the
deep P-well – we still haven’t tested it…
1.8v
1.8v
PMOS
NW or SN
NMOS
PW
DP
DN
PSUB
Vertex 2012, Ivan Peric
25
Sensor concepts
•
•
•
•
•
Pixel electronics is based on a charge-sensitive amplifier and optionally a comparator.
The pixel signal/address is sent as an analog information.
The signal processed by the digital circuits are on the chip periphery or on a separate chip.
1) Mu3e: The pixel signal is processed on the sensor chip itself -> monolithic pixel detector.
2) ATLAS: intelligent sensor concept. The pixel address is transmitted to an existing readout chip,
like FEI4 or an strip-readout chip.
Readout
Electronics
Pixels
Vertex 2012, Ivan Peric
Readout
Electronics
26
Time walk measurement
•
•
•
The digital part accepts only the comparator signals that are within the trigger window.
Time resolution tests possible.
Time resolution is the sum of time walk and signal collection time.
Test signal
Test signal
Ampl. out
Ampl. out
Comp out
del1
Comp out
Window
Window
del2
Vertex 2012, Ivan Peric
27
Time walk measurement
•
•
•
•
In-time efficiency vs. signal amplitude (40ns time window).
Detection of signals > 1230 e with 40ns time resolution possible.
Power consumption of the pixel 7.5µm.
We expect at least 1500 e from MIPs.
1.0
40ns window
Fit: Mean Val.: 732.20782
Sigma: 172.7808
Efficiency
0.8
0.6
0.4
0.2
0.0
0
1000
2000
3000
4000
5000
6000
Signal [e]
Vertex 2012, Ivan Peric
28
Collection time measurement
•
•
•
Comparison of the response delay to capacitive test pulse (delay only caused by the amplifier)
and the delay to IR pulse (delay caused by the amplifier and collection time).
To assure that amplifier delay is equal, we equalize the signal amplitudes for both injections.
The amplitudes are measured as ToT.
ToT is proportional to the input charge.
It does not depend on the amplifier rise times.
Test signal
Ampl. out
Absorption of 850nm light ~14µm
Similar spatial distribution of the charge generation as for MIPs
1400e
Comp out
N-well
5µ m
60%
drift
del2
IR laser signal
10µ m
Depleted (drift)
Ampl. out
40%
diffusion
1400e
Vertex 2012, Ivan Peric
Comp out
29
Collection time measurement
•
•
Charge collection time – IR laser, comparison with the fast capacitive injection.
No measurable delay versus the capacitive test pulse.
Test pulse
IR laser - 850nm
150
145
0.82
Test pulse
IR laser - 850nm
140
0.81
130
Threshold[V]
Delay [ns]
135
125
120
115
110
0.80
0.79
105
100
0.78
95
0.790
0.795
0.800
Threshold [V]
Vertex 2012, Ivan Peric
0.805
0.810
0
100
200
300
400
4000
Time[ns]
30
High-Voltage CMOS Detectors for ATLAS
Vertex 2012, Ivan Peric
31
High-Voltage CMOS Detectors for ATLAS/CLIC
•
•
•
Smart sensor concept
We use one of the existing RO chips for the readout of a HVCMOS sensor.
This approach simplifies the design of sensor and allows us to use the existing
readout- and data-acquisition-systems.
Vertex 2012, Ivan Peric
32
Strip-like Concept
Vertex 2012, Ivan Peric
33
Pixel detector compatible to strip-readout electronics
•
•
The present LHC strip detectors consist of large-area strip sensors that are
connected by wire bonds to multi-channel ASICs
We use the strip readout ASIC for the readout of our SDA sensor
Readout ASIC (such as ABCN)
Comparator or ADC
Vertex 2012, Ivan Peric
CSA
Wire-bonds
Strip sensor
Strip
34
Pixel detector compatible to strip-readout electronics
•
We replace a strip with a line („gang“) of pixels
Readout ASIC (such as ABCN)
Comparator or ADC
Vertex 2012, Ivan Peric
Wire-bonds
Pixels
CMOS sensor
CSA
35
Pixel detector compatible to strip-readout electronics
•
•
Every pixel generates a digital current pulse with unique amplitude
The pixel outputs are summed, converted to voltage signal and transmitted to readout
ASIC by capacitive coupling
Summing line
Readout ASIC (such as ABCN)
Comparator or ADC
Vertex 2012, Ivan Peric
Wire-bonds
Pixels
CMOS sensor
CSA
36
Pixel detector compatible to strip-readout electronics
•
The pixel address is transmitted as analog information
Summing line
Readout ASIC (such as ABCN)
Comparator or ADC
Vertex 2012, Ivan Peric
Wire-bonds
Pixels
CMOS sensor
CSA
37
Simultaneous readout from two 2D sensitive layers
•
Simultaneous readout from two 2D sensitive layers. Signals from two sensor layers
can be easily combined in a single readout ASIC
CSA
Vertex 2012, Ivan Peric
Comparator or ADC
38
Pixel detector compatible to strip-readout electronics
•
•
•
•
•
•
•
•
A large area CMOS sensor can be produced by stitching several 2cm x 2cm wafer reticles.
Any arbitrary pixel group pattern is possible.
Advantages:
Commercial sensor technology – lower price per unit area.
Intrinsic 2D spatial resolution (e.g. 25 m x 125 m binary resolution)
No need for bias voltages higher than 60V.
Operation at temperatures above 0C is according to tests possible (irradiations to 1015 neq/cm2).
Thinning possible.
Vertex 2012, Ivan Peric
39
CCPD Concept
Vertex 2012, Ivan Peric
40
CCPD for ATLAS pixel detector
•
•
•
We use one of the existing RO chips for the readout of an intelligent HVCMOS sensor.
This approach simplifies the design of sensor and allows us to use the existing readout- and dataacquisition-systems.
Intelligence: the pixels are able to distinguish a signal from the background and to respond to a
particle hit by generating an address information.
We replace the standard bump-bonded sensor with…
Pixel readout chip (FE-chip)
Pixel electronics based on CSA
Bump-bond pad
Bump-bond
Pixel length = 250 μm
Pixel sensor
Vertex 2012, Ivan Peric
41
CCPD for ATLAS pixel detector
•
•
The HV CMOS sensor pixels are smaller than the standard ATLAS pixels, in our case 33μm x
125μm - so that three such pixels cover the area of the original pixel.
The HV pixels contain low-power (~ 7μW) CMOS electronics based on a charge sensitive
amplifier and a comparator.
…the capacitive coupled HV CMOS sensor
Pixel readout chip (FE-chip)
Pixel electronics based on CSA
Coupling
capacitance
Bump-bond pad
Glue
Summing line
Transmitting
plate
Pixel CMOS sensor
Vertex 2012, Ivan Peric
33x 125 μm
42
CCPD for ATLAS pixel detector
•
•
•
•
The electronics responds to a particle hit by generating a pulse.
The signals of a few pixels are summed, converted to voltage and transmitted to the charge
sensitive amplifier in the corresponding channel of the FE chip using AC coupling.
Each of the pixels that couple to one FE receiver has its unique signal amplitude, so that the pixel
can be identified by examining the amplitude information generated in FE chip.
In this way, spatial resolution in - and z-direction can be improved.
Pixel readout chip (FE-chip)
Pixel electronics based on CSA
Coupling
capacitance
Bump-bond pad
Glue
Summing line
Transmitting
plate
Pixel CMOS sensor
Vertex 2012, Ivan Peric
33x 125 μm
43
Advantages compared to existing detectors
•
•
•
•
•
•
•
•
No need for bump-bond connection between the sensor and readout chip – lower price, better
mechanical stability, less material.
Commercial technology – lower price.
No need for bias voltages higher than 60V.
Operation at temperatures above 0C is according to tests possible (irradiations to 1015 neq/cm2).
Increased spatial resolution (e.g. 25m x 125m binary resolution) with the existing FE chip
Smaller clusters at high incidence angles.
Possibility of sensor-thinning without signal loss. Since we do not use bumps and FE chips can be
thinned as well, the amount of material would be very low.
Interesting choice for other experiments where low-mass detectors are needed such as CLIC, ILC,
CBM, etc...
Vertex 2012, Ivan Peric
44
Module concept
Module position in detector
Sensor
Wire bonds for sensor
FE chip
PCB
Vertex 2012, Ivan Peric
Wire bonds for FE chips
45
Advantages compared to existing detectors
•
•
•
•
•
•
•
•
No need for bump-bond connection between the sensor and readout chip – lower price, better
mechanical stability, less material.
Commercial sensor technology – lower price.
No need for bias voltages higher than 60V.
Operation at temperatures above 0C is according to tests possible (irradiations to 1015 neq/cm2).
Increased spatial resolution (e.g. 25m x 125m binary resolution) with the existing FE chip
Smaller clusters at high incidence angles.
Possibility of sensor-thinning without signal loss. Since we do not use bumps and FE chips can be
thinned as well, the amount of material would be very low.
Interesting choice for other experiments where low-mass detectors are needed such as CLIC, ILC,
CBM, etc...
Vertex 2012, Ivan Peric
46
Test Chip HV2FEI4
Vertex 2012, Ivan Peric
47
HV2FEI4
•
•
Pixel matrix: 60x24 pixels
Pixel size 33 m x 125 m
21 IO pads at the lower side for CCPD
operation
40 strip-readout pads (100 m pitch) at
the lower side and 22 IO pads at the
upper side for strip-operation
Pixel contains charge sensitive amplifier,
comparator and tune DAC.
IO pads for strip operation
Pixel matrix
4.4mm
•
•
•
Strip pads
IO pads for CCPD operation
Vertex 2012, Ivan Peric
48
HV2FEI4 - Architecture
12x2
Column control
IO pads for strip operation
Matrix
Cap. Injection
SFOut
Test Pad
20x3
Column control
Strip Pads
Bias DACs
IO pads for CCPD operation
Vertex 2012, Ivan Peric
49
Strip and Test-Operation
Column control SR
Strip bus
R2
R2
L2
L2
R1
R1
L1
L1
R0
R0
L0
L0
Bias A
Pad
Bias B
Pad
Bias C
3
3
SelectL=0
SelectR=0
Row control SR
Mon Pad
33um
125um
Vertex 2012, Ivan Peric
50
CCPD Operation
FEI4 Pixels
Signal transmitted capacitively
CCPD Pixels
Bias A
2
2
Bias B
3
3
Bias C
1
Vertex 2012, Ivan Peric
1
51
Pixel electronics
Amplifier
CCPD electrode
G
SFOut
Filter
BL
Comparator
Output stage
(CR filter)
A
D
D
Th
Cap. Injection
In<0:3>
RW
G
G
Select
4-bit DAC
CCPD bus
Programmable current
Strip bus
Vertex 2012, Ivan Peric
52
6 Pixels – Layout
Tune DAC
Comparator
Amplifier
33 µm
Vertex 2012, Ivan Peric
Experimental results
(strip operation)
Vertex 2012, Ivan Peric
54
Strip-like operation
“Hit-bus” operation – 55Fe signals – three pixel columns (each 24 pixels) readout in parallel
The amplitude is set to be equal for every pixel
Strip like operation – 55Fe signals – three pixel columns (each 24 pixels) readout in parallel
The amplitude depends on pixel position
Vertex 2012, Ivan Peric
55
Strip-like operation
“Hit-bus” operation – 22Na signals – one pixel columns (24 pixels) readout in parallel
The amplitude is set to be equal for every pixel - values around 50mV
0.01
Na irradiation
3000
0.00
2500
-0.01
Amplitude [V]
Signal number
22
2000
1500
1000
500
-0.02
-0.03
-0.04
-0.05
0
0.02
0.04
0.06
-0.06
-5.0µ
0.08
0.0
Amplidude [V]
5.0µ
10.0µ
15.0µ
20.0µ
15.0µ
20.0µ
Time [s]
“Hit-bus” operation –
signals – one pixel columns (24 pixels) readout in parallel
0.01
The amplitude depends on pixel position
22Na
0.00
-0.01
Amplitude [V]
-0.02
-0.03
-0.04
-0.05
-0.06
-0.07
-0.08
-0.09
-0.10
-0.11
-5.0µ
Vertex 2012, Ivan Peric
0.0
5.0µ
10.0µ
Time [s]
56
Strip-like operation
“Hit-bus” operation – test injection pulses (~ 1700e)
The amplitude depends on pixel position
0.075
60
Test injection
0.070
0.065
40
Amplitude
Number of signals
50
30
20
0.060
0.055
0.050
10
0.045
0
0.00
0.02
0.04
0.06
Amplitude [V]
Vertex 2012, Ivan Peric
0.08
0
5
10
15
20
25
Position in row
57
Irradiation at PS (CERN)
Irradiation area
The system allows to read by using the
MONITOR signal, and to write the HV2FEI4 chip
The on-board LVDS chip runs to load
the HV2FEI4 chip.
The Analog current-shaped "Monitor"
signal is read-back and amplified
through an analog amplifier
3,3V
RS232
io
5m
LVDS 20m long cable
4 signals
4 signals
5V max
Lvds
1,8V
DE2 board
0,4V max
Monitor signal 20m long cable
Monitor signal
HV2FEI4
Board n°2
VDDA – VSSA – Threshold – Gate – HV
Vertex 2012, Ivan Peric
Results after 144 MRad
Vertex 2012, Ivan Peric
59
Results after 144 MRad
Rate vs. HV
Leakage current vs. power (HV=30V)
400
120
350
100
Current HV [uA]
AmpOut rate [part/spill]
140
80
60
40
20
0
300
250
200
150
100
50
0
20
40
HV [Volts]
60
80
0
0
20
40
Power [mW]
60
80
40
38
36
34
32
30
28
26
24
22
20
Leakage current vs. HV
500
Current HV [uA]
Temperature [C]
Temperature vs. power
0
50
Vertex 2012, Ivan Peric
100
Power [mW]
150
200
400
300
200
100
0
0
10
20
30
40
HV [Volts]
50
60
70
60
Experimental results
(CCPD operation)
Vertex 2012, Ivan Peric
61
Measurement setup
Vertex 2012, Ivan Peric
62
Measurements with test pad
FEI4
HVCMOS
Injection
Test pad
Vertex 2012, Ivan Peric
63
Measurements with test pad
Mean Val.: 0.57566 V
Sigma: 0.01463 V
1.0
Response probability
Response probability
1.0
0.8
0.6
0.4
0.2
0.0
Mean Val. 1745.0 e
sig 73.0 e
0.8
0.6
0.4
0.2
0.0
0.50
0.52
0.54
0.56
0.58
Test pulse [V]
0.577V -> 2964e =>
Capacitance = 0.824fF
Vertex 2012, Ivan Peric
0.60
0.62
1550 1600 1650 1700 1750 1800 1850 1900 1950
Injected charge [e]
Calibrated input: FEI4 noise 73e
(FEI4 threshold was set to 1300e)
64
Measurements with active pixels and test injection
FEI4
1.0
Mean Val.: 1997.8 e
sigma: 169.6 e
Number of Hits
0.8
0.6
0.4
0.2
0.0
1700
1800
1900
2000
2100
2200
2300
Injected signal [e]
HVCMOS
Injection
Test pad
Vertex 2012, Ivan Peric
65
Measurements with Na22 beta source
Vertex 2012, Ivan Peric
66
Conclusions
•
•
•
•
•
•
•
•
•
•
•
•
We are investigating the use of HVCMOS technology for ATLAS detectors
The concept: Intelligent sensors in HVCMOS technology readout by the existing readout ASCIs
Advantages:
Commercial sensor technology – lower price per unit area.
No need for bias voltages higher than 60V.
Operation at temperatures above 0C is according to tests possible (irradiations to 1015 neq/cm2).
Thinning possible.
Test chip HV2FEI4 has been tested in the stand alone mode and as a CCPD readout with FEI4
First measurements with a strip readout chips will be done soon.
In stand alone mode, we measure good performances of the HVCMOS chip
In CCPD mode, noise somewhat increased due to non optimal setup
Irradiation ongoing, we have reached 180MRad so far, the detector still works – leakage current
increased (temperature: 38C).
Vertex 2012, Ivan Peric
67
Thank you
Vertex 2012, Ivan Peric
68
Backup Slides
Vertex 2012, Ivan Peric
69
Experimental results - overview
HVPixel1 – CMOS in-pixel electronics with hit detection
Binary RO
Pixel size 55x55μm
Noise 60e
MIP seed pixel signal 1800 e
Time resolution 200ns
Capacitive coupled hybrid detector
CCPD2 -capacitive coupled pixel detector
Pixel size 50x50μm
Noise 30-40e
Time resolution 300ns
MIP SNR 45-60
Irradiations of test pixels
60MRad – MIP SNR 22 at 10C (CCPD1)
1015neq MIP SNR 50 at 10C (CCPD2)
HV2FEI4 chip (first test next week!!!)
CCPD for ATLAS pixel detector
Readout with FEI4 chip
Reduced pixel size: 33x125μm
RO type: capacitive and strip like
3 pixels connected to one FEI channel
Monolithic detector –
continuous readout
with time measurement
MuPixel –
Monolithic pixel sensor for
Mu3e experiment at PSI
Charge sensitive amplifier in
pixels
Hit detection, zero suppression
and time measurement at chip
periphery
Pixel size: 39x30 μm (test chip)
(80 x 80 μm required later)
MIP seed signal 1500e (expected)
Noise: ~40 e (measured)
Time resolution < 40ns
Power consumption
7.5µW/pixel
1. Technology 350nm HV – substrate 20 cm uniform
2. Technology 180nm HV – substrate 10 cm uniform
3. Technology 65nm LV – substrate 10 cm/10 m epi
Vertex 2012, Ivan Peric
Monolithic detector frame readout
PM2 chip - frame mode readout
Pixel size 21x21μm
4 PMOS pixel electronics
128 on-chip ADCs
Noise: 21e (lab) - 44e (test beam)
MIP signal - cluster: 2000e/seed: 1200e
Test beam: Detection efficiency >98%
Seed Pixel SNR ~ 27
Cluster signal/seed pixel noise ~ 47
Spatial resolution ~ 3.8 m
HPixel - frame mode readout
In-pixel CMOS electronics with CDS
128 on-chip ADCs
Pixel size 25x25 μm
Noise:60-100e (preliminary)
MIP signal - cluster: 2100e/seed: 1000e
(expected)
SDS - frame mode readout
Pixel size 2.5x2.5 μm
4 PMOS electronics
Noise: 20e (preliminary)
MIP signal (~1000e - estimation)
70
Capacitively Coupled Pixel Detectors
CCPDs
Vertex 2012, Ivan Peric
71
Standard hybrid detector
Pixel
Readout chip
Min. pitch ~50 μm
Bumps
Charge signal is transmitted
Vertex 2012, Ivan Peric
Fully-depleted sensor
Signal charge
72
CCPD with a “passive” sensor
Pixel
Readout chip
Min. pitch < 50 μm
Vertex 2012, Ivan Peric
Fully-depleted sensor
Signal charge
Voltage signal is transmitted
Requires bias resistors on the sensor
Can be implemented as punch-through structure
Signal ~30mV for 250µm thick sensor (Cdet = 100fF)
73
Active CCPD
Pixel
Readout chip
Smart diode- or fully-depleted sensor
Signal charge
Sensor implemented as SDA
Advantage:
Charge to voltage amplification on the
sensor chip
Typical voltage signal ~100mV
Easier capacitive transmission
Can be thinned without signal loss
Signal >30mV for very thin sensors
Vertex 2012, Ivan Peric
74