Atomic Layer Deposition in
Semiconductor Manufacturing
Juan Pablo Trelles
Design and Technology Solutions, Intel Corporation
juan.p.trelles@intel.com
Washington State University, Vancouver, WA
November 7, 2011
1
Outline
1. Overview of Semiconductor Manufacturing
–
Semiconductor industry and work @ Intel
2. Introduction to Atomic Layer Deposition
–
Chemistry, process
3. Industrial ALD Processes
–
–
How to make ALD feasible in industry
Role of Computational Modeling & Simulation
2
1. Overview of Semiconductor
Manufacturing
3
About Intel
• Semiconductor Manufacturing  Silicon, Software, Solutions
– Deliver the “Computing Continuum”
• +90 000 employees worldwide
D1C
D1D
(latest)
• R & D facilities in Hillsboro, OR
• 2 Fabs in OR + 1 new (D1X) in 2012
> 2 Billion $
D1X
(new)
http://download.intel.com/newsroom/kits/22nm/pdfs/Global-Intel-Manufacturing_FactSheet.pdf
4
Integrated Circuits
Integrated circuit ~ electric - logical unit
• Circuit design: logic equations
• Layout:
circuit schematics
 transistors
 layers to be fabricated
C=A&B
logic
•
circuit
layout
Chip ~ 3.5 Billion transistors (contrast: world population 7.0 Billion)
controller
core
Core i7
(4 cores)
shared L3 cache
http://www.intel.com/pressroom/archive/releases/2008/20081117comp_sm.htm
5
Semiconductor Manufacturing
sand
melted Si monocrystal ingot slicing
ingot
wafer
apply
photoresist
exposure
single die
slicing &
selection
wash-off
photoresist
3 main types of processes:
– Deposition of material (CVD, PVD, ALD, EP)
– Removal of material (wet etch, dry etch, CMP)
– Modification of material (litho, implant, annealing)
sort test
metal layers
polishing
electroplating
ready
transistor
exposure
(transis. level)
apply high-k
dielectric
ion
implantation
etching
remove
photoresist
http://www.intel.com/pressroom/kits/chipmaking/
6
Moore’s Law
• “The number of transistors on a chip doubles about every two years”
– Driven by High Volume Manufacturing + Economics
– Drives Semiconductor Research roadmap
# trans./ chip 2011
 106  2 20
# trans./ chip1971
Gordon Moore, Co-founder,
Intel Corporation
http://www.intel.com/pressroom/kits/events/moores_law_40th
• Compared to Intel’s first microprocessor, latest microprocessors …
•
•
•
Run +4000X faster
Each transistor uses +5000X less energy
Price per transistor dropped by +50 000X
7
Technology Development @ Intel
• A New Technology introduced every 2 years (Tic – Toc)
transistor
chip cross
section
interconnects
transistors
chip top
view
~ 300 transistors
http://download.intel.com/newsroom/kits/22nm/pdfs/22nm-Details_Presentation.pdf
red blood cell
http://en.wikipedia.org/wiki/File:
Red_White_Blood_cells.jpg
8
Technology Development @ Intel (cont.)
• New Technology often involve revolutionary innovations …
2013
2015
14 nm
10 nm
? ??
http://download.intel.com/newsroom/kits/22nm/pdfs/22nm-Details_Presentation.pdf
ALD technology enabler
ALD intrinsic in
process development
9
2. Introduction to Atomic Layer
Deposition
10
Atomic Layer Deposition (ALD)
Thin Film deposition process characterized by:
1. Complementary and Self-limiting surface reactions
2. Monolayer thickness control
3. ALD processes often involve cyclic exposures and purges of reactants
Example: GeO2 over crystalline Ge for MOSFETs
~ 1 atom
thickness
Tanaka and Takagi, ECT Trans, 2011
11
Examples & Uses of ALD
Industries:
• Semiconductors
• Micro-Electro-Mechanical Systems (MEMS)
• Nano-Electro-Mechanical Systems (NEMS)
• Displays and OLED Lighting Technologies
• Flexible electronics
• Textiles
Applications:
• Lubrication of moving parts
• Optical coatings (reflective, anti‐reflective, absorbers)
• Corrosion protection
• Increased hardness of the mechanical layer
• Tuning of mechanical properties (i.e., stiffness)
• Charge dissipation
• Hydrophobic surface or uniform nucleation layers
• Protective layers for biocompatible coating of MEMS
• Controlled gap filling, closing on nano‐scale pores
• Hermetic coatings
• Growth of sacrificial layers for small gaps
coating of
nano-particles
nanopores
lining & filling
nanotube
coating
photonic
crystals
A. Londergan (Qualcomm), New Opportunities for ALD in MEMS,
NEMS, Displays and OLED Lighting Technologies, Workshop, Atomic
Layer Deposition, Cambridge, MA, 2011
R. Gordon, Atomic Layer Deposition (ALD): An Enabler
for Nanoscience and Nanotechnology, Harvard University
12
Gas Chemistry Kinetics
• Elementary reaction:
k
A B

CD
1 mole of 
molecules A " collides" with


Reaction rate:
([ ] = molar concentration)
with
1 mole of  produces
1 mole of 
probability k







molecules B 
molecules C 




R  k AB
together with
1 mole of 
molecules D


d [ A] d [ B]
d [C ]
d [ D]



 R
dt
dt
dt
dt
• Example: Hydrogen Bromide synthesis
k
H 2 ( g )  Br2 ( g ) 

2HBr( g )
H
Br
Br
H
Br
H
+
H
Br
13
Surface Chemistry Kinetics
• Similar to Gas kinetics, BUT surface as reactant
• Ex: Silicon deposition from Silane
H
SiH4 ( g )  Si(s)  Si(b)  Si(s)  2H 2 ( g )
(g): gas
(s): surface
(b): bulk
H
H
surface 
+
H
H
Si
H
H
Si
Si
Si
…
Si
bulk 
Si
H
Si
Si
• Film growth occurs by repetitive insertion of bulk species; types:
a) two-dimensional
b) island
c) random
1. R. L. Puurunen, J. App. Phys. 97, 121301 (2005)
14
ALD Chemistry
•
•
Ideal 2-step ALD
chemistry is rarely
(if ever) found
“Complementary Self-Limiting Surface Reactions”
“Canonical” ideal ALD of A-B film
(g): gas, (s): surface, (b): bulk
B(b) in
bi-prod out
A(b) in
bi-prod out
bulk
AB film
time
inject A
k1
A( g )  B( s) 
A( s)  C ( g )  B(b)
insert B
inject B
k2
B( g )  A( s) 
B( s)  C ( g )  A(b)
insert A
precursors
surface termination
bi-products
film
+ D(g), dilutant always present
15
Example: ALD of TiN
• TiN deposition from TiCl4 and NH3
TiCl 4 ( g )  NH 2 ( s)  TiCl 2 ( s)  2 HCl ( g )  N (b)
 N deposition
2 NH 3 ( g )  TiCl 2 ( s)  2 NH 2 ( s)  2 HCl ( g )  Ti(b)
 Ti deposition

  

precursors
intermediate surface termination
gaseousbi- product

products
H. Kim, J. Vac. Sci. Technol. B
21„(6), Nov/Dec 2003
N deposition
Ti deposition
16
Elements in ALD
Elements used in
ALD films
Combination of
elements in ALD films
~ most elements
BUT often: high T,
undesired biprods, expensive,
…
R. Gordon, Introduction to the Chemistry of ALD, Atomic Layer Deposition, Cambridge, MA, 2011 based on data in R. Puurunen,
J. Appl. Phys. 97, 121301 (2005)
17
ALD Process
“Cyclic exposure and removal of
reactants over the substrate”
Typical type showerhead reactor
• Example 2-reactans, 4-stages cycle:
1.
2.
3.
4.
Flow reactant A over substrate for time t1
Evacuate reactant A for time t2
Flow reactant B over substrate, time t3
Evacuate reactant B, time t4
wafer
Flow path
exhaust
B. Devulapalli, Deposition: One Layer at a
Time, Report, Fluent (2003)
A(s)
B(s)
1. R. L. Puurunen, J. App. Phys. 97, 121301 (2005)
18
Molecular Dynamics Simulation of ALD
HfO2 from HfCl4 + H2O on oxidised Si substrate
G. Mazaleyrat, A. Estève, L. Jeloaica, M. Djafari-Rouhani, Comput. Mater. Sci. 33, 74 (2005).
Initial SiO2 surface
19
Molecular Dynamics Simulation of ALD
HfO2 from HfCl4 + H2O on oxidised Si substrate
G. Mazaleyrat, A. Estève, L. Jeloaica, M. Djafari-Rouhani, Comput. Mater. Sci. 33, 74 (2005).
Reaction with HfCl4
20
Molecular Dynamics Simulation of ALD
HfO2 from HfCl4 + H2O on oxidised Si substrate
G. Mazaleyrat, A. Estève, L. Jeloaica, M. Djafari-Rouhani, Comput. Mater. Sci. 33, 74 (2005).
Rearrange of HfCl4 –terminated surface
21
Molecular Dynamics Simulation of ALD
HfO2 from HfCl4 + H2O on oxidised Si substrate
G. Mazaleyrat, A. Estève, L. Jeloaica, M. Djafari-Rouhani, Comput. Mater. Sci. 33, 74 (2005).
Reaction with H2O
22
Molecular Dynamics Simulation of ALD
HfO2 from HfCl4 + H2O on oxidised Si substrate
G. Mazaleyrat, A. Estève, L. Jeloaica, M. Djafari-Rouhani, Comput. Mater. Sci. 33, 74 (2005).
Rearrangement of H2O–terminated surface
One full cycle is completed  repeat
23
3. Industrial ALD Processes
24
Chemistry  Process  Film
Q
gas flow
(Input)
A(g)
A(g)
B(g)
B(g)
injection
purge
injection
purge
t2
t3
t4
t1
.
B(b)
Ideal
.
recipe
(4 stages)
time
A(b)
Real
deposition
rate
AxBy film
(Output)
y
t1
x
t2
t3
t4
time
Ideal Chemistry ≠ Ideal Process
- stage duration = complete surface termination
- no mixing, desorption, gas-phase reactions, etc
25
ALD @ Intel
•
Since High-k Metal Gate  ALD technology enabler
M. Bohr, Silicon Technology for 32 nm and
Beyond System-on-Chip Products, IDF 2009
1st gen high-k metal gate
2nd gen high-k metal gate
3-D tri-gate transistors
Intel Technology Journal, ISSN 1535-864X
DOI 10.1535/itj.1202.01
• ALD for High-Volume Manufacturing (HVM)
o cost (precursors, equipment, throughput)
o control, reliability, yield, …
26
How to Increase Process Throughput?
•
Process conditions:
•
•
•
 limited to avoid gas phase reactions, particles
 limited by substrate, may have complex effect
1. R. L. Puurunen, J. App. Phys. 97, 121301 (2005)
Reactivity:
•
•
•
Pressure
Temperature
Catalysts
Plasma-enhancement
 hard to find, could lead to undesired reactions
 complex, may lead to non-conformal growth
Equipment:
•
•
More substrates
Faster
 advance reactor design
 recipe optimization
All above used in HVM; Equipment most advantage
27
Example: ALD Reactor for HVM
•
Multi-substrate batch reactor: 1 inlet (injector), 1 outlet (exhaust), 4 wafers
exhaust
Qout
injector
Qin
Qin
wafer stack
non-uniform injection
dissimilar flow
resistance
recirculation
stagnation
Flow effects limit ideal ALD
28
Patterned Surfaces & ALD Chemistry
•
ALD in semiconductor technology: (geometric) Multi-Scale
wafer
die
pattern
feature
~ 10 cm
Intel Press Release, Intel First to
Demonstrate Working 45nm Chips, 2006
•
~ 1 um
~ 10s nm
Patterned topography increases substrate area
o
•
~ 1 cm
Process from “diffusion limited” to “reaction limited”
Film evolution at the feature-scale:
ALD film
Profiles of obtained film after
each ALD cycle using detailed
10-step chemistry
29
Deposition Process Example
Conditions:
•
•
•
•
•
•
A(g)
Ideal A-B chemistry
k1 = k2
rQin const.
100% B(s) initial surf. term.
D(g) pressure loading
P ~ Torr (Kn << 1)
A(g) transport
+
Qin
B(s) consumption

B(b) deposition
30
Precursor Transport
A(g)
1
2 3 4 5
6
7
2
3
4
5
non-uniform injection 
different deposition
6
7
A(g)
stagnant precursor 
residual deposition
31
Stagnation & Recirculation
1
1
During research (i.e., no
industrial) ALD, these
peaks are > 5X apart 
below problems not found
2
2
A(g)
B(g)
C(g)
1
C(g)
A(g)
recirculation inside injector:
non-uniform injection, mixing
dragging of stagnant gas:
mixing, non-ALD growth
2
stagnant bi-products:
reduce available Pv
Fluid Flow effects limit applicability of
“estimates” in recipe formulation
32
ALD Recipe
Case
Time
Total Cycle
Time
Purge/Total
Growth
rate
Max
A(s)
I
50% T
1/2
59%
65%
non-ALD
II
50% T
2/3
63%
67%
non-ALD
III
75% T
2/3
93%
99%
~ optimal
IV
100% T
2/3
100%
100%
complete
A(s) fractional coverage
ALD
nonALD
• inj. time  growth rate
• purge time  ALD
• purge time > 2/3 cycle
• “optimal” recipe limited
by flow effects
• optimal:
+25% shorter cycle
-7% growth rate
33
Summary
• Semiconductor Manufacturing
– Industry roadmap driven by Moore’s Law
– Economics of High Volume Manufacturing (HVM)
– Latest node @ Intel: 22 nm, 3D transistors, > 1 Billion transistors / chip
•
Atomic Layer Deposition (ALD)
– Atomic-layer control of Thin Film deposition processes
– Complementary & self-terminating surface reactions
•
ALD for HVM challenges: Throughput
– Fluid Flow effects: recirculation, stagnation, dissimilar transport, etc.
– Increasing process throughput limits “ideal ALD”
– Most cycle time spent in “purges” (i.e., no chemistry) … room for improvement?
34
Notes
• Information about Semiconductor Manufacturing and Intel
– www.intel.com  About Intel  Silicon Innovations
– http://www.intel.com/content/www/us/en/silicon-innovations/silicon-innovationstechnology.html
• Review papers on ALD
– H. Kim, H.-B.-R. Lee, W.-J. Maeng, Applications of atomic layer deposition to
nanofabrication and emerging nanodevices, Thin Solid Films 517 (2009) 2563–2580
– O. Sneh, R. B. Clark-Phelps, A. R. Londergan, J. Winkler, T. E. Seidel, Thin film atomic
layer deposition equipment for semiconductor processing, Thin Solid Films 402 (2002)
248–261
• Intel is doubling number of internships for 2012
– More information and online application:
– http://www.intel.com/jobs/usa/students/internships/
35