Improved Synthesis Tool for Miller OTA Stage Using gm/ID
Methodology
THESIS
Presented in Partial Fulfillment of the Requirements for the Degree Master of Science in
the Graduate School of The Ohio State University
By
Yueh-Ching Teng
Graduate Program in Electrical and Computer Science
The Ohio State University
2011
Master's Examination Committee:
Prof. Mohammed Ismail, Adviser
Prof. Steven B. Bibyk
© Copyright by
Yueh-Ching Teng
2011
ABSTRACT
Modern analog integrated circuit design is mainly based on CMOS technology and is
wildly used in different applications. Analog circuit designs are often complicated by
the choice of design parameters such as channel length, channel width, drain current
and biasing voltage that show up in every MOSFET in the circuits. In this thesis, we
will focusing on an new interpretation of MOS modeling for analog design problems
motivated by the traditional square law models. The design procedure for analog
building blocks are based on gm /Id ratio of the device characterization data. The
design problem and trade-offs can be synthesized by program functions then later
verified by the circuit simulators.
ii
To my parents, Ying-Mou Teng and Yu-Yeh Lin
To Zoe Teng and Pei-Chun Hsieh
iii
ACKNOWLEDGMENTS
I would like to express my deep appreciation to my academic advisor Professor
Mohammed Ismail for his guidance and patience. His kindness for letting me use
Analog VLSI Lab. and being a teaching assistance for the mixed signal course were
invaluable.
I am extremely grateful to Professor Steven B. Bibyk for his generous, encouragement and being in my examination committee.
Finally, I am grateful to my parents for their unconditional supports and faith
they have in me. I would like to thank Pei-Chun Hsieh for providing me love and
courage.
iv
VITA
September 03, 1982 . . . . . . . . . . . . . . . . . . . . . . . . . Born - Chiayi, Taiwan
June, 2005 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .B.S. Chung Yuan Christian University
January , 2011 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Graduate Teaching Assistant ,
the Ohio State University.
FIELDS OF STUDY
Major Field: Electrical and Computer Engineering
v
TABLE OF CONTENTS
Page
Abstract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ii
Dedication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
iii
Acknowledgments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
iv
Vita . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
v
List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ix
List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
x
Chapters:
1.
2.
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1
1.1
1.2
Object of Thesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Organization of Thesis . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
2
MOS Models for Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4
2.1
2.2
MOS Modeling . . . . . . . . . . . . . . . . . .
2.1.1 Why more modeling . . . . . . . . . .
2.1.2 Levels of abstraction . . . . . . . . . .
2.1.3 Square law equation . . . . . . . . . .
2.1.4 Short channel effects . . . . . . . . . .
2.1.5 Modern MOSFET . . . . . . . . . . .
2.1.6 MOSFET Operating Region . . . . .
gm /Id Deisgn . . . . . . . . . . . . . . . . . . .
2.2.1 The Problem . . . . . . . . . . . . . .
2.2.2 Design-Driven Small Signal Modeling
vi
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Derive Design Specifications for Analog Building Blocks in Pipeline ADC
32
3.1
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OTA Design using Gm /Id Method . . . . . . . . . . . . . . . . . . . . . . . .
41
4.1
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Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
82
2.3
3.
3.2
4.
4.2
5.
2.2.3
2.2.4
2.2.5
2.2.6
2.2.7
Signle
2.3.1
2.3.2
Transconductance Efficiency as Design Parameter
Define V* . . . . . . . . . . . . . . . . . . . . . . . .
How to choose V* . . . . . . . . . . . . . . . . . . .
Design Driven Device Characterization . . . . . . .
General Design Flow . . . . . . . . . . . . . . . . . .
Stage Deisgn Example . . . . . . . . . . . . . . . . .
Signle Stage Deisgn Flow . . . . . . . . . . . . . . .
Simulation Results . . . . . . . . . . . . . . . . . . .
Basic Pipeline ACD Structure . . . . . . . . . . . . . . .
3.1.1 Pipeline ADC Topology . . . . . . . . . . . . . .
3.1.2 Pipeline ADC Operation . . . . . . . . . . . . .
ADC Design Specifications . . . . . . . . . . . . . . . . .
3.2.1 How to Choose the Value of Capacitors . . . .
3.2.2 What Are the Specs? . . . . . . . . . . . . . . .
3.2.3 How to Choose Design Specifications for ADC
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OTA Design Considerations . . . . . . . . . . . . . . . . .
4.1.1 Why Using Multi-Stage Amplifier? . . . . . . . .
4.1.2 Design Two-Stage Amplifier . . . . . . . . . . . .
4.1.3 Simple Two-Stage Amplifier Model . . . . . . . .
4.1.4 Simplified AC Model using Capacitive Feedback
4.1.5 Loop Gain for Two-Stage Amplifier . . . . . . . .
4.1.6 Swing . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1.7 Settling Performance . . . . . . . . . . . . . . . . .
4.1.8 Noise . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1.9 Dynamic Range . . . . . . . . . . . . . . . . . . . .
OTA Design Example . . . . . . . . . . . . . . . . . . . . .
4.2.1 Divide and Conquer Design Flow . . . . . . . . .
4.2.2 OTA Design Specs . . . . . . . . . . . . . . . . . .
4.2.3 Simulation Results . . . . . . . . . . . . . . . . . .
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Appendices:
A.
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vii
83
B.
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
88
Bibliography . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
90
viii
LIST OF TABLES
Table
Page
2.1
Square law model vs. Short channel model . . . . . . . . . . . . . . . .
6
2.2
Vod vs. V ∗ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20
4.1
ωp2 /ωc vs. P haseM argin . . . . . . . . . . . . . . . . . . . . . . . . . . .
67
4.2
Target Specifications for OTA . . . . . . . . . . . . . . . . . . . . . . . .
75
4.3
Spectre Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . .
77
4.4
Compare Matlab and Spectre Simulation Results . . . . . . . . . . . .
78
ix
LIST OF FIGURES
Figure
Page
2.1
Output Resistance Mechanisms . . . . . . . . . . . . . . . . . . . . . . .
8
2.2
Velocity Saturation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9
2.3
Modern MOSFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11
2.4
Reverse short channel effect . . . . . . . . . . . . . . . . . . . . . . . . .
12
2.5
Sub-Threshold Region . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13
2.6
Moderate Inversion Region . . . . . . . . . . . . . . . . . . . . . . . . . .
14
2.7
The Problem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15
2.8
SPICE Monkey . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16
2.9
Figure of Merit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19
2.10 Figure of Merit for NMOS and PMOS . . . . . . . . . . . . . . . . . . .
19
2.11 Device Scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
22
2.12 fT and gm /Id trade-off
. . . . . . . . . . . . . . . . . . . . . . . . . . . .
22
2.13 fT and gm /Id design case . . . . . . . . . . . . . . . . . . . . . . . . . . .
23
2.14 Composite Figure of Merit . . . . . . . . . . . . . . . . . . . . . . . . . .
24
2.15 Device Characterization . . . . . . . . . . . . . . . . . . . . . . . . . . . .
25
x
2.16 SPICE Netlist for Device Characterization . . . . . . . . . . . . . . . .
26
2.17 General Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
27
2.18 Simple Common Source Amplifier . . . . . . . . . . . . . . . . . . . . . .
28
2.19 Circuit to Find Gate Biasing Voltage Under Constant Drain Current
30
2.20 Common Source Stage Simulation Result . . . . . . . . . . . . . . . . .
31
2.21 Short Channel Device Design Solution . . . . . . . . . . . . . . . . . . .
31
3.1
Pipeline ADC Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . .
33
3.2
S/H Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
35
3.3
Multiplying DAC (MDAC) . . . . . . . . . . . . . . . . . . . . . . . . . .
35
3.4
MDAC Equivalent Model for Noise Calculation . . . . . . . . . . . . . .
37
4.1
Single Stage Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
42
4.2
Two Stage OTA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
43
4.3
Simple Model for Two-Stage Amplifier . . . . . . . . . . . . . . . . . . .
44
4.4
AC Model using Capacitive Feedback . . . . . . . . . . . . . . . . . . .
45
4.5
Bode Plots of Two-Stage Amplifier . . . . . . . . . . . . . . . . . . . . .
47
4.6
Bode Plots of Two-Stage Amplifier After Narrowbanding . . . . . . . .
47
4.7
Miller Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
48
4.8
Pole Splitting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
49
4.9
Typical Gain and Phase Marge with Right Half Plane Zero . . . . . .
51
4.10 Miller Compensation and Nulling Resistor . . . . . . . . . . . . . . . . .
53
4.11 Movement Diagram with Varying Nulling Resistor . . . . . . . . . . . .
54
xi
4.12 Output Swing of Second Stage . . . . . . . . . . . . . . . . . . . . . . . .
56
4.13 Vic=Voc=Vdd/2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
57
4.14 Low Frequency Gain and Large Signal Characteristic . . . . . . . . . .
58
4.15 Step Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
59
4.16 Closed Loop Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
61
4.17 Closed Loop Amplifier with Cload . . . . . . . . . . . . . . . . . . . . .
62
4.18 p/z . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
63
4.19 K value vs. ε . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
65
ωp2
ωc
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
66
4.21 Circuit for total integrated noise . . . . . . . . . . . . . . . . . . . . . .
68
4.22 Dynamic Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
70
4.23 Two Stage OTA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
71
4.24 General Design flow for an OTA
. . . . . . . . . . . . . . . . . . . . . .
72
4.25 Design Flow Used in the OTA Design . . . . . . . . . . . . . . . . . . .
74
4.26 Current Optimization Plot . . . . . . . . . . . . . . . . . . . . . . . . . .
76
4.27 Input Step and Output vs. Time . . . . . . . . . . . . . . . . . . . . . .
79
4.28 Settling Error vs. Time
. . . . . . . . . . . . . . . . . . . . . . . . . . .
79
4.29 Loop Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . .
80
4.30 Output Swing Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
80
4.31 Noise Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . .
81
4.20 PM vs.
xii
A.1 NMOS Transit Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . .
83
A.2 PMOS Transit Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . .
84
A.3 NMOS Intrinsic Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
85
A.4 PMOS Intrinsic Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
85
A.5 NMOS Composite FoM . . . . . . . . . . . . . . . . . . . . . . . . . . . .
86
A.6 PMOS Composite FoM . . . . . . . . . . . . . . . . . . . . . . . . . . . .
86
A.7 NMOS Current Density . . . . . . . . . . . . . . . . . . . . . . . . . . . .
87
A.8 PMOS Current Density . . . . . . . . . . . . . . . . . . . . . . . . . . . .
87
xiii
CHAPTER 1
INTRODUCTION
With advancing technologies in modern semiconductor fabrication, device shrinking
and supply voltage lowering posing challenges for circuit designers. Demand for accurate device models for design using deep submicron transistors is high [1]. Unlike
digital circuit design, the level of abstraction in analog design can not be easily defined and synthesized by the softwares. Analog circuit design is challenging because
the design process targets complex design specs [2]. The parameters of the transistor
models used in analog design procedure are technology dependent, therefore, migrating any existing designs to the new processing technologies is slow and costly, every
design must be customized and optimized separately.
Nowadays, due to the shrinking supply voltage and other constraints, operating
transistor near moderate or weak inversion regions is attractive for low power circuit
design because it provides good trade-offs between speed and power [3]. The idea
of gm /Id methodology is to based on a unified treatment of all the operation regions
of MOSFET [3]. The gm /Id methodology is based on the ratio of transconductance
over the drain current, a pure DC metrics that cover all the short channel effects
[4, 3, 5]. The gm /Id metric is a universal characteristics for transistors in different
processing technologies. The idea proposed in [1] is the combination of V ∗ design
1
method and gm /Id design methodology. Using V ∗ in the design process helps the
designer using pre-existing analog design instincts of square law equations to design
circuits in submicron technologies. The advantages of V ∗ method/modeling are: first,
it is easy to learn, unlike gm /Id based on EKV modeling contains lots of equations that
can not be transferred into design intuitions, the V ∗ modeling equations are mainly
adopted from the square law equations. We can use the analogy of Vdsat , Vod , Vov to
design circuits in submicron technologies, second, as shown in the thesis, the design
procedure using gm /Id methodology can be realized through simple pre-simulated
charts and Matlab scripts, therefore, it is easy to maintain, modify and customize for
any design targets.
1.1
Object of Thesis
The gm /Id methodology adopted in this thesis is to help us designing analog
circuits in submicron technologies. The work is motivated by basic circuit design
challenges: sizing up the transistors in modern processing technologies. By understanding basic characteristics of modern MOSFET, a simple and new design equation
based on transconductance efficiency has been utilized in the design process. A complex design problem without close form solution can be iterated efficiently by using
Matlab design script based on gm /Id method.
1.2
Organization of Thesis
The following chapters of the thesis are organized as follows: a brief introduction
to the modern MOSFET devices and short channel effects will be presented in Chapter2. A single transistor design example will be shown in the last part of Chapter 2.
2
In Chapter 3, we will discuss the basic building blocks of pipeline ADC and discuss
how to derive design specs.
In Chapter 4, we will apply the gm /Id design method on the two-stage OTA
design. We will go trough various design considerations of the two-stage OTA and
discuss the design trade-offs that been used in the design scripts. An design flow for
two-stage OTA is shown in Chapter 4. The last part of Chapter 4 is a two-stage design
example using Matlab script based on gm /Id method. Finally, Chapter 5 concludes
the work in the thesis and discusses how to extend the usage of synthesis tool.
3
CHAPTER 2
MOS MODELS FOR DESIGN
In this chapter, we will introduce modelings of the MOSFET and the general gm /Id
design method. In the modeling section, we will discuss the reason to use new modelings and will briefly discuss the short channel effects and operation regions of the
modern MOSFET. In the gm /Id design section, we will discuss gaps between design
equations and the actual implementations. A design driven small signal modeling
will be introduced. We will define a new design parameter called V* and discuss its
role in the design process. Last but not least, we will introduce the design driven
characterization of the modern MOSFET. A simple SPICE netlist was given and the
simulation results could be found in the Appendix A.
2.1
MOS Modeling
2.1.1
Why more modeling
In digital circuit design, we can create some kind of margin, such as noise margin to simplified the design problems. As long as the circuit meet these constraints,
circuits will behave well within the desired specs. That is, digital circuits have larger
”margin of errors” to play with[5]. However, in analog circuit design, the circuit performance is usually rely on precise currents, voltages, etc [5]. In other words, analog
4
circuits are more sensitive to the transistor behaviors [5]. There is no way for a circuit designer to design analog circuits consider every details in physical devices and
process parameters. A design engineer needs good abstraction and design intuitions.
Therefore, models and simulators such as SPICE provide tools for thinking/verifying how circuits might behave during the design process. Doing experiments with
simulator is much cheaper and easier to do than waiting for the IC tape-out results.
2.1.2
Levels of abstraction
Derive proper abstraction for any circuit design is crucial. The best abstraction
usually depends on what goals that the designer wants to achieve [5]. In digital circuit
design problem such as digital delay, a MOS can be treated as a current source and
a switch driving some load capacitors. We can create levels of abstraction based on
digital functionality and digital performance [5]. However, creating analog abstraction
is not as simple as digital abstraction. A modern MOSFET device described by
BSIM models contains hundreds of parameters. Therefore, the analog characteristics
described by models are too complicated to come up with simple abstractions for
different analog circuits. Designing analog circuits based on measurement results is
not possible, because there is no way for designers to remember every device I-V
characteristics or physical details in the element during the design process.
2.1.3
Square law equation
We can find the MOSFET square law equation in almost all microelectronics
textbooks and analog circuit design books. The square law model is well known:
W
1
ID,sat = ⋅ µn ⋅ Cox ⋅ ⋅ (VGS − Vth )2
2
L
5
(2.1)
the equation is based on charge and velocity assumptions. That is, the equation is base
on Q × v, charge times velocity. We assumed that the charge Q is only related to the
Vgs and the velocity v is only proportional to the VDS or µ × E. The square law model
is good approximation for long channel devices but totally inadequate to describe
short channel behaviors [5, 6]. In short channel devices, due to velocity saturation,
the velocity v is no longer proportional to µ × E in all operation conditions. The
charge Q is not only related to the Vgs but is also a function of VDS , Q ≈ f (Vgs , VDS ).
It turns out that the velocity v is also a function of Vgs , the vertical field.
Square Law Model
Charge density only determined by vertical field
Drift velocity only set by lateral field
Neglect diffusion currents
Constant mobility
Short Channel Model
Q ≈ f (Vgs , VDS )
velocity ≈ (verticalf ield, lateralf ield)
Vth varies with biasing
Mobility reduction
Table 2.1: Square law model vs. Short channel model
[5]
2.1.4
Short channel effects
The Channel length modulation(CML) is one of the common second order approximations for MOSFET equation. The change of VDS cause the depletion region
to vary and also change the effective channel length. If the change of channel length
is small, then [5]:
I∝
1
1
δL(VDS )
Ids
≈ (1 +
) Ð→
= (1 + λVds )
L − δL(VDS ) L
L
Ids0
(2.2)
One other observation from modern MOSFET device is that the Vth goes down with
the increasing of drain voltage. This is called the drain induced barrier lowering
6
(DIBL) effect. Because the drain region of the MOSFET imaged some charges on
the channel, the gate node need less voltage to mirror the charge onto the channel,
therefore, the effective Vth is lower. It can be modeled as [5]:
Vth = Vth0 − ηVDS
(2.3)
The source and substrate of the MOSFET formed a P-N diode. At high electric field,
some moving electrons may have enough energy(hot electrons) and will knock off
electrons of Si lattice(impact ionization) to create currents and may eventually cause
junction to break down(avalanche breakdown). This is called substrate current body
effect(SCBE) [5]. In other words, if we push drain voltage to high enough level, the
drain current ID (not IDS ) and substrate current will suddenly increase. In modern
devices the brake down voltage may not be high, usually between 1.5 ∼ 2V [5]. If
device operated in SCBE dominated region for a long time, the electrons may be
trapped in the gate oxide and create defects and cause long term problem. From the
analog circuit designers stand point, the SCBE may lower the output resistance so
operating MOSFET in SCBE region is probably not a good choice.
Fig. 2.1 shows the drain current and output resistance with different VDS . All
effects are active simultaneously. Regions on the Fig. 2.1 indicate what effect dominate
at that voltage range. The cure formed by circles is the drain current curve, output
resistance curve is represented by squares. As we can see from the Fig. 2.1, the
CML kicks in at relatively low fields, the DIBL dominates the high field and the
SCBE happens at very high fields. From Fig. 2.1 we can clearly see that the output
resistance is not constant after the MOSFET device left triode region. Instead of
showing sharp transition between triode region and the saturation region that square
law model predicted, Fig. 2.1 shows gradual transition for the output resistance curve
7
in different operation regions. One may suggest that in order to get more gain from
the device, we need higher output resistance. Therefore, biasing the transistor in the
region where the DIBL effect dominates seems to be a good idea. However, in most
analog circuits design require some finite swing, biasing transistor in the DIBL region
is not a good idea. In fact, most modern analog circuits design will biasing transistors
in the CML region, the output resistance has big variation in the CML region.
Figure 2.1: Output Resistance Mechanisms
[5]
Every material have speed limit, compared to GaAs and other materials, the
speed limit of silicon (Si) is higher. In Fig. 2.2, we can see the drift velocity increase
8
linearly with the field in the beginning. As the filed gets higher, the carriers reach
the speed limit and the ID ∝ (VGS -Vth ) [5]. Another effect is vertical field mobility
reduction. As the gate voltage increases, it not only change the charges on the channel
but also affect how fast the channel charges can move, as a result, mobility depends
on gate (vertical) field. The reason is that the electric filed pushes carriers toward
the surface and the additional scattering lower the mobility of the charge [5]. Both
velocity saturation and mobility reduction caused by vertical field will cause gm to
vary, we will discuss it later.
Figure 2.2: Velocity Saturation
[5]
9
2.1.5
Modern MOSFET
Fig. 2.3 shows cross section of modern MOS transistor. As we can see in Fig. 2.3
(a), the depth of source or drain junction is roughly equal to the length of the channel.
The p-substrate is not uniformly doped, instead, it usually uses highly non-uniform
doping called retrograde doping to reduce the body effect. The doping level near
the channel is lower. The high doping level on the substrate makes the depletion
region smaller, therefore, the device behaves better. The pocket (halo) implements
under the drain and source area prevent drain and source depletion regions to connect
together(punch trough). The increased doping level in the channel will cause output
impedance to increase, junction capacitance will increase too. The gate oxide is very
thin so that some of the electrons can tunnel directly trough the barrier, in many
cases, it is not characterized by device models. If the circuit is sensitive to the gate
input current, care must be taken to ensure that the gate leakage current will not
degrade the circuit performance.
10
(a) A real transistor
(b) Side view
Figure 2.3: Modern MOSFET
[5]
In Fig. 2.4 (a), the transistor without halo doping has constant Vth , as the channel
length shrinks, two depletion regions eventually touch each other and cause the Vth to
go down. With halo doping, the Vth is higher when channel length is shorter. This is
11
because the effective doping level in the channel is higher, larger Vth means the device
needs more voltage to image charges on the channel. For modern process with halo
doping, if we want Vth of the transistor to be lower, we can use transistor with longer
channel length. As shown in Fig. 2.4 (b), the effective doping level in the channel of
longer device is lower, therefore, the Vth is lower than short channel devices.
(a) Vth vs. Channel Length
(b)
Figure 2.4: Reverse short channel effect
2.1.6
MOSFET Operating Region
In real MOSFET operation, when VGS ≤Vth , the current does not go to zero, the
device is in the sub-threshold region. The current in or near the sub-threshold region
have exponential behavior as shown in Fig. 2.5, this is because the transistor itself
forms a lateral BJT [5]. The sub-threshold or weak inversion current is dominate by
the diffusion current. The current equation is similar to the BJT current equation:
12
Ids =
q(Vgs −VT )
−qVDS
W
⋅ Ids,0 ⋅ e nkT ⋅ (1 − e kT ), n > 1.
L
(2.4)
The base of this lateral BJT is controlled by the capacitive divider (see Fig. 2.5).
The non-ideal factor of channel control n varies with bias, the typical number for n is
about 1.5. Because tiny current driving large capacitor Cgs , operate MOS device in
weak inversion region is usually slow. However, some modern sub-micron processes,
device can get relative high speed even operate in the weak inversion region, some
low power circuits usually operate in the weak inversion region. In the weak inversion
region, the Vth matching is poor and the model is not well defined [5].
Figure 2.5: Sub-Threshold Region
[5]
13
Operating transistors in strong inversion region cost more power, operating transistors
in weak inversion region is slow. Why can’t we operate devices in the region between
weak and strong inversion regions? The region between weak and strong inversion
regions is called moderate inversion region Fig. 2.6. In moderate inversion region, the
current is composed of both drift and diffusion current. With the shrinking supply
voltage, operating transistors in moderate region is attractive. However, no closed
form equation exist for the moderate inversion region [5, 6]. Some models such as
EKV uses weak and strong inversion equations to interpolate the moderate inversion
region. The EKV models or BSIM models are too complicated to generate any close
form equations for traditional hand analysis. From the designer’s stand point, simple
and effective hand analysis model to build design intuitions is necessary. Often times,
question such as what channel width should I use to get certain gm is what a circuit
designer cares most.
Figure 2.6: Moderate Inversion Region
[5]
14
2.2
gm /Id Deisgn
2.2.1
The Problem
Once we learn some neat circuit design theories and hand analysis techniques
by taking courses and reading books. Given a set of design specifications, we may
start our design by using simple hand analysis equations such as MOSFET square law
equation. However, when we open the modern device models such as BSIM model,
usually we can’t find µ⋅Cox , λ or any parameters that we are familiar with. The
equations used in BSIM models or any other models are too complicated for hand
analysis. From a designer’s stand point we need something to gain useful intuitions,
not a pile of equations. Furthermore, from previous sections we already know that
there is a huge discrepancy between modern CMOS models and traditional square
law equations. All these discrepancies posing a challenge for modern circuit designer,
as shown in Fig. 2.7.
Figure 2.7: The Problem
[6]
15
The lack of good hand analysis models to design circuits forcing many designers to
give up hand calculation/analysis, they iterate their design problem in the simulators
until they somehow meet the design specs. Even the circuit meet the design targets,
usually, the design is not guarantee to be optimal. In other words, this issue or
challenge turns many designers into ”SPICE Monkey”, Fig. 2.8 [6]. Normally, any
design should be based on a systematic analysis and reasonable considerations, the
simulator is just a calculator to check the design meet the specs or not.
Figure 2.8: SPICE Monkey
[6]
2.2.2
Design-Driven Small Signal Modeling
Circuit designer, unlike layout designer care mostly about W and L, they care
about gain, bandwidth, noise, power, swing and etc [5]. We need something that
tells us critical parameters such as gm , ro , CGS , CGD without resorting to the actual
16
equations in the modern device models. The idea is simple, we want to use circuit
simulators as a lookup table to design circuits [5] [6].
The transconductance gm of MOSFET using square law model operating in the
saturation region have the following equations:
¿
WÁ
À 2Ids
gm = µCox Á
L
µCox W
L
(2.5a)
√
gm =
2µCox
√
W
Ids ∝ Ids
L
(2.5b)
W
1
1
gm = ⋅ µn ⋅ Cox ⋅ ⋅ (VGS − Vth )2 1
2
L
2 (Vgs − Vth )
gm =
2⋅ Ids
2⋅ Ids
=
(Vgs − Vth )
Vod
(2.5c)
(2.5d)
The overdrive voltage Vod or so called Vdsat found in equation (2.5d) tells us two
things, swing and transconductance efficiency. The lower the the Vod , the higher the
swing and more gm you get per unit current you spent.
The MOSFET operating in the weak inversion region have Ids and gm :
Ids ≈
q(Vgs −VT )
W
⋅ Ids,0 ⋅ e nkT
L
∂IDS
gm =
=
∂VGS
gm =
(2.6)
q(Vgs −VT )
nkT
W
L ⋅ Ids,0 ⋅ e
n kT
q
IDS
∝ IDS
n kT
q
17
(2.7a)
(2.7b)
Therefore, if we simulated the MOSFET and plot gm vs. VGS . In the weak inversion
region, gm is proportional to VGS following the exponential behavior described in
(2.7b). In strong inversion region, gm is linearly proportional to the VGS as described
in equation (2.5c). Comparing the transconductance gm of BJT and MOSFET, where
gm BJT =
IC
Vt
and gm F ET =
2Ids
Vod .
We found that for the given ID , BJT has larger gm . In
other words, for a given current, BJT has better transconductance efficiency. This is
because Vod is much larger than Vt = kT
q ≈ 26mV . What if we make Vod close to Vt ?
This will cause MOSFET to operate in the sub-threshold region and give out better
gm efficiency. However, the operation speed in sub-threshold region is slow [5, 6].
2.2.3
Transconductance Efficiency as Design Parameter
We can always determine the
gm
ID
ratio of any MOSFET. All we have to do is take
the device and measure it’s current. To get gm , we take the derivative of that drain
current with respect to gate voltage. By using simulator, we can always determine the
gm
ID
regardless of any short channel effect or complex modeling equations. As shown
in Fig. 2.9, we can drive the simulator to give us the answer that we care about:
gm
ID .
We can always plot gm vs. ID of MOSFET for any process technology because it
is a pure DC metric. From Fig. 2.9 we known that before the moderate inversion
or sub-threshold regions, the curve can be approximated by
equation used in the sub-threshold region is
by
1
n kT
q
The
gm
ID
gm
ID
=
1
n kT
q
similar to the BJT device. The ideal limit of
of MOSFET has extra n factor in
1
n kT
q
gm
ID
=
2
(Vgs −Vth )
. Notice that the
gm
ID
of BJT is
gm
ID
=
2
Vod .
The
gm
ID
is limited
1
≈ 38V −1 .
=
kT
q
of the sub-threshold region, therefore,
the MOSFET can never reach the ideal 38V −1 value [5, 6]. The capacitive divider
between the oxide and depletion region as shown in Fig. 2.5 reduce the effective
18
voltage at the channel of the MOSFET. One interesting discovery is that weak and
moderate inversion regions are clearly the most efficient regions to operate in [5].
Form Fig. 2.10, we can see that the transconductance efficiency metric is mostly
independent of device types.
Figure 2.9: Figure of Merit
Figure 2.10: Figure of Merit for NMOS and PMOS
19
2.2.4
Define V*
After we see that the transconductance efficiency is a good design parameter, we
can take equation (2.8a) and define a new parameter called V* [1, 5].
2
2
gm
=
=
ID (Vgs − Vth ) Vod
V∗ ≡
(2.8a)
2ID
gm
2
⇐⇒
= ∗
gm
ID V
(2.8b)
In square law model, V ∗ = Vdsat = Vov = Vod = VGS − Vth as we can see in equation (2.8a).
We define V ∗ for modern MOSFET not because real device behave like square law
device. Because it is simple and useful. It allows us to by analogy, think about how
to pick V ∗ in the same way as to pick Vod for the square law device. We already
know that the real MOSFET do not obey square law equations [5]. So how does V ∗
work? For example, if we have a V ∗ = 200mV , that means we have
gm
ID
= 10V −1 . If we
lower the V ∗ to 150mV, for the same current, we will have better transconductance
efficiency and potentially higher swing, we will have larger device, therefore, more
parasitic capacitance.
Vod
Overdrive voltage Vod
▷ Cannot be measured
▷ Complex equations
Long channel device
▷ V ∗ = Vod = Vdsat
▷ Id ∼ V ∗2
▷ Boundary between triode and sat. region
▷ ro is constant for VDS > Vod
V∗
V = 2ID /gm
▷ Measure(simulate) easily
▷ Complex equations
Short Channel device
▷ All interpretation of V ∗ are approximations
D
∗
▷ Except V ∗ = 2I
gm (but V ≠ Vdsat )
Table 2.2: Vod vs. V ∗
[5]
20
∗
Equation (2.9) shows figures of merits for device characterization [3, 6]. Since
we can use the analogy between V ∗ and Vod , these equations can help us determine
the V ∗ value during the design process. From equation (2.9a) we know that we want
high gm but low current. From equation (2.9b) we know that both smaller channel
length and higher V ∗ lead to higher fT . We want large gm but small Cgg . As we will
see in Fig. 2.11, the fT goes up substantially with the processing technology. For a
given 10GHz target, if we use 0.18µm device to replace the 0.25µm device, the V ∗
will goes down and the operation of the transistor is faster, we also scale down the
current that we have to spend to get the same fT in 0.25µm device.
2.2.5
Transconductance efficiency
2
gm
=
ID Vod
(2.9a)
Intrinsic gain
gm
2
≈
g0 λVod
(2.9b)
Transit frequency (fT )
gm 3 µVod
≈
Cgg 2 L2
(2.9c)
How to choose V*
By taking a MOSFET and connect its gate and drain and doing a voltage sweep
in the simulator, we can plot Vgs vs. fT and gm /Id , as shown in Fig. 2.12. Base on
the plot we found that if we make Vgs larger, generally we will get more gm (ignore
vertical filed degradation) and the fT will go up. Equation (2.9c) predicted these
trends. Therefore, if we want fast device, we want large Vgs and device with smaller
channel length (Fig. 2.11), but if we want a good current efficiency, we want low
Vgs (low current density region) to operate the device in moderate or weak inversion
21
region. To have higher transconductance efficiency, the Vgs is lower and the device
is larger, which means we have lower gm per unit capacitance, therefore, it is slower.
All the trends described above can be seen in Fig. 2.12.
Figure 2.11: Device Scaling
[1]
Figure 2.12: fT and gm /Id trade-off
[1]
22
If we have a design target ωu = 1GHz, we can set our device fT = 5GHz. Now the
question is how to find the gm /Id range. If we choose high gm /Id , the device fT will
be lower than 5GHz. On the other hand, if we choose low gm /Id , we will meet the fT
target but wasting current. We can see these trade-offs in Fig. 2.13 .
Figure 2.13: fT and gm /Id design case
[1]
Because many of the circuit performance parameters that we care about would be
directly related to the gm /Cgg or fT . We can plot composite figure of merits as fT
times gm /Id vs. Vod shown in Fig. 2.14. As we can see in the Fig. 2.14, the peak
performance choice of the V ∗ would be somewhere around 100mV to 200mV in this
plot. This magic V ∗ voltage range is a nice trade-off between the device fT and
23
the current efficiency. For many applications, the biasing point of MOSFETs would
probably near or at the moderate inversion region, because in this region we get pretty
good efficiency, moderate speed(fT ) and reasonable gm /ID . Notice that the magic
voltage range is processing dependent and it is not truly optimal for any particular
circuit design. For particular circuit design, if we want high gm /ID , we are going to
increase the intrinsic capacitance of the device because the device is larger. Depending
on the load capacitance, bandwidth and the intrinsic capacitance, every design is
independent and the optimization of that design is based on different considerations,
there is a certain ratio between the intrinsic capacitors of the transistor and the load
capacitor to get the best result. However, given any processing technology, we can
always make this composite figure of merit plots by using different channel lengths
to see what would be the magic voltage range. We can use this voltage range in the
beginning of the design process.
Figure 2.14: Composite Figure of Merit
[1]
24
2.2.6
Design Driven Device Characterization
So far we known that we can always characterize the device by measuring the
Id , gm in the simulator and choose V ∗ . Therefore, given a device modeling file (e.g
BSIM), we can generate plots of parameters in equation (2.9) with respect to the gm /Id
[6, 4]. By using simple configuration in Fig. 2.15, we can generate several useful plots
for hand analysis. A simple SPICE netlist file shown in Fig. 2.16 demonstrate how
to generate these useful plots. All plots generated by the SPICE netlist shown in
Fig. 2.16 can be found in Appendix A.
Figure 2.15: Device Characterization
[6]
25
Figure 2.16: SPICE Netlist for Device Characterization
2.2.7
General Design Flow
Fig. 2.17 shows the general design flow by using pre-simulated plots and the
gm /Id design method. Normally, our design target would require certain amount of
gain, therefore, we should determine how much gm that we need first. After we found
the range of gm that we needed, we can look at the intrinsic gain charts to find what
channel length should be used. Based on the unity gain bandwidth or current budget
26
we can determine the gm /Id or the ft of the device. Once we determine the L, gm /Id
or the ft of the device, we can determine device width based on the current density
charts. The above description is just a general design flow using gm /Id design method.
The design flow may be changed based on the actual constraints, circuit specs and
many other things [4].
Figure 2.17: General Design Flow
[4]
2.3
Signle Stage Deisgn Example
In this section, we will design a simple common-source amplifier based on the
design flow shown in Fig. 2.17.
27
2.3.1
Signle Stage Deisgn Flow
Fig. 2.18 shown a simple common source amplifier configuration with Cload on
its output. The design targets are as follows:
DC gain
Av0 ≥ 100 [V /V ]
(2.10a)
Unity Gain Frequency
fu = 100M Hz
(2.10b)
Load Capacitance
Cload = 5pF
(2.10c)
Figure 2.18: Simple Common Source Amplifier
28
First we need to determine the channel length based on the gain requirement. This
can be achieved by looking at the intrinsic gain charts. Once we decided the channel
length, we can calculate the gm by using gm ≈ 2 ⋅ π ⋅ fu ⋅ Ccload which is equal to
3.14mS. Based on the composite figure of merit plots, we choose V ∗ to be 200mV
in the processing technology that we used here. Using equation (2.8b), we can found
that the drain current is equal to 314µA. After we known the channel length, drain
current and V ∗ value, we can determine the width of the transistor by using the
current density charts. Based on the device characterization charts we can derived
the device width to be 24.634µm.
2.3.2
Simulation Results
After we determined all the parameters of common-mode stage, we can use circuit
shown in Fig. 2.19 to find the gate biasing voltage for the V ∗ that we choose. The
circuit in Fig. 2.19 allow us to sweep the drain voltage of the device under constant
basing current. The ideal amplifier form a feedback loop to generate proper gate
biasing voltage.
29
Figure 2.19: Circuit to Find Gate Biasing Voltage Under Constant Drain Current
Fig. 2.20 shows that the simulation result meet both the unity gain frequency and
the gain requirement. By using the pre-simulated device characterization charts and
gm /Id design methodology, we can bridging the gap between hand analysis and the
modern device models, as shown in Fig. 2.21 [6]. The discrepancies between gm /Id
design results and the actual simulations results are usually on the oder of 10 ∼ 20%,
mostly due to the assumptions that we made during the gm /Id design procedure [6].
Even we found the discrepancies in the simulation results, we can always look back to
our gm /Id derivations to track down the root causes [6]. The square law calculations
are based on inappropriate parameters that do not exit or have no significant impacts
in the modern spice models [6].
30
Figure 2.20: Common Source Stage Simulation Result
Figure 2.21: Short Channel Device Design Solution
[6]
31
CHAPTER 3
DERIVE DESIGN SPECIFICATIONS FOR ANALOG
BUILDING BLOCKS IN PIPELINE ADC
In this Chapter, we would like to introduce the structure and basic operation of
the pipeline ADC. After we understand the basic ideas of the pipeline ADC, in the
second part of this chapter we will discuss how we come up with the basic designing
specifications for the ADC. The design specifications used in Chapter 4 are based on
the derivation introduced in Chapter 3.
3.1
Basic Pipeline ACD Structure
3.1.1
Pipeline ADC Topology
The pipeline ADCs are commonly used in modern electronic applications. The
main feature of the pipeline ADC is that it trades accuracy with latency. Fig. 3.1
shows the basic pipeline ADC topology, the basic building blocks are:
32
1. Sample and Hold Circuit
2. Multiplying DAC (MDAC) Circuits
▷ Sample and Hold
▷ DAC
▷ Subtractor
▷ Gain Amplifier
3. Sub-ADC Circuits
4. Synchronization Circuits
5. Digital Error Correction Circuits
Figure 3.1: Pipeline ADC Topology
[7, 8]
33
3.1.2
Pipeline ADC Operation
A generic pipeline ADC consists of N cascade stages, each resolve B-bit. In each
stage, the analog input signal is first sampled and held then coarsely quantized by
a sub-ADC circuit to resolve B-bit. By using a DAC, the quantized value is then
subtracted from the original input signal to generate the quantization error. The
quantization error is amplified by an amplifier with gain 2B−1 . The resulting residue
signal is then feed into the next stage for further quantization on the next clock cycle.
The function of DAC, S/H, subtraction and the amplification can be combined into a
single stage called multiplying DAC (MDAC) [9], as shown in Fig. 3.1. Because each
stage has sample and hold function, each stage works concurrently to achieve high
throughput.
Fig. 3.3 and Fig. 3.2 show the circuit level implementations of the S/H and MDAC
building blocks. Notice that the main building elements in each of these blocks are
amplifiers or OTAs, therefore, how to design a good amplifier/OTA become a key
issue for any pipeline ADC design projects. Designing a high quality OTA is never
an easy task, the performance of an ADC is mainly affected by these analog building
blocks. As we will see later, the main focus of this thesis is to design these OTAs
based on systematic design procedure and also decrease the designing times.
34
(a) Single Ended S/H
(b) Fully Differential S/H
Figure 3.2: S/H Circuits
Figure 3.3: Multiplying DAC (MDAC)
35
3.2
ADC Design Specifications
3.2.1
How to Choose the Value of Capacitors
The value of the capacitors used in the MDAC and the S/H circuit are determined
by:
1. Capacitor matching issue.
2. The errors created by switches in the network.
3. Noise consideration
4. Switch-capacitor common-mode feedback and other parasitic capacitance.
Because we can use various circuit techniques (bottom plate sampling, bootstrap) to
reduce the error caused by the non-ideal switches, the noise consideration determine
the lower bound value of capacitors. After we estimate the capacitance values, we
can add matching and common-mode into design considerations to adjust the final
capacitance values that we are going to use in the actual design simulations.
Two main sources contribute the total noise are:
1. KT/C noise
2. Noise from the amplifier
We can use the equivalent model shown in Fig. 3.4 to determine the capacitance
values. During the sampling phase, φ1 and φ1a are high, φ2 are low.The KT/C noise
and the input signals are sampled on the capacitors.
36
Figure 3.4: MDAC Equivalent Model for Noise Calculation
The KT/C noise sampled on the capacitors can be expressed as:
2
Vout
≈
K ⋅T
, Camp is the total input capacitance of the amplifier.
Cs + Cf + Camp
(3.1)
During the hold phase, the input signals and the noise charges sampled on the capacitor will be transferred to the Cf , we can derive the output noise to be:
2
Vout
≈ KT ⋅
Cs + Cf + Camp KT 1
=
⋅ , β is the feedback factor
Cf2
Cf β
(3.2)
The input referred noise can be derived by dividing the total output noise with the
square of the gain:
37
2
Vin2
Cf
KT ⋅ (Cs + Cf + Camp )
V2
KT 1
= out
=
⋅ (
) =
2
2
G
Cf β Cf + Cs
(Cs + Cf )
(3.3)
The noise of the amplifier will be determined by the circuit topology and actual
implementation. The main noise source from the amplifier is generated by the drain
current noise: i2n ≈ 4 ⋅ KT ⋅ ( 32 ⋅ gm ). We can calculate the total noise power from the
amplifier by deriving the transfer function and doing the integration. We can derived
the input referred noise variance to be:
2
σ2 =
2
Cf
Vout
2
1
1
=
⋅
KT
⋅
⋅
(
)
G2 3
β CLtot Cf + Cs
where CLtot = CLoad + β ⋅ (Cs + Camp ), CLoad is the loading of later stages
(3.4)
If we assumed the KT/C noise and the noise in the amplifier are uncorrelated, we
can found the total input referred noise to be:
2
σtotal,in
⎡
2⎤
⎥
⎢ KT ⋅ (Cs + Cf + Camp ) 2
Cf
1 1
⎥
⎢
+
⋅
F
⋅
KT
⋅
⋅
(
)
=2⋅⎢
⎥
2
3
β
C
C
+
C
⎥
⎢
(C
+
C
)
Ltot
s
f
s
f
⎦
⎣
where F is noise factor depend on different circuit topology
38
(3.5)
3.2.2
What Are the Specs?
Suppose we want to design a 10-bit ADC with 50MS/s. We can derive the
following design specs:
Accuracy: εwrost =
1 1
⋅
210 2
Settling time: τperiod =
(3.6a)
1
= 20ns Ô⇒ τhalf,period = 10ns
50M
(3.6b)
Dynamic Range: 10 × 6.02 + 1.76 ≈ 65dB
(3.6c)
Close Loop Gain: 2 for 1.5-bit stage
(3.6d)
Worst Case Vdd : 1.8 ± 10% ≈ 1.6 ∼ 1.98V
(3.6e)
Power: as low as possible
(3.6f)
From equation (3.6a) we can known that the total error budget for the entire ADC.
The static error of the amplifier is equal to
1
(DC Loop Gain)
=
1
T0.
For a 0.1% accuracy
in the first stage of the 10-bit ADC, we need loop gain T0 > 60dB. Usually, we will
make the loop gain larger to get more margins for other defects in the design. From
equation (3.6b) we know that the amplifier has less than 10ns to settle within the
desired ranges. Typically we want to settle the outputs to 18 LSB within
1
2
⋅ τperiod [8].
The close loop gain in equation (3.6d) is determine by the gain of each stage that
been used in the ADC. A large close loop gain is equivalent to the smaller feedback
39
factor, which means the loop gain must be large to achieve the desired static error.
Usually, we started the design by choosing an OTA topologies that have sufficient
gain and less noise [8]. In some circumstances such as high resolution ADC designs,
we may use some circuit techniques to compensate the finite gain errors [4, 7].
3.2.3
How to Choose Design Specifications for ADC
For a 10-bit resolution pipeline ADC, we can derive the input referred noise of
single stage as:
Cs = Cf = C, Camp =
Vn2in ,tot =
1
⋅ C, F = 6 :Two stage or folded cascode structures
2
165 KT
KT
KT
⋅
= 4.58 ⋅
≈6⋅
36 C
C
C
Vn2in ,ADC ≈
1
1
1
1
11 ⋅ KT
6 ⋅ KT 6 ⋅ KT
+
⋅ (1 + 2 + 4 + 6 + 8 + ⋅ ⋅ ⋅⋅) ≈
2C
C
2
2
2
2
C
(3.7)
(3.8)
(3.9)
We choose the input referred noise to be a fraction of one LSB, in other words, we
don’t want the noise to degrade the SNDR of the ADC, here we choose 61 LSB to be
the design value. With full scale voltage VF S at the output to be equaled to 2 volts,
√
10
we can calculate one LSB is equal to VLSB = 2/2 ≈ 1.953mV . σin = Vn2in ,ADC =
1
6 LSB
≈ 325µV . By using
11⋅KT
C
= 325µV , we found that C ≈ 0.5pF . We can adjust
the C value based on the matching and common-mode feedback considerations, we
have to derive CLoad value from the worst case loading during the circuit operations.
Once we decided the C and the Cload values, we can use them in the OTA design
process.
40
CHAPTER 4
OTA DESIGN USING GM /ID METHOD
In this chapter, we would like to introduce the basic design flow for the OTA used in
pipeline ADC. First, detail design considerations of two stage miller OTA structure
will be discussed. In the second part, we will transfer these design ideas into Matlab
codes using gm /Id method introduced in the Chapter 2. We will use the circuit
simulator to simulate the circuit based on Matlab simulation outputs and compare
their simulation results.
4.1
OTA Design Considerations
4.1.1
Why Using Multi-Stage Amplifier?
A single stage amplifier have direct trade-off between swing and gain. A single
stage amplifier can be simplified with two current sources as shown in The Fig. 4.1 [5].
The more Vod we put across the current source, the more gain we get (higher output
impedance). However, higher Vod will reduce the effective swing and may degrade the
dynamic range.
41
Figure 4.1: Single Stage Amplifier
4.1.2
Design Two-Stage Amplifier
Two-stage amplifier can decouple the direct trade-off between gain and swing.
However, two-stage amplifier also have more poles associate with it so the stability
of the amplifier is crucial. Figure. 4.2 shown a two-stage configuration, the first stage
use telescopic structure to get more gain, the second stage use simple common source
differential pair to increase the output swing. Therefore, the two stage structure can
have high gain and high output ranges. With the telescopic structure, the gain is
roughly equal to (gm ro )3 . With 1.8V supply voltage, the common output swing can
be as large as 2Vp−p (differential).
42
Figure 4.2: Two Stage OTA
4.1.3
Simple Two-Stage Amplifier Model
We can use simple two-stage amplifier shown in Fig. 4.3 [5] [4] to analyze the
stability issue. As shown in Fig. 4.3, we can use simple R and C to express total
resistance and capacitance at the output of each stage. From the simple R,C elements
shown at the output, we know that there are at least two poles in this simple twostage model, therefore, at least 180 degrees phase shift. If the two-stage amplifier
used in a loop configuration,the phase shift of 180 degrees from these two poles is
theoretically stable, but in reality, any tiny parasitic capacitance in the loop could
cause the phase shift to be larger than 180 degrees.
43
Figure 4.3: Simple Model for Two-Stage Amplifier
4.1.4
Simplified AC Model using Capacitive Feedback
By adding two capacitors to the circuit shown in Fig. 4.3, we can derive simplified
model (Fig. 4.4) with feedback network for two-stage amplifier in Fig. 4.2. Equations
(4.1a) and (4.1b) are equivalent output resistance at outputs. The β in equation
(4.1c) is the feedback factor. The total equivalent output capacitance CLtot at output
of second stage is shown in (4.1d), total equivalent output capacitance at first stage
is C1 . The equivalent input capacitance at the gate of the first stage is Cx . Notice
that the feedback factor β is not just a function of Cs and Cf , is is also a function
of Cx . The Cgg values of input transistors will have large impact on the value of Cx ,
therefore, proper sizing the input transistor is crucial get the desired β value.
44
R1 ≈ (gm3 ⋅ ro3 ⋅ ro4 ) ∥ (gm2 ⋅ ro2 ⋅ ro1 )
(4.1a)
R2 ≈ ro5 ∥ ro6
(4.1b)
β≈
Cf
Cf + Cs + Cx
(4.1c)
CLtot ≈ CL + (1 − β) ⋅ Cf + Cdb5 + Cdb6
Figure 4.4: AC Model using Capacitive Feedback
45
(4.1d)
4.1.5
Loop Gain for Two-Stage Amplifier
By using the return ratio theory in reference [10], we can derive loop transfer
function of the circuit (Fig. 4.4) in equation (4.2). The loop transfer functions T (s)
consists of feedback factor and the transfer functions of each stage a1 (s) ⋅ a2 (s) = a(s).
Notice that the resistance and capacitance at the output of each stage create two
poles in the loop transfer function, therefore, the circuit is potentially unstable. If
ωp1 and ωp2 are close to each other we will have small phase margin (Fig. 4.5). In
order to make sure the circuit stable and obtain more phase margin, we could make
the transfer function smaller. However, the gain accuracy requirement may require
certain amount of T (s) value. The other simple solution is narrowbanding which
makes the loop behave like first order system [10] [5]. Narrowbanding means we push
either ωp1 or ωp2 happen at lower frequency to even lower frequency. Figure . 4.6
shown that by introducing the dominant pole in the system makes ωp2 to be much
larger than ωp1 . The phase margin of two-stage amplifier with extra dominant pole
is determine by the ωp /ωc ratio, where ωp is the pole at the higher frequency and ωc
is the unit gain frequency of loop transfer function. The phase margin in Fig. 4.6 is
approximately equal to ωp2 /ωc .
T (s) = β ⋅
p1 = −
gm1 R1 ⋅ gm5 R2
(1 − ps1 ) ⋅ (1 − ps2 )
1
1
, p2 = −
R1 C1
R2 CLtot
46
= β ⋅ a1 (s)a2 (s) = β ⋅ a(s)
(4.2a)
(4.2b)
Figure 4.5: Bode Plots of Two-Stage Amplifier
[4]
Figure 4.6: Bode Plots of Two-Stage Amplifier After Narrowbanding
[4] [5]
47
By introducing dominant pole to the system we can make the circuit stable. In
reality, making one of the poles dominate will require large capacitance at the output
of the stage. Also, the unit gain frequency would be pretty low. From the circuit
designer’s stand point, both of them are undesirable. We can make our circuit stable
by purposely connect an additional capacitor between the input and output of the
second stage, this is called Miller compensation [10, 5, 6, 4, 11]. After adding the
Miller capacitor in the circuit (Fig. 4.7), two pole will split apart (pole splitting) and
the system can be treated as first order system. Due to the Miller capacitor, the total
capacitance (C1 ) at the output of the first stage is gaining larger, therefore, the pole
associate with it moves to the lower frequency. On the contrary, at high frequency,
the Miller capacitor look like a low impedance path between the input and output of
the second stage, as a result, the pole moves to higher frequency. Figure 4.8 shown
the result of adding Miller capacitor.
Figure 4.7: Miller Compensation
48
Figure 4.8: Pole Splitting
[10]
We can derive the transfer function of
vo
vx
and the result is shown in equation (4.1.5).
The result of transfer function is messy and complicated. In order to better analyzing
and designing the circuit, we can use dominant pole approximation to simplify the
results.
a(s) =
vo
vx
(4.3)
gm1 R1 ⋅ gm5 R2 ⋅ (1 − s gCm5c )
=
1 + s [(CLtot + Cc ) R2 + (C1 + Cc ) R1 + gm5 R1 R2 Cc ] + s2 R1 R2 (C1 CLtot + Cc CLtot + Cc C1 )
49
We can use dominant pole approximation and assume ∣ p2 ∣≫∣ p1 ∣, we can write denominator D(s) and simplified it as [4]:
D(s) = (1 −
s
1
1
s2
s
) ⋅ (1 − ) = 1 − s ( + ) +
p1
p2
p1 p2
p1 p2
≈ 1 − s(
1
s2
)+
p1
p1 p2
(4.4a)
(4.4b)
Compared coefficients in equation (4.4) with equation (4.1.5), we can find identify p1
and p2 . We can derive the following results [4]:
a(s) ≈ a0 ⋅
z=+
(1 − zs )
(1 − ps1 ) ⋅ (1 − ps2 )
gm5
Cc
(4.5a)
(4.5b)
p1 ≈ −
1
gm5 R2 R1 Cc
(4.5c)
p2 ≈ −
gm5
C1
C1 + CLtot + CLtot
Cc
(4.5d)
As expected, equation (4.5) shows that the circuit have a right half plane zero. Usually, connection between input and output will create zero in the circuit. Here, the
Miller compensation capacitor create a low impedance path between input and output at high frequency. The right half plane zero is problematic because it can reduce
the phase margin if occurs before the cross over frequency. [10, 5, 4]. As shown in
Fig. 4.9, the right half plane zero happens before the loop cross over frequency and
flatten the gain, therefore, causing the circuit to be unstable.
50
Figure 4.9: Typical Gain and Phase Marge with Right Half Plane Zero
[10]
We may want to push the right half plane zero way higher than the cross over frequency, but what can we do? We can derive loop cross over frequency (ωc ) as gain
(T0 ) times bandwidth (ωp1 ) [4]:
ωc ≈ ωp1 ⋅ T0 =
ωz =
β ⋅ gm1 R1 ⋅ gm5 R2
gm1
=β⋅
gm5 R2 R1 Cc
Cc
gm5
Cc
(4.6a)
(4.6b)
51
and we can derive the ratio between the right half plane zero and the loop cross over
frequency to be:
ωz 1 gm1
= ⋅
ωc β gm5
(4.7)
Since ωc is usually fixed and the gm1 is also fixed, the only thing we can play around is
the gm5 [6]! Besides, pushing right half plane zero beyond crossover frequency requires
gm5 > β ⋅ gm1 is sometimes undesirable or impossible [4].
There are two commonly seen methods to mitigate the right half plane issue
[6] [4]. The first one is to make the feedback path of Cc unilateral. One practical
realization is by adding source follower. However, using source follower the circuit
will consume more power and degrade the swing. The other way to create unilateral
path is to use cascode compensation. The drawbacks of cascode compensation is that
the circuit became third order system and is difficult to design. The second method
is to use nulling resistor as shown in Fig. 4.10. We can derive new transfer function :
a(s) ≈ a0 ⋅
1
− Rz )
1 − sCc ⋅ ( gm5
(1 − ps1 ) ⋅ (1 − ps2 ) ⋅ (1 − ps3 )
52
(4.8)
Figure 4.10: Miller Compensation and Nulling Resistor
From equation (4.8), we know that by adding the nulling resistor, the transfer function
now has three poles and a tuning knob to mitigate the zero. Fig. 4.11 shown the
movement of zero position as the nulling resistor changes. We can move zero to
infinity by making Rz = 1/gm5 . The nulling resistor can be realized using poly resistors
or triode region transistors [4] [5]. Some may suggest that we can set the nulling
resistor equal to cancel out the second pole. Theoretically the idea is good but not
piratical in real design. Due to process variation, the nulling resistance may not
cancel the desired pole and create the pole-zero doublet which will slow down the
circuit transient response [5] [4].
53
Figure 4.11: Movement Diagram with Varying Nulling Resistor
[10]
By using the Miller capacitor and the nulling resistor, we found that the loop
crossover frequency depends on the Cc and the non-dominant pole (high frequency)
is set by the CLtot [4]. We can summarized two design equations
ωc ≈ β ⋅
p2 ≈ −
gm1
Cc
(4.9a)
gm5
C1
C1 + CLtot + CLtot
Cc
(4.9b)
that used in the Matlab design script. Notice that unlike the single stage amplifier,
the increasing of the load capacitance will cause ωp2 move to lower frequency and
hence reduces the phase margin [4].
4.1.6
Swing
The output swing of the second stage shown in Fig. 4.2 is critical to many design
specs. Often time the circuit is noise limited, therefore, the circuit require large output
swing range. For the common mode differential pair output stage, the available swing
depends on both input and output common mode. That is, we can’t decouple the
54
input common mode from output swing. Generally, we would choose folded cascode
structure to avoid input common mode set the output swing. As shown in Fig. 4.12,
the out put swing is limited by the active load or the input device. We found that
[4]:
Vxx = Vin,cm − Vgs,in = Vic − (Vov + Vth )
(4.10a)
Vo,max = Vdd − Vminp
(4.10b)
Vo,min = Vxx − Vminn
(4.10c)
Assumed all devices operate in the edge of saturation region (long channel model),by
adjusting the overdrive voltage and the common mode range, we can get maximum
available output swing. In real life, we may not have the freedom to choose the
common mode level because it is determined by the previous stage circuits [4].
55
Figure 4.12: Output Swing of Second Stage
[4]
If both input and output common mode level are half of the supply voltage. By
assuming the output swing limited by Vminn , we found that the available output
differential peak to peak swing is around 4 ⋅ Vth shown in Fig. 4.13 [4].
56
Figure 4.13: Vic=Voc=Vdd/2
[4]
Because usually the OTA is used in some feedback configuration, the large signal
gain characteristic is what we really care about. By plotting the the large signal
gain versus the output differential range, we can found the available swing at the
output. Using AV 0 = ∆Vout /∆Vin we can plot Fig. 4.14. The plot shows that for a
given deviation at the input, how much deviation show on the output.
57
Figure 4.14: Low Frequency Gain and Large Signal Characteristic
[5]
We known from the early section, the transition between triode and saturation region
is gradual, not abrupt. So how can we find the exact output swing of the circuit?
We can plot the large signal characteristic and define output range as the full scale
swing (differential) that causes no more than 30% variation drop in the gain [4]. The
output range in Fig. 4.14 is roughly around 2V.
58
4.1.7
Settling Performance
The settling performance is about how long it take to get the right result out
of amplifier. For a switched capacitor OTA used in ADC, we care about two things:
what is the residue error you can tolerate and how much time the output take to
reach the final value. For a 10-bit ADC with 200Ms/s, the non-overlap clock period
is 5ns each and we have half clock period(2.5ns) for our circuit to settle. As shown
in Fig. 4.15, after putting in a step, the output will rise and settle. Because the step
is relatively broadband, applying input with a step and check the output response is
best way to approximate what really happen to the circuit [5].
Figure 4.15: Step Response
[5]
There are two types of settling errors, the static error and the dynamic error [5].
The static error is related to the finite gain of the amplifier and the mismatch of the
59
capacitors setting the feedback loop, no matter how long we wait, the static error is
always there. If we tie the amplifier with capacitors shown in Fig. 4.16, we can derive:
−c
Vo
=
, T0 = β ⋅ Av0
Vi 1 + β⋅A1 v0
(4.11a)
β≈
Cf
, feedback factor
Cf + Cs + Cx
(4.11b)
c=
Cs
, closed loop gain
Cf
(4.11c)
where the equation (4.11a) can be approximated as:
−c
Vo
1
=
)
≈ −c ⋅ (1 −
1
Vi 1 + β⋅Av0
β ⋅ Av0
(4.12)
From equation (4.12) we found that the loop gain T0 will change the closed loop gain
c and causing gain error. The input capacitance Cx will cause the feedback factor to
change. For a given error spec, if the feedback factor deviated from the ideal value
too much, we will need large open loop gain. For example, if we want error to be
smaller than 0.1% and the close loop gain c = −4 with Cs = 500f F , Cx = 500f F and
Cs = 2pF . The feedback factor β = 1/6, therefore, we need AV 0 grater than 6000 over
the required output range!
60
Figure 4.16: Closed Loop Amplifier
[5]
Dynamic errors are set by many dynamic effects such as: finite bandwidth, feedforward zero, non-dominant pole, doublets and slewing [5]. Figure. 4.17 shows a closed
loop amplifier with load capacitor. By using single time constant approximation, we
can find useful linear settling results.
61
Figure 4.17: Closed Loop Amplifier with Cload
[5]
From Fig. 4.17 we can derive:
C
1 − s ⋅ Gmf
Vo
= −c ⋅
C
+(1−β)⋅Cf
Vi
1 + s ⋅ load
(4.13)
β⋅Gm
Notice that because the feedforward created from the feedback loop, it will create
zero in settling response. If we apply input with a step Vi,step = Vstep /s, the output
step response is Vo,step (s) = −c ⋅ 1+s/z
1+s/p ⋅ Vstep /s. By taking inverse Laplace transform or
using initial and final value theorems, we can derive time domain response at the
output is [5]:
p
Vo,step (t) = −Vstep ⋅ c ⋅ [1 − (1 − ) ⋅ e−p⋅t ]
z
(4.14)
where −Vstep ⋅ c is the ideal response and 1 − p/z is the initial error caused by feedforward. If p/z < 0 then there is extra swing that we need to spend as shown in
Figure. 4.18.
62
Figure 4.18: p/z
[5]
For ∣ p/z ∣≪ 1, equation (4.14) can be rewritten as:
Vo,step (t) = −Vstep ⋅ c ⋅ [1 − e−t/τ ], τ = 1/p
(4.15)
we can derive relative settling error to be:
ε = e−t/τ
(4.16a)
ts
= −lnε
τ
(4.16b)
Equation (4.16b) is critical in the design process: if I have a fixed settling time ts ,
how many τ do I need to reach the settling error ε that I’m interest in. In other
words, I know how fast that the circuit is going to operate (ts ), I know what value
63
that I want to settle to (ε) then I can calculate the gain bandwidth that I need to hit
the design target. The typical number to remember is 2.3τ per decade in the error
specs. Notice that the total equivalent output capacitance (Clef f ) on the output of
Fig. 4.16 is usually set by how much noise we can tolerate in the circuit. Therefore,
we can find the required gm value from equation (4.16b) [5].
If ∣ p/z ∣ is not negligible, equation (4.14) can be rearranged as:
p
Vo,step (t) ≈ −Vstep ⋅ c ⋅ [1 − (1 − ) ⋅ e−t/τ ], τ = 1/p
z
(4.17)
and we can derive relative settling error to be:
p
ε = (1 − ) ⋅ e−t/τ
z
(4.18a)
ts
ε
= −ln (
)
τ
1 + β ⋅ Cf /Clef f
(4.18b)
Notice that from equation (4.18b), we can decrease the feedforward by decrease Cf or
increase Cload . We know that to compensate the extra swing shown in Figure. 4.18,
the circuit needs longer times to settle. However, the extra time that we need to
spend is less than 1τ . Therefore, for dynamic error budget, we can calculate the
design value by using 2.3τ per decade rule plus some margin (Appendix.B, line 13).
The non-dominant pole in the circuit will impact the settling response. The
non-dominant poles can be found in cascode, gain boosting and multistage amplifiers.
Here we focus on the non-dominant poles in the multistage amplifier. The equation
(4.9) can be used to calculate the ratio of crossover frequency and non-dominant pole
frequency. We can define
64
ωp2 = K ⋅ ωc
(4.19)
If K is smaller than 1, then both the phase margin and bandwidth of the loop are
small. In order to lower the dynamic error settling time, we need certain amount of
bandwidths and phase margin. Fig. 4.19 shows that the optimum value of K depends
on the required εdynamic (accuracy) [5] [4]. Generally, we don’t want the K to be lower
than 2.
Figure 4.19: K value vs. ε
[5]
The phase margin can be defined as [4]:
65
P M ≅ tan−1 (
ωp2
)
ωc
(4.20)
As shown in Fig. 4.20, if the phase margin is too low, in other words,
ωp2
ωc
is too small,
the overall output response will have ripples and peaking on it. Therefore, it will take
more time to settle within the desired accuracy. In the multistage design example,
the calculation of the K value can be found in [4].
Figure 4.20: PM vs.
[10]
4.1.8
ωp2
ωc
Noise
Fig. 4.21 shows the simplified equivalent circuit of two stage OTA used in noise
calculation. The total integrated noise of the circuit shown in Fig. 4.21 is [12]:
66
ωp2
ωc
PM
1
2
3
4
5
45○
63○
72○
76○
79○
Table 4.1: ωp2 /ωc vs. P haseM argin
[4]
γp gm4
γp gm6
KT
1 KT
⋅
⋅ γn ⋅ (1 +
⋅
)+
⋅ [1 + γn ⋅ (1 +
⋅
)]
β Cc
γn gm1
CLtot
γn gm5
(4.21a)
γp V1 ∗
γp V5 ∗
1 KT
KT
≈ ⋅
⋅ γn ⋅ (1 +
⋅
)+
⋅ [1 + γn ⋅ (1 +
⋅
)]
β Cc
γn V4 ∗
CLtot
γn V6 ∗
(4.21b)
Vo2 ≈
From equation (4.21) we found that in order to reduce the total integrated noise,
we want to choose larger V ∗ for the loading device. However, the desired swing
requirement may force us to use lower V ∗ value. We also found that the larger the
Cc and CLtot , the smaller the total integrated noise. It seems attractive to use larger
capacitors to lower down the total noise. However, there are many limitations for
integrated capacitors. Also, to drive larger capacitance means the circuit will consume
more power and the transistor is bigger and slower(parasitics, transit frequency and
etc). An integrated circuit usually face the trade-off between the design simulation
(may or may not be real) and the actual realization (practical stand point).
67
Figure 4.21: Circuit for total integrated noise
[4]
4.1.9
Dynamic Range
The available output swing of the second stage in OTA will determine the dynamic range of the circuit. The dynamic range at the output can be calculated using:
DR =
2
Psignal,max 0.5 ⋅ Vod,peak
=
Pnoise
Vod2
(4.22)
The dynamic range is simply the power of the signal at the output divide by the power
of the noise at the output. The available swing of the common source differential pair
used in the second stage is shown in Fig. 4.22. We can derive:
68
Vo,peak ≤
1
(VDD − VodP − VodN − VodN )
2
Vod,peak ≤ (VDD − VodP − VodN − VodN )
Vod,peak ≤ (VDD −
2
2
2
−
−
)
(gm /Id )P (gm /Id )N (gm /Id )N
Vod,peak ≤ (VDD − VP ∗ − VN ∗ − VN ∗ )
(4.23a)
(4.23b)
(4.23c)
(4.23d)
For worst case corner, the supply voltage VDD =1.6V and the Vod,peak =1V, the total
budget for all three V ∗ would be 0.6V. If we assumed PMOS and NMOS using same
V ∗ then each V ∗ is less than or equal to 200mV. In other words, the gm /Id for
NMOS and PMOS should be ≥10. The above derivation are used during the Matlab
simulation setup. In order to lower the noise on the output, the V* of the load device
should be larger than the V ∗ of the gain device. However, using larger V ∗ will reduce
the effective swings at the output. Therefore, the designer must choose these ratio or
parameters carefully.
69
Figure 4.22: Dynamic Range
[4]
4.2
OTA Design Example
4.2.1
Divide and Conquer Design Flow
After we know the design considerations in the previous section, we can start
designing an OTA and keep those design equations in mind. Fig. 4.23 shows an two
stage OTA used in the 10-bit pipeline ADC. As we can see from the Fig. 4.23, we
need to choose sixteen channel lengths and widths plus the compensation capacitor
value and the lead resistance value. Obviously, if we just put this circuit in the
simulator without any initial calculation, it would be time consuming and painful
for any designers to finish it on time. We could spend a lot of time on this and the
70
design still don’t meet the specs. It is impossible to find a close form solution for
such complex circuit design problem, therefore the design must be iterated several
times[4]. We can use the basic characterization circuit introduced in Chaper 2 and
plots similar charts shown in Appendix A to do our iteration. Instead of using human
brain and paper pencil to iterate this problem. We can use the Excel, Matlab or any
other software to iterate/design this circuit based on the gm /Id method introduced
before. We can use Matlab function and treat these characterization charts as lookup
table to help us iterate the circuit during the design process [5, 6, 4, 1, 3].
Figure 4.23: Two Stage OTA
71
Once we setup the tool for accessing the characterization charts, we need to
analyze the design problem. We need to define primary variables and secondary
variables. Primary variables are the tuning knobs for the design, any tiny changes
in these variables will cause circuit performance to changed significantly. Secondary
variables are those parameters which will not cause serious impact on the critical
design trade-offs [4]. There are many possible ways to analyze the design targets and
define primary variables. The general design flow for complex circuits such as an
OTA is shown in Fig. 4.24.
Figure 4.24: General Design flow for an OTA
[4]
72
We choose Cgg1 and Cgg2 as main design variables and left others as secondary variables. The iteration loop is shown in Fig. 4.25, the equivalent Matlab codes and
function can be found in the Appendix B and [4]. The main calling function has
been adopted and modified from reference [4]. In order to create a loop for the design iteration, several lookup functions has been developed at the early stage of the
design. The lookup functions and the Matlab design script are crucial in the loop
iteration process because entire design method is based on the pre-simulated charts
and the Matlab codes. Therefore, the correctness of the device characterization data
is very important, we can only verify this through circuit simulators. Notice that even
we extracted the wrong data during the device characterization process, the Matlab
function may still generate reasonable results.
73
Figure 4.25: Design Flow Used in the OTA Design
[4]
4.2.2
OTA Design Specs
The design specs for the OTA shown in Fig. 4.23 is based on 10-bit 50Ms/s
pipeline ADC. The clock period is 20ns, therefore, the settling time ts is half of the
clock period. The dynamic range requirement is 65dB. The supply voltage is 1.8V
and we want to use minimum power. The load capacitance, sampling and feedback
74
capacitance is determined by the noise requirement. The static error is set to be
1
8 LSB
and the dynamic error is set to be around
1
16 LSB.
Table 4.2: Target Specifications for OTA
Vdd
Cload
Av,cl
DR
ts
εstatic
εdynamic
Cs = Cf
Vod,p−p
Power
1.8V
2.5pF
1
65dB
≤ 10ns
244.14µV
125µV
0.5pF
2V
min
The design process started by choosing the channel length to meet the static error
requirement. We can choose gm ratios to be equal at the beginning of the design
process. For the secondary design parameter such as phase margin, we must choose
carefully. If we choose high phase margin(e.g 75), the gm5 , the total current consumption will be significantly larger than low phase margin design. However, if we choose
the phase margin to be lower than 60, we will see ripples in the output step response
and the OTA may not meet the error specs. After we determine the secondary design
variables, we need to set the primary variables: Cgg1 and Cgg5 . We may guess some
numbers and try to iterate the problem. Since using minimum current is our design
goal, one systematic way is to use loop function to find the lower current combinations
as shown in Fig. 4.26. The capacitance ratios in the current optimization plot may
not be the optimal choice, but it shows the tendency for the design problem. Usually,
we want the Cgg1 to be small because we want it’s impact on feedback factor to be
smaller.
75
Figure 4.26: Current Optimization Plot
4.2.3
Simulation Results
The circuit simulations results are summarized in Table.4.3. Device parameters
are listed in Table.4.4, the discrepancies between the Matlab simulation results and
the circuits simulator results are mainly caused by the assumptions made during the
device characterizations. We can see that the circuit simulation basically meet all the
76
design specifications. To make the design more robust against processing variations,
all we have to do is to change the design parameters in the Matlab scripts to get more
margins. After we adjust the design parameters to obtain margins, the next step is to
apply and refine the biasing network. We may choose some high swing and constant
gm biasing networks. After we finished the biasing network design, the next step is
to implement the common mode feedback network and refine the device fingers and
multipliers. The last step is to check the design using different processing corners and
adjust the design.
Table 4.3: Spectre Simulation Results
fc
T0
PM
ts
εstatic
DR
Vod,p−p
Power
203M Hz
88.5dB
65.73
6.4ns
∼ 230µV
65.725dB
∼ 2V
4.9mA
77
Table 4.4: Compare Matlab and Spectre Simulation Results
m1 (knob)
Cgg
Cdd
gm
ft
gm /Id
Id
Id /W
W
Matlab
17f
9.2872f
603.15µ
5.6467GHz
10.8228
55.73µA
10.708
5.2045µm
m3
Simulation
17.033f
2.012f
579µ
Matlab
Simulation
Matlab
Simulation
14.551f
716.24µ
3.3f
704.966µ
58.206f
716.24µ
16.88f
700.94µ
10.432
55.5µA
10.673
5.2µm
12.8521
55.73µA
6.3047
8.8394µm
12.7
55.5µA
6.278
8.84µm
12.8521
55.73µA
1.0901
51.126µm
12.63
55.5µA
1.086
51.1µm
m4
Cgg
Cdd
gm
ft
gm /Id
Id
Id /W
W
m2
m5 (knob)
Matlab
Simulation
33.789f
545.708µ
8.7f
526.264µ
9.792
55.73µA
2.1509
25.91µm
9.482
55.5µA
2.124
25.9µm
Matlab
151.48f
47.991f
22.9m
24.017GHz
9.5269
2.4mA
29.3545
81.738µm
78
m6
Simulation
151.389f
29.959f
22.5789m
Matlab
Simulation
215f
18.291m
138.732f
18.178m
9.407
2.4mA
29.375
81.7µm
7.6215
2.4mA
5.664
423.62µm
7.574
2.4mA
5.674
423µm
Figure 4.27: Input Step and Output vs. Time
Figure 4.28: Settling Error vs. Time
79
(a) Loop Phase
(b) Loop Gain
Figure 4.29: Loop Simulation Results
(a) Large Signal Output Range
(b) Normalized Output Range
Figure 4.30: Output Swing Results
80
(a) Noise vs. Frequency
(b) Total Integrated Noise
Figure 4.31: Noise Simulation Results
81
CHAPTER 5
CONCLUSION
A design methodology based on the gm /Id characterization was presented in this
thesis. The proposed methodology was validated by the design of an two-stage OTA.
The results showed excellent matching between the Matlab synthesis results and the
circuit simulator results. The synthesis tool can reduce the re-design and optimization
times of the critical analog building blocks, it can also be used to synthesis the design
targets based on different processing corners. Designing times of complex analog
circuits such as pipeline ADC can be significantly reduced because the synthesis tool
can speed up the redesigning process. By changing the device characterization data
and properly modify the design script, the designer could migrate analog circuits to
different processing technologies in a short time. Last but not least, the synthesis
tool could be used for educational purpose by adding more circuit configurations and
more processing technologies. Instead of directly using circuit simulators to design the
circuits and get get frustrated, students can quickly learn the circuit design trade-offs
by using the synthesis scripts in the Matlab.
82
APPENDIX A
T echnology Characterization Charts f or T SM C 0.18µm P rocess
Figure A.1: NMOS Transit Frequency
83
Figure A.2: PMOS Transit Frequency
84
Figure A.3: NMOS Intrinsic Gain
Figure A.4: PMOS Intrinsic Gain
85
Figure A.5: NMOS Composite FoM
Figure A.6: PMOS Composite FoM
86
Figure A.7: NMOS Current Density
Figure A.8: PMOS Current Density
87
APPENDIX B
M ain Design Script.m
1
2
3
4
5
6
7
% design script.m
% tech parameters
tech.pcgd w = 0.657e-15; %
tech.ncgd w = 0.491e-15; %
tech.ncdb = 0.488;
tech.pcdb = 0.596;
tech.mun mup = 265/103; %
8
9
10
11
12
13
14
15
% specifications
spec.dr = 65;
% 65dB SNR
spec.ts = 10e-9; % 10ns
spec.es = 2.4414e-004 % error, static
spec.ed = 0.0125e-2 % error, dynamic, 8.9872tao, 1/8 LSB
spec.g = 1; % close loop gain
spec.vodpp = 2; % Vodp-p swing
16
17
18
19
20
21
22
23
24
25
26
% design choices
% noise
choices.gm6 gm5 =
choices.gm4 gm1 =
choices.gm3 gm2 =
choices.gm2 gm1 =
choices.gm3 gm4 =
choices.gm7 gm4 =
choices.gm8 gm5 =
160/200;
190/210;
160/160;
190/160;
210/160;
210/170;
160/170;
27
28
29
30
31
choices.cs = .5e-12;
88
32
33
34
choices.cf = choices.cs;
choices.cl = 2.5e-12;
choices.cgg1 = 0.01*(choices.cf+choices.cs);
35
36
37
38
choices.pm = 60;
choices.vodntot = (0.5*(spec.vodpp/2)ˆ2)/(10ˆ(spec.dr/10));
choices.fc = -(log(spec.ed)/(2*pi*0.5*spec.ts));
39
40
41
42
43
% dc gain requirement
beta guess = choices.cf/(choices.cf+choices.cs+choices.cgg1);
a0 = 1/spec.es/beta guess;
44
45
46
47
% pick L to achieve the computed value of gm gds for all devices (using
% intrinsic gain charts)
48
49
50
51
52
choices.L1
choices.L2
choices.L3
choices.L4
=
=
=
=
0.45;
0.5;
0.5;
0.5;
53
54
55
choices.L5 = 0.20;
choices.L6 = 0.35;
56
57
58
choices.L7 = 0.45;
choices.L8 = 0.25;
59
60
61
62
63
64
% primary optimization variables
cgg1 cs plus cf = 0.017;
cgg5 cltot = .055;
65
66
67
68
% compute required current for given design choices
[itotal, beta, cc, c1, c2, m1, m2, m3, m4, m5, m6, m7, m8] =
two stage miller(cgg1 cs plus cf, cgg5 cltot, choices, tech)
89
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91