VLSI Technology Overview
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VLSI Technology Overview Jeff Davis ECE6130 Reading (IEDM 2002 Paper plus Begin Chapter 3) Outline • • • • • • Introduction/Motivation Physical Technology Trends Clock Frequency and Power Trends Intel’s 90nm Logic Process Future Opportunities Questions Moore’s Law 10000 Number of Transistors (Millions) 1000 1 billion transistors @ 2008 100 Pentium 4 Pentium II 10 1 486 DX 1 million transistors @ 1989 286 Pentium III Pentium 386 0.1 8086 0.01 8080 4004 8008 0.001 1965 1970 1975 1980 1985 1990 1995 2000 2005 2010 Year Number of transistors doubles every 18 months!! 2015 Cost-per-function • Historically 25% reduction every year. 1971to 2004 --- approximately 4 orders of magnitude decrease in cost in cost-per-function. Question where does this come from? Smaller Transistor size reduces the Cost-Per-Function! 1.58 x increase in transistors per die ?=? 38% reduction in cost? ITRS Future Trends/Projections (public.itrs.net) • FYI: Intel recently announced that they will reach 1 billion transistors by 2007 with 65nm technology # of transistors per chip (M/chip) •ITRS partially uses historical trends to PROJECT the FUTURE of the Semiconductor Industry 10000 1000 100 10 1 1995 2000 2005 2010 Year Gigascale Integration (GSI) = 1 billion transistors per chip 2015 Technology Generation Definition Traditionally this has been every three years (1994 Roadmap) (Intel has new technology generation every two years) Mark Bohr, Intel Fellow, 2002 Press Release www.intel.com Intel on Schedule? “The company has attained yields suitable for volume production of 90nm-based processors at Fab D1C, according to Burns. Incorporating CDO (carbon-doped oxide, a low-k dielectric material) technology, seven copper interconnect layers and flip chip packaging, the processors’ performance was outstanding, he added. Fabs 11X is slated to begin volume production next quarter and Fab 24 will start wafer input in 2004. Further, Intel has begun 65nm test production at its Fab D1D and Fabs 24 and 12C will follow in 2005. When Intel enters 32 and 22nm processing in 2009 and 2011, respectively, the transistors will be smaller than a chromosome, Burns noted. ” DigiTimes (Sept. 22, 2003) Zeroth Level MOSFET Model Parallel Plate Charge Approximation electron mobility Cox Definition <v>=mE Q = CV Moving all charge out of Channel Q<v>/L = I Cox = eox/tox Lateral Electric Field Approx E = V/L Current Expression Gate Stack Capacitance C = CoxWL Rough average carrier velocity IDS= C(VGS-VT)<v>/L <v>=m(VDS/L) IDS= m Cox (W/L)(VGS-VT)VDS kn’ = process transconductance = m Cox bn= device transconductance = (W/L) kn’ VLSI designer does not control Zeroth Order nFET Model Drain Drain IDS Gate = Normally open switch -- “assert high” switch (i.e. VG = high then switch is “on” ) Rn= VDS/IDS= 1/[mnCox (W/L)n(VGS-VTn)] Source Source Zeroth Order pFET Model Drain Drain Gate Normally closed switch -- “assert low” switch (i.e. VG = low then switch is “on” ) IDS = Rp= VDS/IDS= 1/[mpCox (W/L)p(VGS-|VTp|)] Source Source Zeroth Level MOSFET Model Drain IDS IDS Drive Current when VGS=VDS=VDD VGS=VDD Gate VT <VGS<VDD Source Isaturation Not include: † VDS Vdd VGS< VT 1 = bn (VGS - VTn )(VDS ) VDS=VGS -Vt 2 1) Channel Length Modulation 2) Mobility degradation 3) Drain Induced Barrier Lowering (DIBL) 4) etc… Drive Current Metric Gate Length Vdd tox Source n+ L Channel Length n+ Drain p Idrive m n e oe r W m n e oe r W 2 = (Vdd - VTn ) ª (Vdd )2 2 tox L 2 tox L Constant-Field Scaling MOSFET device parameters Scaling factor (s>1) Gate Oxide Thickness (tox) 1/s Channel Length (L) 1/s Transistor Width (W) 1/s Junction Depth (xj) 1/s Doping concentration (Na, Nd) s Voltage (V) 1/s I drive m e oe r W m e oe r W 2 2 = (Vdd - Vt ) ª (Vdd ) 2 tox L 2 tox L Constant-Field Scaling Device Behavior MOSFET device parameters Scaling factor (s>1) Electric Field (E) 1 Carrier Velocity (v = mE) 1 Depletion Layer Width 1/s Gate Capacitance (C=eA/tox) 1/s Inversion layer charge density (Qi) 1 Current (drift) 1/s Channel Resistance (R) 1 Constant-Field Scaling Circuit Behavior MOSFET device parameters Scaling factor (s>1) Circuit Delay Time(t ~ CV/I) 1/s Power Dissipation per circuit (~VI) 1/s2 Power-Delay Product per circuit (P x t) 1/s3 Circuit Density ( µ 1/A ) s2 Power Density (P/A) 1 Transistor Performance Metric CV I drive dVds I ds = C g dt t =t 1 dt = C g I ds t =0 Ú Vds =Vdd Ú dVds Vds =0 2 Vdd CoxWLVdd L t =C = ª2 I drive C m W (V - V ) 2 m (Vdd ) ox dd t 2L A Different View of CV/I? Rn= VDS/IDS= 1/[mnCox (W/L)n(VGS-VTn)] + - t = 2.3RnCGn CGn= CoxWL Cox WL L2 = 2.3 ª2 W m (Vdd ) Cox m (Vdd - Vt ) L Don’t forget the wires! IBM microprocessor micrograph Interconnections between transistors are stacked on top!! M4 M3 M2 M1 silicon wafer surface Wires Classification: Local and Global local wires = intra macrocell wiring global wires = inter macrocell wiring Impact Extra Wire Capacitance?? Cw CV I drive Cg Vdd CoxWLVdd + CwVdd t = C g + Cw = I ds C m W (V - V ) 2 ox dd t 2L Ê LC w ˆ L2 ˜˜ ª ÁÁ 2 +2 Cox mWVdd ¯ Ë m (Vdd ) ( ) Global Wire Performance Metric Rwire Wr Hr He r = Lwire Wr H r + † Cwire = - † t = RwireC wire = e re o r e r e o Wr 2 Lwire H r He He Lwire Transistor and Interconnect Performance Metrics Transistor only L2 2 m (Vdd ) Transistor plus local wire Global long wire 2 Ê LC w L Á2 +2 Á m (V ) Cox mWVdd dd Ë Smaller = Faster! ˆ ˜ ˜ ¯ er 2 Lwire H r He † Smaller = No Improvement! ….Or slower!! Minimum Feature Size Projections Minimum Lithographic Feature Size Projections Drawn and Effective Channel Length 200 180 2 Ê LC w L Á2 +2 Á m (V ) Cox mWVdd dd Ë 160 140 ˆ ˜ ˜ ¯ 120 100 80 DRAM 1/2 Pitch MPU Gate Length Project Drawn Channel Length (nm) Effective Channel Length (nm) 60 40 20 0 1999 2002 2005 2008 2011 2014 Year Minimum Feature Size Decreases 30% every technology generation! Intel is ahead! Mark Bohr, Intel Fellow, 2002 Press Release www.intel.com Equivalent Gate Oxide Thickness Projections Effective Oxide Thickness [nm] 3 Ê Ltox Cw L2 ÁÁ 2 +2 e ox mWVdd Ë m (Vdd ) 2.5 ˆ ˜˜ ¯ 2 No known solutions 1.5 1 Quantum Effects! 0.5 0 1999 2002 2005 2008 Year 2011 2014 Intel is ahead! Mark Bohr, Intel Fellow, 2002 Press Release www.intel.com Gate Leakage on the RISE! Intel Technology Journal Q3 1998 Thompson, Packan and Bohr Supply Voltage Scaling 2 Supply Voltage [Volts] 1.8 2 Ê LC w L Á2 +2 Á m (V ) Cox mWVdd dd Ë 1.6 1.4 ˆ ˜ ˜ ¯ 1.2 1 0.8 0.6 0.4 0.2 0 1999 2002 2005 2008 Year WHY SCALE THIS? 2011 2014 Intel? Mark Bohr, Intel Fellow, 2002 Press Release www.intel.com Drive Current per unit width (Idrive/W) (microA/micron) ITRS Drive Current per Transistor Width Stays constant! 2500 2000 Drive Current Projections (microA/micron) ITRS Projections 1500 1000 500 0 1999 2002 2005 2008 2011 2014 Year Idrive m e oe r 1 m e oe r 1 2 = (Vdd - Vt ) ª (Vdd )2 W 2 tox L 2 tox L Intel? Mark Bohr, Intel Fellow, 2002 Press Release www.intel.com Why? Mark Bohr, Intel Fellow, 2002 Press Release www.intel.com CV/I Metric Projections 1.2E-11 2 Ê LC w L Á2 +2 Á m (V ) Cox mWVdd dd Ë CV/I metric [secs] 1E-11 ˆ ˜ ˜ ¯ 8E-12 Transistor Only Transistor plus Local Interconnect ITRS Values 6E-12 4E-12 2E-12 0 1999 2002 2005 2008 Year Assume Lwire = 30F!! 2011 2014 Global RC Charging Time/ CV/I gate delay metric Global Interconnect Delay Trends for Lwire=1mm 160.00 140.00 Global Interconnect 1mm : W=F : Aluminum 120.00 e re o r 2 L wire 2 F 100.00 80.00 60.00 40.00 20.00 † 0.00 1999 2002 2005 2008 2011 2014 Year What are we going to do! Interconnects don’t scale! Global RC Charging Time/ (CV/I) gate delay metric Material Changes will help! 160.00 140.00 Global Interconnect 1mm : W=F: Aluminum Global Interconnect 1mm: W=F : Copper 120.00 100.00 Global Interconnect 1mm: W=F : Copper Low k dielectric 80.00 60.00 40.00 20.00 0.00 1999 2002 2005 2008 Year 2011 2014 Reverse-Scaling Methodology Global RC Charging Time/ CV/I gate delay metric 90.00 Global Interconnect 1mm : W=F : Copper 80.00 70.00 Global Interconnect 1mm : W=2F : Copper Global Interconnect 1mm : W=3F : Copper 60.00 50.00 3F 2F F 40.00 30.00 20.00 10.00 er 2 Lwire H r He 0.00 1999 2002 2005 2008 Year 2011 2014 † Reverse Scaling works --- but at a price!! DENSITY Repeater Insertion L L/k L/k L/k Global RC Charging Time/ CV/I gate delay metric 90.00 Global Interconnect: L= 1mm : W=F : Copper 80.00 70.00 Global Interconnects With Repeaters: L=1mm: W=F: Cu 60.00 50.00 40.00 30.00 20.00 10.00 0.00 1999 2002 2005 2008 Year 2011 2014 Current Solution: Metal Wire Stacks Number of Metal Levels 12 10 8 6 4 2 0 1999 2002 2005 2008 2011 2014 Year Silicon Transistors Outline • • • • • • Introduction/Motivation Physical Technology Trends Clock Frequency and Power Trends Intel’s 90nm Logic Process Future Opportunities Questions Trends in Clock Frequency Doubles every technology generation Intel Technology Journal Q3 1998 Thompson, Packan and Bohr What is driving Increase in Clock Frequency? Circuit Delay Time(t ~ CV/I) 1/s 1.42x performance increase every generation with device performance ???? 2.0x increase in clock frequency Where is extra performance coming from? Reduction in number gates in Critical Path Average # of gate delays per clock cycle 60 To maintain 2x increase in frequency 50 Intel 1) reduced number of gates in one clock period (more pipelined) 2) employing advance circuit techniques 40 30 20 Alpha 10 0 1985 1990 1995 2000 2005 Year *Vivek De and Shekhar Borkar (INTEL), "Technology and Design Challenges for Low Power and High Performance," 1999 International Symposium on Low Power Electronics and Design, San Diego, CA, Aug. 16-17 1999, pp. 163-168. *Paul Gronowski, et al (Compact Digital), "High Performance Microprocessor Design," IEEE Journal of Solid-State Circuits, Vol. 33, No. 5, May 1998, pp. 676-686. 2010 Trends in Power Dissipation ~ 1.8x increase per generation Intel Technology Journal Q3 1998 Thompson, Packan, and Bohr Dynamic vs. Static Power Trends Intel Technology Journal Q3 1998 Thompson, Packan, and Bohr Why is Static Power Increasing? Intel Technology Journal Q3 1998 Thompson and Bohr Why is Static Power Increasing? Intel Technology Journal Q3 1998 Thompson, Packan, and Bohr Outline • • • • • • Introduction/Motivation Physical Technology Trends Clock Frequency and Power Trends Intel’s 90nm Logic Process Future Opportunities Question Intel State of the Art • 90nm Technology with 50nm gate lengths • 1.2nm gate oxides • “Strained” silicon used to increase mobility Mark Bohr, Intel Fellow, 2002 Press Release www.intel.com Mark Bohr, Intel Fellow, 2002 Press Release www.intel.com After K, Rim, et al (IBM),”Mobility Enhancement in Strained Si NMOSFETs with Hf02 Gate Dielectrics,” 2002 Symposium on VLSI Technology Digest of Technical Papers, Kyoto, Japan, pp. 12-13. Mark Bohr, Intel Fellow, 2002 Press Release www.intel.com Mark Bohr, Intel Fellow, 2002 Press Release www.intel.com Mark Bohr, Intel Fellow, 2002 Press Release www.intel.com Mark Bohr, Intel Fellow, 2002 Press Release www.intel.com Outline • • • • • • Introduction/Motivation Physical Technology Trends Clock Frequency and Power Trends Intel’s 90nm Logic Process Future Opportunities Questions INTEL’s TRANSISTOR OF THE FUTURE!!!! THE TERAHERTZ TRANSISTOR!! AKA Fully-Depleted SOI Device! Kevin Teixeira, Online Intel Technological Background Report, “Intel’s Terahertz Transistor Architecture”, www.intel.com/research/silicon. Kevin Teixeira, Online Intel Technological Background Report, “Intel’s Terahertz Transistor Architecture”, www.intel.com/research/silicon. Other Choices??? James Hutchby, et al, “Extending the Road Beyond CMOS”, IEEE Circuits and Devices Magazine, March 2002, pp. 28-41. Exotic Choices?? James Hutchby, et al, “Extending the Road Beyond CMOS”, IEEE Circuits and Devices Magazine, March 2002, pp. 28-41. Outline • • • • • • Introduction/Motivation Physical Technology Trends Clock Frequency and Power Trends Intel’s 90nm Logic Process Future Opportunities Questions
