M74HC161
SYNCHRONOUS PRESETTABLE 4-BIT COUNTER
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■
■
■
■
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■
HIGH SPEED :
fMAX = 62 MHz (TYP.) at VCC = 6V
LOW POWER DISSIPATION:
ICC =4µA(MAX.) at TA=25°C
HIGH NOISE IMMUNITY:
VNIH = V NIL = 28 % VCC (MIN.)
SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 4mA (MIN)
BALANCED PROPAGATION DELAYS:
tPLH ≅ tPHL
WIDE OPERATING VOLTAGE RANGE:
VCC (OPR) = 2V to 6V
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 161
DESCRIPTION
The M74HC161 is an high speed CMOS
SYNCHRONOUS
4-BIT
BINARY
PRESETTABLE COUNTER fabricated with silicon
gate C2MOS technology.
The CLOCK input is active on the rising edge.
Both LOAD and CLEAR inputs are active LOW.
Presetting is synchronous on the rising edge of
the clock, the function is cleared asynchronously.
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DIP
PACKAGE
TUBE
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TSSOP
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ORDER CODES
DIP
SOP
TSSOP
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SOP
M74HC161B1R
M74HC161M1R
T&R
M74HC161RM13TR
M74HC161TTR
Two enable inputs (TE and PE) and CARRY
output are provided to enable easy cascading of
counters, which facilities easy implementation of
N-bit counters without using external gates.
All inputs are equipped with protection circuits
against static discharge and transient excess
voltage.
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PIN CONNECTION AND IEC LOGIC SYMBOLS
July 2001
1/12
M74HC161
INPUT AND OUTPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION
PIN No
SYMBOL
1
CLEAR
2
CLOCK
3, 4, 5, 6
7
10
9
14, 13, 12,
11
15
8
16
A, B, C, D
PE
TE
LOAD
Asynchronous Master
Reset
Clock Input (LOW to
HIGH, Edge-triggered)
Data Inputs
Count Enable Input
Count Enable Carry Input
Parallel Enable Input
QA to QD
Flip Flop Outputs
CARRY
GND
Vcc
CLEAR
LOAD
PE
TE
CLOCK
QA
QB
L
X
X
X
X
L
L
H
L
X
X
H
H
X
L
H
H
L
X
H
H
H
H
X
X
e
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LOGIC DIAGRAM
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This logic diagram has not be used to estimate propagation delays
2/12
bs
O
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X : Don’t Care
A, B, C, D : Logic level of data inputs
Carry : CARRY = TE·QA·QB·QC·QD
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OUTPUTS
B
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Terminal Count Output
Ground (0V)
Positive Supply Voltage
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TRUTH TABLE
INPUTS
NAME AND FUNCTION
FUNCTION
QC
QD
L
L
RESET TO "0"
C
D
PRESET DATA
NO CHANGE
NO COUNT
NO CHANGE
NO COUNT
COUNT UP
COUNT
NO CHANGE
NO COUNT
M74HC161
TIMING CHART
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ABSOLUTE MAXIMUM RATINGS
Symbol
VCC
P
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Supply Voltage
Parameter
Value
Unit
-0.5 to +7
V
VI
DC Input Voltage
-0.5 to VCC + 0.5
V
VO
DC Output Voltage
-0.5 to VCC + 0.5
± 20
mA
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V
IIK
DC Input Diode Current
IOK
DC Output Diode Current
± 20
mA
IO
DC Output Current
± 25
mA
ICC or IGND DC VCC or Ground Current
PD
Power Dissipation
Tstg
Storage Temperature
TL
Lead Temperature (10 sec)
± 50
mA
500(*)
mW
-65 to +150
°C
300
°C
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
(*) 500mW at 65 °C; derate to 300mW by 10mW/°C from 65°C to 85°C
3/12
M74HC161
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
VCC
Value
Supply Voltage
VI
Input Voltage
VO
Output Voltage
Top
Operating Temperature
Input Rise and Fall Time
tr, tf
Unit
2 to 6
V
0 to VCC
V
0 to VCC
V
-55 to 125
°C
VCC = 2.0V
0 to 1000
ns
VCC = 4.5V
0 to 500
ns
VCC = 6.0V
0 to 400
ns
)
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DC SPECIFICATIONS
Test Condition
Symbol
VIH
Parameter
Min.
2.0
4.5
6.0
2.0
4.5
6.0
Low Level Input
Voltage
VOH
TA = 25°C
VCC
(V)
High Level Input
Voltage
VIL
High Level Output
Voltage
1.5
3.15
4.2
IO=-20 µA
4.5
IO=-20 µA
6.0
ICC
4/12
ete
ol
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II
Pr
Input Leakage
Current
Quiescent Supply
Current
b
O
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-40 to 85°C
Max.
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Pr
Min.
Max.
1.5
3.15
4.2
0.5
1.35
1.8
-55 to 125°C
Min.
0.5
1.35
1.8
2.0
1.9
1.9
4.4
4.5
4.4
4.4
5.9
6.0
5.9
5.9
IO=-4.0 mA
4.18
4.31
4.13
4.10
IO=-5.2 mA
5.68
5.8
5.63
V
0.5
1.35
1.8
1.9
Unit
Max.
1.5
3.15
4.2
IO=-20 µA
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Low Level Output
Voltage
)-
2.0
4.5
Typ.
so
6.0
VOL
Value
V
V
5.60
2.0
IO=20 µA
0.0
0.1
0.1
0.1
4.5
IO=20 µA
0.0
0.1
0.1
0.1
6.0
IO=20 µA
0.0
0.1
0.1
0.1
4.5
IO=4.0 mA
0.17
0.26
0.33
0.40
6.0
IO=5.2 mA
0.18
0.26
0.33
0.40
6.0
VI = VCC or GND
± 0.1
±1
±1
µA
6.0
VI = VCC or GND
4
40
80
µA
V
M74HC161
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6ns)
Test Condition
Symbol
Parameter
tPLH tPHL Propagation Delay
Time
(CLOCK - Q)
tPLH tPHL Propagation Delay
Time
(CLOCK - CARRY)
tPLH tPHL Propagation Delay
Time
(TE - CARRY)
tPLH
Propagation Delay
Time
(CLEAR - Q)
tPHL
Propagation Delay
Time
(CLEAR - CARRY)
fMAX
Maximum Clock
Frequency
tW(H)
tW(L)
Minimum Pulse
Width (CLOCK)
tW(L)
Minimum Pulse
Width (CLEAR)
e
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ts
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ts
th
(LOAD, PE, TE)
Minimum Set-up
Time
(A, B, C, D)
Minimum Hold
Time
(A, B - CLOCK)
tREM
Minimum Removal
Time
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
Min.
Typ.
Max.
25
7
6
48
16
14
57
19
16
39
13
11
60
20
17
72
24
20
18
53
62
18
6
6
24
7
6
40
10
8
20
5
3
75
15
13
125
25
21
150
30
26
100
20
17
150
30
26
200
40
34
s
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6.2
31
37
18
4
3
-40 to 85°C
-55 to 125°C
Min.
Min.
Max.
95
19
16
155
31
26
190
38
32
125
25
21
190
38
32
250
50
43
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5
25
30
75
15
13
75
15
13
100
20
17
75
15
13
0
0
0
50
10
9
Max.
110
22
19
190
38
32
225
45
38
150
30
26
225
45
38
300
60
51
4.2
21
25
95
19
16
95
19
16
125
25
21
95
19
16
0
0
0
65
13
11
Unit
ns
ns
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Minimum Set-up
Time
TA = 25°C
VCC
(V)
tTLH tTHL Output Transition
Time
Value
ns
ns
ns
ns
MHz
110
22
19
110
22
19
150
30
26
110
22
19
0
0
0
75
15
13
ns
ns
ns
ns
ns
ns
5/12
M74HC161
CAPACITIVE CHARACTERISTICS
Test Condition
Symbol
Parameter
Value
TA = 25°C
VCC
(V)
Min.
Typ.
Max.
10
CIN
Input Capacitance
5.0
5
CPD
Power Dissipation
Capacitance (note
1)
5.0
50
-40 to 85°C
-55 to 125°C
Min.
Min.
Max.
10
Unit
Max.
10
pF
pF
1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC
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CL = 50pF or equivalent (includes jig and probe capacitance)
RT = ZOUT of pulse generator (typically 50Ω)
P
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WAVEFORM 1: PROPAGATION DELAY TIMES, CLOCK MINIMUM PULSE WIDTH
(f=1MHz; 50% duty cycle)
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M74HC161
WAVEFORM 2 : PROPAGATION DELAY TIMES,CLEAR MINIMUM PULSE WIDTH (CLEAR MODE)
(f=1MHz; 50% duty cycle)
)
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WAVEFORM 3 : SETUP AND HOLD TIMES (PRESET MODE) (f=1MHz; 50% duty cycle)
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M74HC161
WAVEFORM 4 : SETUP AND HOLD TIMES (COUNTENABLE MODE) (f=1MHz; 50% duty cycle)
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WAVEFORM 5 : PROPAGATION DELAY TIMES (CASCADE MODE) (f=1MHz; 50% duty cycle)
)
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M74HC161
Plastic DIP-16 (0.25) MECHANICAL DATA
mm.
inch
DIM.
MIN.
a1
0.51
B
0.77
TYP
MAX.
MIN.
TYP.
MAX.
0.020
1.65
0.030
0.065
b
0.5
0.020
b1
0.25
0.010
D
)
s
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ct
20
E
8.5
e
2.54
e3
17.78
u
d
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0.335
7.1
I
5.1
s
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c
1.27
e
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bs
O
)
3.3
Z
Pr
0.100
F
L
0.787
0.700
0.280
0.201
0.130
0.050
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P001C
9/12
M74HC161
SO-16 MECHANICAL DATA
mm.
DIM.
MIN.
TYP
A
inch
MAX.
MIN.
TYP.
a1
1.75
MAX.
0.1
0.068
0.2
a2
0.003
0.007
1.65
0.064
b
0.35
0.46
0.013
b1
0.19
0.25
0.007
C
0.5
0.018
)
s
(
ct
0.010
0.019
c1
45° (typ.)
D
9.8
10
0.385
E
5.8
6.2
0.228
e
1.27
e3
8.89
F
3.8
4.0
4.6
5.3
L
0.5
)
(s
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t
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so
b
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1.27
S
Pr
0.393
0.244
0.050
G
M
u
d
o
0.62
0.350
0.149
0.157
0.181
0.208
0.019
0.050
0.024
8° (max.)
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PO13H
10/12
M74HC161
TSSOP16 MECHANICAL DATA
mm.
inch
DIM.
MIN.
TYP
A
MAX.
MIN.
TYP.
MAX.
1.2
A1
0.05
A2
0.8
b
0.047
0.15
0.002
0.004
0.006
1.05
0.031
0.039
0.041
0.19
0.30
0.007
c
0.09
0.20
0.004
D
4.9
5
5.1
0.193
E
6.2
6.4
6.6
0.244
E1
4.3
4.4
4.48
1
e
bs
0.65 BSC
K
0°
L
0.45
let
o
s
b
0.60
s
(
t
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0.75
du
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P
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0.0089
0.197
0.201
0.252
0.260
0.173
0.176
0.0256 BSC
0°
8°
0.018
0.024
0.030
u
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P
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A
O
)
8°
0.012
t
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0.169
)
s
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A2
A1
b
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K
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E
D
E1
PIN 1 IDENTIFICATION
1
0080338D
11/12
M74HC161
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from
its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications
mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information
previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or
systems without express written approval of STMicroelectronics.
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