How to avoid Layout and
Assembly got’chas with
advanced packages
Parts and pitch get smaller. Pin counts get larger. Design cycles get shorter.
BGA, MicroBGA, QFN, DQFN, CSP packages are taking the design world by
storm. Learn how to avoid the most common trip-ups when designing with these
packages. Also learn how the various board finishes can impact the use of
advanced package components in a prototype world.
Presenter Bio:
Duane Benson is a 25-year technology
veteran and runs the marketing department
at Screaming Circuits, a quick-turn
prototype pcb assembly company.
Why are you all here?
 “Small” means something different now
 1” to 0.5” is no big deal
 1mm to 0.5mm is
Why is it such an issue now?
 Old days – TH first
 Now, just small packages because of volumes
What is advanced packaging

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0.5mm or smaller pitch BGA, uBGA, CSP, LGA
QFN
0402, 0201 and 01005 passives
A little RoHS, just because
Look close:
0201s and
01005s
BGA, uBGA, CSP,
LGA
BGA LAYOUT
 Lead vs. no lead
– Assembly has to follow the BGA
 Non-soldermask defined pads are preferred
– Better mechanical connection
BGA LAYOUT
 Non Solder Mask Defined land pad – side view
NSMD
SMD
MICRO BGA ROUTING
 Not enough room
 Don’t change pad size
or shape
VIA TYPES
 A little refresher
BGA VIA IN PAD
 Not a time to buy a board based on price
BGA VIA IN PAD
 Capillary action = bad
 Sucking solder through a straw much worse than
sipping cider through a straw
 Worse with lead
VIA IN PAD
 Open
 Ye haw!
BGA VIA IN PAD
 Bad, bad, bad example board
– Uneven board surface
– Giant via holes
– Low precision
BGA VIA NEAR PAD
BGA VIA NEAR PAD
 B: Via can still wick solder away
 B: Solder mask defined pads, not recommended
MASKED VIAS
 The intention was good, the workmanship was not
ALL-AROUND AWFUL
VIA NEAR PAD W/O MASK
 Post reflow
 Solder balls were sucked right off these two pads
BGA BOARD SURFACE
 HASL not really
appropriate for
uBGA and CSP
 Flat surface is very
important with super
small parts
BGA BOARD SURFACE
 Bumpy HASL surface is
not much of a problem
with large parts
 Can be a problem with
fine pitch and small
CSP or uBGA
PLUGGED VIA
 Flat (coplanar) surface is very important with the very
small parts
PLUGGED VIA
 Flat (coplanar) surface is very important with the very
small parts
PLUGGED VIA
 Flat (coplanar) surface is very important with the very
small parts
QFN
QFN Thermal pad
 Heat sink
– May require lots of vias
 Grounding
– Simple low-speed ground may not require any vias
– High speed & RF may require engineered via placement
QFN LAYOUT
 Solder paste stencil opening
– No big openings
Bad
Good
QFN FULL CENTER LAND
 Ideal if stencil is made correctly
 Little chance for tilt
QFN WRONG AND RIGHT
May cause even less stable
placement resulting in tilted
component
Reduces solder more evenly
over the entire land area
QFN COPPER PATTERNS
 Some parts require
Special copper
patterns
(From Freescale appnote)
QFN COPPER PATTERNS
 Don’t forget the stencil
pattern
 A full opening will almost
guarantee faulty
placement
 Make matching cutouts
at reduced size
(From Freescale appnote)
VIA IN PAD
 Via in pad
– Plug it and/or mask it, please
– Or, at least, make
it very, very tiny
 Capping the chip-side is better
than capping the bottom
– Reduce chance of outgassing
and voids
QFN SMALL CENTER LAND
 Signal vias may short to ground
 Part may tilt
 Vias not fully capped
QFN VIA IN PAD
MASKED VIAS IN PAD
 Solder mask
 Better than nothing
 May break open
PLUGGED VIAS IN PAD




Conductive fill
Thicker via wall and non-conductive fill
Plugs
Plated over
PLUGGED AND MASKED
 Reduced chance of break-through or outgassing
 Can contribute to
excess solder in
center pad
(simulated image)
BLORT…
A BETTER WAY
0402, 0201, 01005
VERY SMALL PASSIVES
 Tombstoning
– Some process related causes
– Some layout related causes
TOMBSTONING
 Possible layout causes:
– Inner layers
– Uneven traces
– Large components close by
Inner layer
Sinks heat
Wide trace
Sinks heat
SOLDERMASK
 Raised soldermask can create a well and lead to
tombstoning with tiny passives
 Can be cause by thick mask or SMD pads
MISCELLANEA
RoHS WETTING
 Can allow via in pad in some situations
– Lead-Free solder may not wick down
small via holes
 Can allow smaller pad sizes for greater
component density
RoHS – SORT OF
 When is a RoHS
passive, not RoHS?
ENIG & IMMERSION SILVER
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Black pad
Micro voids
Don’t touch
Don’t cap both via sides
on silver boards
 Keep dark, keep sealed
OSP
 Check for contamination
 Surface should be bright
and consistent
 Caused by poor surface
preparation at the fab house
 Caused by poor handling
 Caused by atmospheric
contamination
OSP
So long and thanks for all the lead