Agilent Measurement Forum 2010
Through Silicon Via (TSV) Equalizer
*Joohee Kim, *Eakhwan Song, *Jeonghyeon Cho, *Jun So Pak,
**Junho Lee, **Hyungdong Lee, **Kunwoo Park and *Joungho Kim
* Korea Advanced Institute of Science and Technology (KAIST)
** Hynix Semiconductor Inc.
2010. 6. 17.
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Contents

Introduction

Analysis of loss mechanism of a TSV

Proposed TSV Equalizer

Simulation-based Verification of the Equalization Performance of the
Proposed TSV Equalizer

Conclusion
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Through Silicon Via (TSV) in 3-dimensional Integrated Circuits
Stacked
Dies
Interposer
Package
PCB
[ 3-dimensional Integrated Circuits ]
Die
Interposer
Through Silicon Via
Package
 Through Silicon Via (TSV) is a vertical interconnection method
between chips in 3-dimensional integrated circuits.
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A Through Silicon Via Structure on Double-sided Silicon
Substrate
Underfill
Bump
Metal (M1,M2)
Inter-metal Dielectric
Insulation layer
Double-sided
Silicon Substrate
TSV
1111111111111
Cinsulator GSi sub
Inter-metal Dielectric
Underfill
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Bump
Cu
SiO2
Si
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Frequency
dependent term
Cinsulator GSi sub
Leakage current
Cu
SiO2
Si
Loss term
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Transmission coefficient (S21) [dB]
Frequency-dependent Loss of Through Silicon Via
0
-1
-2
-3
-4
Capacitive
region
Resistive
region
-5
-6
0.1
1
Frequency [GHz]
10 20
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High Speed Signal Performance Degradation caused by TSV
Ground
TSV
Signal
TSV
Cinsulator Cinsulator
Voltage (V)
0.25
0
-0.25
0
20
40
60
Time (ps)
80
100
Voltage (V)
0.25
-0.25
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The Eye is Closed!
We Need an Equalizer !
0
0
20
40
60
Time (ps)
80
100
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Scalable Equivalent Circuit Model of a TSV
Signal
TSV
CBump
Cinsulator
Cinsulator
LTSV
RTSV
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Cinsulator
Cinsulator
LTSV
CSi sub
GSi sub
Cinsulator
Cinsulator
Cinsulator
Cinsulator
Bump
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Ground
TSV
CBump
RTSV
Bump
Structural Parameters
TSV diameter
:d
TSV-to-TSV pitch : p
SiO2 thickness : t
Height
:h
Bump diameter : D
Equations
Cinsulator (d,h,t)
CSi sub (d,h,p,t)
CBump (p,D)
GSi sub (d,h,p,D)
RTSV (d,h)
LTSV (d,h,p)
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Scalable Equivalent Circuit Model of a TSV
Cinsulator (d,h,t)
CSi sub (d,h,p,t)
: SiO2 insulator capacitance
: Silicon substrate capacitance
Cinsulator 
2π  ε0 εr
L
b
ln ( )
a
 ( 2π  ε0  4 ) 
t
p
h
d
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h
d/ 2  t
ln (
)
d/ 2
b
a
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1 2π  ε0 εr

L
2 ln ( 2a )
b
2π  ε0 εr
1


h
2 ln ( p  d  2t )
(d/ 2 )
CSi _ sub 
t
b
a
h
d
Ref) Matthew N.O. Sadiku, Elements of Electromagnetics, 3th Edition
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Scalable Equivalent Circuit Model of a TSV
CBump (d,p,h)
RSi (d,p,h)
: Capacitance between Bumps
: Resistance of Silicon
Cbump 
ε0 ε r
D
 π(
) 10um
p-D
2
L
ζS
0.7  p  30um

p
10  (
 50um  d)  h
2
RSi _ sub 
p
p/2+d+50um
D
p
10um
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L
h
Ref) Matthew N.O. Sadiku, Elements of Electromagnetics, 3th Edition
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Scalable Equivalent Circuit Model of a TSV
RTSV (d,h)
LTSV (d,h,p,D)
: Resistance of TSV
: Inductance of TSV
RTSV  ρ
l
A
 ( 1.72e  8 ) 
μ0l
p
ln ( )
π
a
( 4π  e  7 )
p
p

 (h  ln (
)  ( 20um) ln (
))
π
d/ 2
D/ 2
LTSV 
h
d
d
π  (( )2  ( -δskin depth )2 )
2
2
δSkin depth
l
p
h
h l
a
d
d
D
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10 um
Ref) Matthew N.O. Sadiku, Elements of Electromagnetics, 3th Edition
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Insertion Loss of a TSV in Low Frequency Range
Signal TSV
Ground TSV
Cinsulator dominantly affects frequency
dependency of insertion loss of a TSV.
SiO2
Cinsulator
Cinsulator
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Si
Cu
Cinsulator
Cinsulator
Signal current
Leakage current
Transmission coefficient (S21) [dB]
Cu
0
-1
-2
-3
-4
Cinsulator
-5
-6
0.1
1
Frequency [GHz]
10 20
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Insertion Loss of a TSV in Mid Frequency Range
Ground TSV
CSi sub
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Signal current
Leakage current
CSi sub dominantly affects frequency
dependency of insertion loss of a TSV.
Transmission coefficient (S21) [dB]
Signal TSV
0
-1
-2
-3
-4
-5
-6
CSi sub
0.1
1
Frequency [GHz]
10 20
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Insertion Loss of a TSV in High Frequency Range
Signal TSV
CBump dominantly affects frequency
Ground TSV
CBump
CBump
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Signal current
Leakage current
Transmission coefficient (S21) [dB]
dependency of insertion loss of a TSV.
0
-1
-2
-3
-4
-5
-6
CBump
0.1
1
Frequency [GHz]
10 20
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Designed TSV Channel for Experimental Verification
 Designed TSV Channel with Single-ended Signal TSVs
Re-distribution Layer
(RDL)
Re-distribution layer (RDL)
Re-distribution layer (RDL)
for connecting TSVs
Signal TSV
Ground TSV
Bump
Through Silicon Via
(TSV)
Re-distribution Layer
(RDL)
Top die
Bottom die
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Measurement Environment for Experimental Verification
Probe
Station
Vector
Network
Analyzer
(VNA)

Vector Network analyzer (VNA)
 Agilent Technologies / N2530A
(300kHz-20GHz)

Cascade Probe
 I40-GS/SG 100um pitch
High
speed
cable

High Speed Cables
 Micro-coax
(Frequency range : 0.05-26.5GHz)
Cascade
probe
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(Insertion loss : 1.57dB/m at 26.5GHz)
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Verification of the Analyzed TSV loss by Measurement
S21 magnitude (dB)
0
-0.5
Cinsulator
-1
CSi sub
-1.5
-2
CBump
-2.5
-3
-3.5
0.1
Proposed model
Measurement
1
10
20
Frequency (GHz)
 TSV has capacitive characteristic which brings frequency dependency to
loss of a TSV.
 Insulator capacitance, Cinsulator, dominantly affects the overall frequency
dependent loss of a TSV.
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The Proposed TSV Equalizer using an Ohmic Contact
Ohmic contact
(Al/n+ type)
Signal
TSV
n+ high
doped Silicon
Ground
TSV
n-type
Silicon
Substrate
Bump
Bump
 We intentionally made leakage by using an Ohmic contact
resulting in DC attenuation between signal and ground TSV.
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Intended DC attenuation of the Proposed TSV Equalizer
Rcontact
Rcontact
Ohmic contact brings
DC attenuation!
Ground TSV
Rcontact
Rcontact
Transmission coefficient (S21) [dB]
Signal TSV
0
-1
-2
Before Equalization
-3
-4
-5
After Equalization
-6
0.1
1
Frequency [GHz]
10 20
Signal current
Intended Leakage current
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Process of the Proposed TSV Equalizer
Silicon Doping
The Proposed TSV Equalizer
Lithography
Ohmic contact
Via Etch
Insulator Deposition
Metal Plating
Chemical Mechanical
Polishing (CMP)
Signal
TSV
Silicon
Substrate
Ground
TSV
Metal Patterning
Back-grinding
Backside Silicon doping
SiliconMetal
Substrate
Back-side Metal Patterning
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Simulation Item for Verification of the TSV Equalizer
Performance
TSV dimension
Ground
Signal
Ground
TSV diameter
75 um
TSV height
90 um
TSV-to-TSV pitch
150 um
SiO2 thickness
0.1 um
Number of stacked dies
8
Ohmic Contact information
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Junction depth
1 um
Resistivity of
Junction
0.032 Ω·cm
Resistivity of
Silicon
10 Ω·cm
Contact Width
22.5 um
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Transmission coefficient (S21) [dB]
Frequency Domain Simulation-based Verification of the TSV
Equalizer Performance
0
Insertion loss of 8 TSVs
without TSV equalizer
-2
4.8 dB
-3.8 dB
-4
- 4.5
1 dB
-6
0.7dB
Flattened from DC to 10GHz
(Nyquist frequency of 20Gbps)
Insertion loss of 8 TSVs with TSV equalizer
-8
0.1
1
10 20
Frequency [GHz]
• We successfully flattened frequency dependent loss by 3.8 dB
by using TSV Equalizer.
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Time Domain Simulation-based Verification of the TSV
Equalizer Performance
0.25
Voltage (V)
Voltage (V)
0.25
0
Pk-pk jitter : 16 ps
0
Eye opening: 100mV
-0.25
0
20
40
60
Time (ps)
80
100
-0.25
0
20
40
60
80
100
Time (ps)
• We successfully achieved normalized pk-pk jitter and eye-opening,
32% and 20%,
meanwhile the unequalized eye is completely closed.
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Conclusion

We analyzed the loss mechanism of a TSV with scalable equivalent
circuit model which is verified with measurement.

We analyzed the frequency dependent loss of a TSV which is
capacitive and resistive.

We proposed the TSV Equalizer by using DC attenuation from an
ohmic contact to flatten the frequency dependent loss of a TSV.

With the proposed TSV Equalizer, we achieved normalized timing jitter
and eye opening, 32% and 20%, even with the almost closed eye.
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