Vol. 35, No. 12
Journal of Semiconductors
December 2014
A method to restrain the charging effect on an insulating substrate in high energy
electron beam lithography
Yu Mingyan(于明岩)1; 2; Ž , Zhao Shirui(赵士瑞)2 , Jing Yupeng(景玉鹏)2 , Shi Yunbo(施云波)1 ,
and Chen Baoqin(陈宝钦)2
1 The Higher Educational Key Laboratory for Measuring & Control Technology and Instrumentations of Heilongjiang Province,
Harbin University of Science and Technology, Harbin 150080, China
2 Key Laboratory of Microelectronics Devices & Integrated Technology, Institute of Microelectronics, Chinese Academy of
Sciences, Beijing 100029, China
Abstract: Pattern distortions caused by the charging effect should be reduced while using the electron beam lithography process on an insulating substrate. We have developed a novel process by using the SX AR-PC 5000/90.1
solution as a spin-coated conductive layer, to help to fabricate nanoscale patterns of poly-methyl-methacrylate
polymer resist on glass for phased array device application. This method can restrain the influence of the charging
effect on the insulating substrate effectively. Experimental results show that the novel process can solve the problems of the distortion of resist patterns and electron beam main field stitching error, thus ensuring the accuracy of
the stitching and overlay of the electron beam lithography system. The main characteristic of the novel process is
that it is compatible to the multi-layer semiconductor process inside a clean room, and is a green process, quite
simple, fast, and low cost. It can also provide a broad scope in the device development on insulating the substrate,
such as high density biochips, flexible electronics and liquid crystal display screens.
Key words: charging effect; pattern distortions; electron beam lithography
DOI: 10.1088/1674-4926/35/12/126002
EEACC: 2520
1. Introduction
Electron beam lithography (EBL) is one of the fabrication
techniques considered for nano-scale devicesŒ1 4 . With the
continuous miniaturization of the critical dimension (CD) of
semiconductor technology, the nanolithography technique has
reached the 22 nm threshold and lowerŒ5 . In this condition, an
electron beam with a high accelerating voltage is much more
advantageous when fabricating a sub-22 nm pattern sizeŒ6 .
While using insulating substrates, which is often restricted by
the surface charging effect during electron beam direct writingŒ7 9 , charge is trapped around the substrate surface and
cannot be dissipated as on conductive substrates. The higher
the electron beam voltage is, the larger the scattering range is,
the larger the amount of accumulated charge is, and the more
serious the charging effect is. Figure 1 shows the discharge
phenomenon and lines distortion of the photoresist caused by
the charging effect in our previous experiment. Therefore, it
is important to find a new method to solve this problem. Researchers used an electron beam with a low accelerating voltage to fabricate PMMA patterns on glass and they obtained
good resultsŒ10; 11 .
Generally, in order to restrain the influence of the charging effect, a layer of metal film is deposited on the surface of
the substrate to dissipate the accumulated charge. However,
this kind of method is used successfully for first layer electron beam direct writingŒ12 15 . Due to the metal contamination, the metal film is not allowed in some semiconductor pro-
cesses. Besides, the metal film can generate an electron current in high energy lithography, which can also repel the direct writing electron beam and cause the deviation of exposure
beam position. While using electron beam lithography for the
next several layer overlay to pre-pattern structures, it is still a
challenge to dissipate the accumulated charge on the isolated
patterns on insulating substrates without causing pattern distortion. In this paper, in order to fabricate the Phase Array Devices with a glass substrate, a novel process using conductive
resist SX AR-PC 5000/90.1 (GermanTech Co., Ltd) was developed to restrain the charging effect; not only can it be used
on pre-patterned isolated structures on an insulating substrate,
but also it can be expanded to the untreated insulating substrate
directly. The process has several advantages. First, it is totally
compatible to the semiconductor process in a clean room, so the
conductive layer can be spin-coated on the substrate directly.
Second, the conductive layer is water soluble, which can be
removed easily without affecting the performances and structures of the device. Thus the process is a green, simple, fast and
low cost process.
2. Experimental
The SX AR-PC 5000/90.1 solution (GermanTech Co., Ltd)
is spin-coated to form a conductive protective thin layer, to
dissipate the electrostatic charges generated during electron
beam direct writing. There are many tiny conductive particles that are added to the conductive resist solution. During
* Project supported by the National Natural Science Foundation of China (No. 61475079) and the National Major Scientific Equipment
Developed Special (No. 2011YQ4013608).
Ž Corresponding author. Email: yumingyan@ime.ac.cn
c 2014 Chinese Institute of Electronics
Received 26 March 2014, revised manuscript received 26 June 2014
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Yu Mingyan et al.
Fig. 1. Discharge phenomenon and lines distortion of photoresist
caused by the charging effect in high energy electron beam lithography on insulating substrate.
the beam writing process, the accumulated charges are dissipated through the exposure of these conductive particles. The
detailed mechanism using conductive particles as the charge
dissipating medium is still under investigation nowadays. After being exposed by an electron beam, the performance of the
conductive resist layer is similar to a negative resist, while it is
immersed in deionized water, as the developing process, within
2 min, there are patterns left. While developing for more than
10 min, all conductive layers will be completely removed with
the bottom layer uncovered. In the experiment, we conducted
three sets of comparative processes on an insulating substrate
to develop a suitable process for phase array device fabrication by overlay and direct writing, using a metal layer and a
conductive polymer layer respectively as the charge dissipating medium. The three processes are illustrated as follows.
1. For substrate 1#, the experimental procedures are as follows.
(1) A layer of ITO (Indium tin oxide) and a layer of Cr
were deposited on the surface of the glass substrate.
(2) A layer of SAL601 resist was spin-coated above the
Cr layer. The first layer patterns were exposed by the MEBS
4700S EBL system. The patterns were developed after exposure.
(3) The patterns generated were transferred to a metal
ITO/Cr layer by chemical etching. The patterned metal structures became isolated, which were separated by an uncovered
glass substrate.
(4) A layer of PMMA resist was spin-coated above the
metal pattern with 3000 r/min for 1 min, and subsequently the
substrate was baked via a hot plate at 180 ıC for 2 min, then the
overlay and direct writing was proceeded by a high resolution
JBX-6300FS EBL system.
(5) The developing of PMMA was conducted by 1 : 3 of
MIBK (methyl isobutyl ketone) and IPA (iso-propyl alcohol)
solution. The developing time was 5 min, and the time for
fixing with IPA was 30 s. The whole experiment was carried
out under ambient clean room conditions. The process flow is
shown in Fig. 2.
2. For substrate 2#, the experimental procedures are as fol-
Fig. 2. Schematic process flow diagram of insulating substrate 1#
coated with charge dissipating metal layer and PMMA resist.
lows.
(1) A layer of ITO and a layer of Cr were deposited on the
surface of the glass substrate.
(2) A layer of SAL601 resist was spin-coated above the
Cr layer. The first layer patterns were exposed by the MEBS
4700S EBL system. The patterns were developed after exposure.
(3) The patterns generated were transferred to a metal
ITO/Cr layer by chemical etching. The patterned metal structures became isolated, which were separated by an uncovered
glass substrate.
(4) A layer of PMMA resist was spin-coated above the
metal pattern with 3000 r/min for 1 min, and subsequently the
substrate was baked via a hot plate at 180 ıC for 2 min. All
the above procedures were the same as for substrate 1#. Then a
layer of conductive resist was spin-coated above PMMA with
300 r/min for 1 min. Then the overlay and direct writing was
proceeded by the high resolution JBX-6300FS EBL system.
(5) The developing process was successfully conducted as
follows. The substrate was first immersed in deionized water
for 10 min to remove the conductive resist layer completely,
and then the PMMA resist was developed using an organic solvent, as illustrate for substrate 1#. The immersion and removal
of the conductive layer with water did not affect the developing
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Fig. 4. Schematic process flow diagram of insulating substrate 3#
coated with PMMA resist and conductive polymer layer.
Fig. 3. Schematic process flow diagram of insulating substrate 2#
coated with a metal layer, PMMA resist and conductive polymer layer.
process and the performance of the PMMA resist at all.
The flow process is shown in Fig. 3.
3. For substrate 3#, the experimental procedures are as follows.
(1) After the spin-coated layer of PMMA, another layer
of conductive resist was spin-coated on the substrate directly.
Then the substrate was exposed by the JBX-6300FS EBL system.
(2) After the exposure process, substrate 3# was immersed
in deionized water for 10 min to remove the top conductive
layer completely, and then the PMMA resist was developed
using an organic solvent as illustrated for substrate 1#. The process flow is shown in Fig. 4.
3. Results and discussion
3.1. Charging effect and pattern distortion on insulating
substrate with pre-patterned isolated metal structures
Figure 5 shows the SEM (scanning electron microscope)
image of the substrate 1#. Figure 5(a) is the test pattern data
in the experiment and its dimension is 1 1 mm2 . Figure 5(b)
is an enlarged SEM view of part of the center of the test pattern, where the designed line width from left to right are 500,
1000, 100, 50, and 40 nm respectively. The distances between
all lines are 50 m and the dimension of the rectangle pattern
area in (d) is 14 12 m2 . It can be seen that the line distortion still exists under the condition of a metal interlayer on
glass, although it is not serious as shown in Fig. 1.
In Fig. 5, the distortion caused by the surface charging
effect on a glass substrate is measured by SEM. The distortion around the square area is obvious because there is more
charge accumulated. For substrate 1# in Fig. 5, before the first
exposure process, the metal layer is grounded by connecting
with the conductive probe, as shown in Fig. 2, which is nowadays widely used to dissipate the charge while directly writing
on insulating substrates. However, after the chemical etching
process, the area of the substrate uncovered on glass is nonconductive. That is, the structures of ITO and Cr are isolated
without being grounded, and the accumulated charge cannot
dissipate, so the distortions still exist. The Cr and ITO layers
alleviate the charging effect on an insulating substrate, to a certain degree.
The mechanism of pattern distortions is illustrated in
Fig. 6. Figure 6(a) is a schematic of the exposure main field
division for a patterned structure. The dimension of each main
field used here is 62.5 m, and the electron beam exposal sequence is shown as the arrow direction. Figure 6(b) is the enlarged view of each main field, the scanning direction of the
electron beam is shown as the arrow and the scanning range
of the electron beam as a sub-field is about 250 nm. For single
lines with critical dimensions of 1 m, and 500 nm, after exposure, they were divided into four lines and two lines, respectively, as illustrated in Figs. 5(c), 6(c) and 6(e). The distortion
and pattern overlay are still challenges to Phase Array Device
fabrication using a glass substrate.
The level of main field stitching and pattern distortion is
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Yu Mingyan et al.
Fig. 7. Simulation analysis of the quantity of accumulated charge with
different accelerating voltages.
Fig. 5. Distortion of main field exposure caused by the charging effect
on an insulating substrate, where the stitching error reaches several
microns. (a) The test pattern for the experiment, which includes a line
group with a different width and rectangle area with different dimensions. (b) Part of an enlarged view of the distortions of exposure of the
main fields and lines. (c) Part of an enlarged view of the distortion of
a line with a 1 m width; the line is divided into four lines. (d) Distortion of a rectangular pattern of 14 12 m2 . (e) Part of an enlarged
view of (d).
on an insulating substrate, the charging accumulation phenomena can be compared with the proximity effect caused by the
electron scattering in electron beam lithographyŒ16 . The randomness of electron scattering trajectories is used to reflect the
scattering range of electrons in an insulating substrate. Figure 7
shows a simulation analysis for the variation of the scattering
range of accumulated charge with different electron beam accelerating voltages on a glass substrate. The scattering range
increased and finally achieves its maximum at 100 keV when
the voltage is enlarged from 10 to 100 keV, and meanwhile,
the influence range of the pattern distortion is also the largest
at 100 keV in experiments. Nowadays, low-voltage electron
beam lithography is recommended for directly writing work
on an insulating substrateŒ17 .
Further, according to the research of Satyalakshmi et al.Œ17
and our previous experiments, the distortion is also depends on
several factors, such as the dimension size and density of patterns, the working distance of the electron beam, the surface
charge density, the molecular weight of the resist, and the dielectric constant of insulating substrate materials, etc. A more
detailed physical model is still under investigation to understand the influence of the charging effect in future study.
3.2. Charging effect restrained using conductive polymer
layers on an insulating substrate with pre-patterned
isolated metal structures
Fig. 6. Schematic of the exposure main field and the distortion of test
pattern. (a) The division of the exposure main field. (b) Part of an
enlarged view of each main field. (c) Distortion of a line with 1 m
width. (d), (e) Schematics of the test pattern in Fig. 5(c).
related to the amount of charge trapped in the square patterns.
At the square patterns area, the amount of accumulated charge
is large, so the distortion is obvious, and the larger the square
pattern area is, the more serious the distortion becomes. From
Fig. 5(c), it can be seen that the distortion of 1 m line is about
5 m for a square pattern of 5 5 m2 , and the pattern distortion and stitching error for the 250 nm sub-field is about
hundreds of nanometers to 1 m.
In order to elucidate the influence of charge accumulation
on the deviation of the electron beam direct writing position
Figure 8(a) shows the exposure result of substrate 1# without conductive resist, (b), (c), (d) are enlarged views of (a); (e)
is the exposure result of substrate 2# with a thin layer of conductive resist, it can be seen that the distortions are improved
to a certain degree, but they cannot be eliminated. Besides, the
immersion time is 1 min for the conductive resist in deionized
water, which is not enough for the residue to be dissolved completely. When the immersion time is extended to 10 min, the
residue can be removed completely, as shown in Figs. 9 and
10.
Figure 9 shows the exposure result of substrate 2# with
a thick layer of conductive resist, where the charging effect
can be restrained effectively. The overlay and direct writing
with the electron beam lithography system can be routinely
processed on the insulating substrate with isolated metal pat-
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Fig. 9. Exposure result of substrate 2# with a thick layer of conductive
resist after being immersed in DI water for 10 min.
Fig. 8. Example of distortion and stitching error of main field exposure
caused by the charging effect on insulating substrate. (a) Exposure
result of insulating substrate 1# without conductive resist. (b), (c), (d)
Part of an enlarged SEM view of (a). (e) Exposure result of insulating
substrate 2# with a thin layer conductive resist. The immersed time of
the conductive resist in DI water is 1 min.
terns. The phase array devices can be successfully developed
by using the conductive resist layer. The process is easily performed, green as it uses a water solution, and has a low cost.
Particularly, it is compatible to the semiconductor process in a
clean room.
3.3. Charging effect restrained using conductive polymer
layers on various insulating substrates
Figure 10 shows the exposure result of substrate 3# with
a thick layer of conductive resist above the PMMA directly.
From Fig. 10, it can be obtained that whether the insulating
substrate with isolated metal patterns, or directly insulating the
substrate, the charging effect can be restrained effectively by
applying a thick layer of conductive resist. It can provide a
broad scope in the device development on an insulating substrate, such as high density biochips, flexible electronics and
Fig. 10. (a) Exposure result of substrate 3# with a thick layer of conductive resist above the PMMA directly. (b), (c), (f) Part of the enlarged view of (a), where the designed width of the line group from
left to right is 1–10 nm respectively in (b). (d), (e) Enlarged views of
(c) and (f) respectively, where the designed line width is 1 m in (d).
liquid crystal display screens.
Therefore, through the three sets of experiments, it can be
obtained that after the first exposure process, the major factor
of solving the charge accumulation on an insulating substrate in
high-energy electron beam lithography is the conductive resist
rather than the metal pattern.
4. Conclusion
The charging effect, which could induce the pattern distortion of a PMMA resist on glass is investigated at the high
electron beam energy of 100 keV. This paper presents a new
method, which uses a conductive resist containing conductive
particles to restrain the charging effect on the insulating sub-
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Yu Mingyan et al.
strate. This method is particularly suitable for the semiconductor process, which is not compatible with the metal conductive
layer in electron beam lithography. The results show that, either on the insulating substrate with an isolated metal pattern,
or on the insulating substrate directly, the charging effect can
be restrained effectively by using this method. This technology has been successfully applied to the fabrication of a multiphased driving electrode device, and has solved the problem of
the charging effect in high energy electron beam lithography on
an insulating substrate.
[8]
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