Dynamic Virtual Ground Voltage Estimation
for Power Gating
Hao Xu, Ranga Vemuri, Wen-Ben Jone
Dept. of ECE, University of Cincinnati
814 Rhodes Hall, Cincinnati, OH 45221-0030, USA
{xuho, ranga, wjone}@ececs.uc.edu
ABSTRACT
With the technology moving into the deep sub-100nm region, the
increase of leakage power consumption necessitates more aggressive power reduction techniques. Power gating is a promising technique. Our research emphasizes the virtual ground voltage (VVG)
as the key to make critical design trade-offs for power gating. We
develop an accurate model to estimate the dynamic VVG value of a
circuit block as a function of time after its ground is gated. Experimental results show that the model has less than 1% average error
compared with HSPICE results. The CAD tool implemented based
on the model has a 100× speedup over HSPICE.
Categories and Subject Descriptors
B.7.2 [Integrated Circuit]: Design Aids–Simulation
General Terms
Design, Performance
Recently, studies have shown that the Virtual Ground Voltage
(VVG) has a significant impact on most design issues related to
ground power gating, as shown in Figure 1. (Virtual VDD voltage
has a similar impact on supply power gating. We will only study
ground gating in this paper since it is used in most design practises.)
There are several reasons for this. First, the leakage current has
exponential relationship with the circuit voltage potential, so the
VVG value determines the effectiveness of leakage power reduction. Second, Singh et al. [3] establish the quadratic dependency
of the circuit wake-up time on VVG. They also show that the rush
current after wake-up is directly proportional to the VVG value,
whereas the energy saving is reversely proportional to it. Based
on this observation, they propose an “intermediate strength power
gating” method to control the VVG value, and thus make design
trade-offs among energy saving, wake-up time and ground-bounce
noise. Similarly, Kim et al. [4] propose a “multi-mode power gating” structure providing several possible VVG values for designers
to choose from. Third, the VVG value directly affects the voltage
of the output logic [2]. So it is important for data retention as well.
Keywords
Leakage power consumption, Power gating, Virtual ground voltage
1.
VD D
LOGIC CIRCUIT
INTRODUCTION
MOSFET scaling into deep sub-100nm has resulted in significant increase in leakage power consumption. Particularly, in 45nm technology and beyond, leakage power consumption will catch
up with, and may even dominate, dynamic power consumption
[1]. This makes leakage power reduction an indispensable component in the nano-era low power design. Sub-threshold leakage,
gate leakage and band-to-band tunneling leakage are the three main
components contributing to the total leakage power.
Power gating, or sleep transistor technique, has been introduced
and studied to reduce sub-threshold leakage as well as gate leakage
[1]. Various design issues must be considered while determining
the efficacy of power gating. Performance penalty, ground-bounce
noise, wake-up delay and data retention are among the major issues
to be considered [2].
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Virtual Ground
SLEEP
GND
Figure 1: Virtual Ground of Ground Gating
So far, all the studies in the literatures are based on the assumption that the VVG value is static. The sleep time of the circuit
is considered to be long enough such that the internal node will
be charged to a steady value [3,4,5]. This steady value is then
used to estimate the leakage savings, wake-up time, ground-bounce
noise and so on. The impact of variation in the VVG value before it reaches the steady value has not been studied. We will call
this variation the “dynamic” value of VVG (Figure 2). As CMOS
technology scales down, we believe that modeling of the dynamic
VVG value will become critical. There are two reasons for this.
First, the ratio of the leakage to dynamic power consumption increases quickly as the technology scales down. Hence in the future, the energy breakeven point of the circuit can occur before its
virtual ground gets fully charged. For example, our simulation results show that in 32nm predictive technology [9] on benchmark
circuit C7552, the energy breakeven point occurs well before the
VVG value reaches its steady value (T1=3ns T3=80ns, Figure
2). Second, in order to develop more aggressive power reduction
techniques, such as active leakage power saving or fine-grained
power gating, the circuit needs to enter the sleep mode more fre-
VVG
Dynamic
where K1 , K2 and K3 are technology-dependant exponents, and I
is the leakage current under the normal condition terminal voltages.
For ground gating, the terminal voltages of the off-state NMOS
or PMOS have the patterns as shown in Figure 3. Note that in equations and figures we use VV G to denote the voltage of the virtual
ground. The leakage current for ground gating can be expressed as:
Static
Steady Point
Possible M inim um Sleep T im e
Energy B reakeven T im e
T1
T2
T3
Time After The Ground Is Gated
V D = V DD
Figure 2: Dynamic VVG Versus Static VVG
V G= V VG
quently to exploit idleness. Thus the minimum sleep time can be
further reduced. In Figure 2, the minimum sleep time T2 can be
any value larger than T1, and can fall in the dynamic VVG range.
The accurate estimation of dynamic VVG as a function of time will
be a necessity when making design trade-offs in this case, as well
as in future power gating designs in general.
For the first time, this paper presents an accurate model for dynamic VVG at any time after the ground is gated. This model can
also give estimation of the dynamic leakage energy saving. This
paper is organized as follows. In Section 2 detailed model derivation is presented. Section 3 presents the CAD tool implemented
based on the model and discusses the experimental results. Finally,
Section 4 concludes the paper.
2.
DYNAMIC VVG MODEL DERIVATION
In the following modeling process, we consider the sub-threshold
leakage as the major leakage source. The gate leakage is projected to have a reduction of 100× in the 45nm technology with
the use of high-k dielectrics [6,8]. And because of the exponential
dependency of the sub-threshold leakage on temperature, the subthreshold leakage is still the dominant leakage component during
run-time. In this paper, we focus on the sub-threshold leakage and
refer to it as leakage.
2.1 Static VVG Modeling at Transistor Level
The static VVG estimation has been discussed in many literatures. Generally, it can be obtained by matching the leakage current
of a logic circuit with the leakage current of the ground gate device
(the footer). Singh et al. [3] give the equation to obtain the static
VVG value as follows.
Ileak (Circuit) = Ileak (F ooter)
(1)
Substituting Ileak (Circuit) and Ileak (F ooter) in the above equation with functions of VVG yields a new equation of VVG. In [3],
this equation is solved to obtain the static VVG value. However unlike [3], we will firstly simplify the VVG equation before solving
it. Starting from the single transistor sub-threshold leakage current
model in [1], we have:
I = A · e1/mVT (VG −VS −Vth0 −γ
with A = µ0 Cox
VS +ηVDS )
· (1 − e−VDS /vT )
W
(vT )2 c1.8 c−∆Vth /ηvT
Lef f
(2)
where Vth0 is the zero bias threshold voltage, vT is the thermal
voltage, γ is the linearized body effect coefficient, and η is the
DIBL coefficient. When VDS vT , the term (1 − e−VDS /vT ) in
the above equation can be neglected. Assuming that the temperature and the body bias voltage are fixed, we can simplify Equation
2 into:
I = I · eK1 VG +K2 VD −K3 VS
(3)
V B= 0
(Cons tant)
V S =V VG
NMO S leakage so urce
V S = V DD
V G= V DD
V B= V DD
(Cons tant)
V D =V VG
P MO S leakage so urce
Figure 3: Voltage Biases of NMOS and PMOS With Ground
Gating
⎧
⎪
I = I · eK1 VG +K2 VD −K3 VS
⎪
⎨
VG = VV G (N M OS) VG = VDD (P M OS)
(4)
⎪
⎪ VD = VDD (N M OS) VD = VV G (P M OS)
⎩
VS = VV G (N M OS) VS = VDD (P M OS)
Solving the above equations yields:
IN = I · eK1 VV G +K2 VDD −K3 VV G = IN · e−KN VV G
IP = I · eK1 VDD +K2 VV G −K3 VDD = IP · e−KP VV G
(5)
where IP (IN ) is the leakage current of PMOS (NMOS) with zero
VVG, and KP (KN ) is the leakage reduction exponent of PMOS
(NMOS). So a single transistor in off-state can be modeled as a
VVG-controlled current source. Note that the simplification of the
term (1 − e−VDS /vT ) in Equation 2 causes inaccuracy when VDS
is comparable with vT . (When VDS equals to 4vT , the error is
1.8%.) However, when VDS is small, the leakage current is very
small such that it can be approximated as zero in EBT calculation.
Hence our model is accurate when VDS < 4vT . Typically, the
final steady value of VV G is less than VDD − 4vT , due to the footer
leakage.
The footer has a similar model since essentially it is a NMOS
transistor with high threshold voltage. By using Equation 5 to substitute the leakage current in Equation 1, the static VVG value of a
single transistor circuit can be obtained. However we stop here and
turn to dynamic VVG modeling. The static VVG can be obtained
from our dynamic VVG model as well.
2.2 Dynamic VVG Modeling at Transistor Level
Considering a NMOS transistor with its ground gated by a footer,
we now model its dynamic VVG. As soon as the footer is turned
off, the leakage current starts to charge the internal nodes. As a
result, the VVG level gradually rises. Consequently, the leakage
current is reduced according to Equation 5. As shown in Figure 4,
we model this as a charging process of the virtual ground capacitor
by a VVG-controlled current source. The resistances of the transistor and the interconnect do not affect the charging time, since the
charging is due to an equivalent current source. The resistance is
then neglected in our model. We have designed an experiment in
Section 3 to verify this simplification.
By considering VVG and leakage current as functions of time,
the charging process can be characterized as:
t
⎧
VV G (t) = C1 0 Icharge (t)dt
⎪
⎪
⎨ I
charge (t) = INM OS (t) − If ooter (t)
(6)
−KN VV G (t)
I
⎪
NM OS (t) = IN · e
⎪
⎩
−KF VV G (t)
If ooter (t) = IF · e
VD D
impact of stacking effect on the leakage current. Consider a general
case of transistors in series as shown in Figure 6a. Assume that the
upper terminal voltage of the four-transistor stack is Va , and the
virtual ground voltage is VV G . By using Equation 3, the leakage
I CIRCUIT
VVG
I CHARGE
VVG
SLE E P
C
I FOOTER
V VG
V1
V VG
The above solution gives the model of dynamic VVG at the transistor level. Additionally, the leakage current as a function of time
is given by:
C
(8)
INM OS (t) =
KN (t + K CI )
N N
2.3 Dynamic VVG Modeling at Gate Level
In the following study, we show modeling of dynamic VVG at
the gate level.
Consider a two-input NAND gate. Since the input vectors have
significant impacts on the leakage current, we model the gate by
each input vector. As shown in Figure 5, the two-input NAND gate
is modeled into four VVG-controlled leakage current sources (Ii ),
with equivalent capacitances (Ci ) attached to the virtual ground of
the gate. The next question is to find out the relationship between
1
0
0
1
0
0
1
1
0
0
1
0
1
0
I1
I2
VVG
PM O S
Leakage
C1
I3
VVG
NMOS
Leakage
C2
I4
VVG
C3
NMOS
Leakage
VVG
V3
V VG
V VG
V VG
a. Fo u r o ff-state N M O S stack
b . Th e seco n d N M O S is o n
Figure 6: Off-state Transistors In Series
current for each transistor is given below:
⎧
I1 = I1 eK1 VV G +K2 Va −K3 V1 = Iseries
⎪
⎪
⎨
I2 = I2 eK1 VV G +K2 V1 −K3 V2 = Iseries
⎪
I = I3 eK1 VV G +K2 V2 −K3 V3 = Iseries
⎪
⎩ 3
I4 = I4 eK1 VV G +K2 V3 −K3 VV G = Iseries
(9)
where Iseries is the leakage current of the stack. Substitute Ii
˘
(i=1,2,3,4) with eIi . Equations 9 turn into:
⎧
K2 Va − K3 V1 + I˘1 = ln(Iseries /eK1 VV G )
⎪
⎪
⎨
K2 V1 − K3 V2 + I˘2 = ln(Iseries /eK1 VV G )
(10)
⎪ K2 V2 − K3 V3 + I˘3 = ln(Iseries /eK1 VV G )
⎪
⎩
K2 V3 − K3 VV G + I˘4 = ln(Iseries /eK1 VV G )
Solving the above equations yields:
2.3.1 Example Of Two-input NAND Gate
1
V2
V VG
V3
V VG
V1
1
V2
V VG
where t is the time after the ground is gated, and C is the equivalent
capacitance attached to the virtual ground. In this case, C includes
the junction capacitances of the NMOS and the footer, and gate
capacitance of the NMOS. IF and KF are the zero-VVG leakage
current and leakage reduction exponent of the footer, respectively.
In the above equations when the VVG level is low, the leakage
current of the footer is very small and can be ignored. (The footer
leakage will be considered in the circuit level model.) Equations 6
can then be solved as:
C
1
KN IN
VV G (t) =
(t +
ln(
))
(7)
KN
C
KN IN
I leak
Va
V VG
Figure 4: Transistor Level Dynamic VVG Modeling
1
I leak
Va
GND
C4
NMOS
Leakage
Figure 5: Two-input NAND Gate Dynamic VVG Modeling
the leakage current (Ii ) of the gate and the VVG. Since the offstate transistors control the amount of leakage current, our answer
starts from studying two basic gate structures: off-state transistors
in series and parallel.
2.3.2 Off-state Transistors In Series
Case four in Figure 5 has the minimum series structure of two
off-state NMOS transistors in stack. Our first goal is to find out the
Iseries = e
4 V +A
K2
a
B
where,
·e
4
K1 B−K3
B
VV G
= Iseries · e−Ks VV G (11)
A = K23 I˘1 + K22 K3 I˘2 + K2 K32 I˘3 + K33 I˘4
B = K23 + K22 K3 + K2 K32 + K33
With the stacking effect, the leakage current still has an exponential dependency on VVG. The difference is that the leakage reduction exponent turns into an equivalent exponent KS , and the zeroVVG leakage current of the stack turns into Iseries . Now consider
a special case that one of the transistors in the stack is on as shown
in Figure 6b. Assume the voltage difference between V1 and V2 is
negligible. This case is then equivalent to a three-transistor stack.
Hence if some transistors in the stack are in the on-state, the total
leakage current of the stack still satisfies Equation 11.
2.3.3 Off-state Transistors In Parallel
Case one in Figure 5 is the simplest example of off-state transistors in parallel. Since both PMOS transistors have the same
leakage reduction exponent K, the total leakage remains an exponential function, despite of the transistor sizes. Similarly, for a
parallel structure with only one transistor in each branch (Figure
7a), the total leakage is an exponential function of VVG. The parallel structure can be complex when a branch has more than one
transistor. Due to the stacking effect, it can have different K values
depending on the number of off-state transistors in that branch. For
example in Figure 7b, by using the result of Equation 11, the total
leakage current can be expressed as:
Iparallel = Ia e−Ka VV G + Ib e−Kb VV G + Ic e−Kc VV G + ... (12)
0
Ia
Ib
Ic
Va
Vb
Vc
0
Ia
0
Va
Ib
Ic
Vb
0
0
1
0
1
0
a single current source (Iij ), with a single equivalent capacitance
(Cij ). Hence in this step, we build a downsized circuit model with
maximally j2i current sources.
⎧
⎨ Iij = ( Iijh )e−Kij VV G
h
(14)
Cijh
⎩ Cij =
Vc
V VG
V VG
a. O ne transistor in each branch
b. M ore than one transistor in each branch
h
Figure 7: Off-state Transistors In Parallel
where Ki (i = a, b, c...) is the equivalent leakage reduction exponent of each branch. Since Ki is different, the total leakage current is no longer a simple exponential function. However, we still
approximate Iparallel into a single exponential function of VVG
because of two reasons.
1) Most gates have the simple parallel structure shown in Figure
7a, for example, NAND gates, NOR gates and Buffers.
2) For complex parallel structures, the K values can be different
because the number of off-state transistors in each branch is different. In this case, due to the stacking effect, the branches with the
least number of off-state transistors (branches b and c in Figure 7b)
have much larger leakage current than other branches (at least one
order of magnitude [1]) and become the dominant ones. The total
leakage current of the gate is close to the sum of dominant branches
current with the same K value. Hence it can be approximated as
an exponential function.
We have shown that the leakage current of any number of offstate transistors in series is an exponential function of VVG. And
in parallel, it can be approximated into an exponential function. So
for any type of gate structure, we model the total leakage current
of the gate as an exponential function of VVG. Conclusively, we
define the full-fledged gate model as follows. For each input vector
i, the gate is modeled as an equivalent virtual ground capacitance
Ci and a VVG-controlled current source Ii satisfying:
(13)
Ii = Ii e−Ki VV G
where Ii is the zero-VVG leakage current, and Ki is the equivalent
reduction exponent of the gate. Use this gate model to substitute
the NMOS model in Equations 6 and solve them in a similar way.
The dynamic VVG of the gate can be obtained.
2.4 Dynamic VVG Modeling at Circuit Level
At the circuit level after the ground is gated, each gate in the
circuit can be modeled as a VVG-controlled current source with a
capacitance attached to the virtual ground of the circuit, as shown
in Figure 8. Take the footer leakage current into account. We derive
the circuit level model in two steps.
I3
G3
I4
G4
C4
C3
VVG
G1
G2
I1
I2
C1
SLEEP
VVG
C Fo o ter
C2
I leak (Footer)
Figure 8: Dynamic VVG Modeling At Circuit Level
STEP ONE
For those gates (h), which have the same gate type (j) and receive the same input vector (i), they can be linearly combined into
STEP TWO
Now the total charging current to the virtual ground of the circuit turns into the summation of all Iij of each gate in the circuit,
subtracted by the⎧footer leakage current:
I
= Icircuit − If ooter
⎪
⎨ charge Iij e−Kij VV G
Icircuit =
(15)
ij
⎪
⎩
If ooter = IF e−KF VV G
The total virtual ground capacitance of the circuit is a linear summation of all the equivalent capacitances Cij . By considering the
VVG and the current as functions of time, the charging process of
the⎧circuit VVG can be characterized
as:
t
1
⎪
VV G (t) = Ctotal
I
(t)dt
charge
⎪
⎪
0 −Kij VV G (t) −KF VV G (t)
⎨
− IF e
Iij e
Icharge (t) =
(16)
ij
⎪
⎪
⎪
=
C
ij
⎩ Ctotal
ij
The above equations do not have a closed-form solution. Our approach to address this problem is called the Step-Solver. It includes
the following six sub-steps.
a) Divide the full VDD scale into r voltage regions. The number
of r is a trade-off between accuracy and speed. Larger r causes
more solving iterations and thus slower speed. Smaller r causes
larger error of linear regression in Sub-step b and thus less accuracy.
In our experiments, r is chosen to be 18.
b) Perform linear regression in each voltage region r on all the
gate level leakage current model (Iij ), and the footer leakage model.
We obtain the linearized
in each region:
r models
r
Iij = Sij
VV G + Tijr
(17)
Ifrooter = SFr VV G + TFr
r
r
where Sij and Tij are the linearized parameters for the leakage
current model of each gate in each region r, and SFr and TFr are the
linearized parameters for the footer.
c) The total charging current in region r turns into:
r
Icharge = (Sij
VV G + Tijr ) − (SFr VV G + TFr )
ij
(18)
= Sr V V G + T r
where Sr and Tr are the linearized model parameters for the total
charging current of the circuit in each region r.
d) Substitute the charging current in Equations 16 with the above
linearized model. Make the VVG and the current as function of
time. Solving it yields:
1 C Sr t
(e total − Tr )
(19)
VV G (t) =
Sr
e) Starting from the first voltage region, use Equations 19 to obtain the dynamic VVG in that region.
f) Use the results of Sub-step e as the initial Icharge and VV G of
the next region (r + 1) and obtain the dynamic VVG for (r + 1).
Then go back to Sub-step e iteratively until the VVG value of the
last voltage region is solved.
2.5 Voltage Dependant Capacitance
In the previous study, the equivalent capacitance attached to the
virtual ground is considered to be a constant. However, it is shown
that the gate capacitance of a transistor has a dependency on its
VGS [7], which is a changing value during the VVG charging process. So our model needs to take this phenomenon into consideration. Once again, we divide the full VDD scale into r voltage
1 C rSr t
(e total − Tr )
(20)
Sr
r
is the equivalent virtual ground capacitance of the circuit in
Ctotal
each region r. Equation 20 gives the entire dynamic VVG model at
the circuit level. For a given circuit, this model is able to estimate
the VVG value at any time after the ground is gated. Additionally,
this model can also give estimation on the dynamic leakage energy
saving Es (t) by:
Es (t) = VDD · Icircuit · t − VDD · VV G (t) · Ctotal
(21)
where the first term is the leakage energy consumption of the circuit
without ground gating, and the second term is the energy consumption for charging the virtual ground when applying ground gating.
If we assume that the energy leaking away from the footer is negligible, the second term equals to the leakage energy consumption
of the circuit at time t after its ground is gated.
VV G (t) =
3.
EXPERIMENTAL RESULTS OF DYNAMIC
VVG MODEL
A CAD tool has been implemented based on the model. The
tool flow is similar to our model derivation process. The gate level
model (Ii , Ki , Ci ) in Equation 13 and the footer model are characterized from the cell library and the technology files. Then the
first-step circuit level model (Iij , Kij , Cij ) in Equation 14 are calculated from the gate level model, the footer model and the circuit
netlist. Finally the Step-Solver solves the dynamic VVG model at
the circuit level in Equation 20.
Experiments have been conducted to compare the HSPICE simulation results with model estimations. The ISCAS85 benchmark
circuits in 32nm, 45nm and 65nm technologies [9] are used in the
experiments. The gate level implementation and parasitic information of the benchmarks is from [10]. We insert footers into the
benchmark circuits to implement the ground gating. Since footer
sizing does not affect the correctness of our model, it is designed to
be equal to the NMOS width of the circuit for simplicity.As soon as
the footer is turned off, the HSPICE simulation data of the dynamic
VVG value is collected and compared with the model estimations.
The simulation temperature is set to be 110C to emulate the runtime temperature. The gate leakage is set to be zero.
1) Experimental Results of Resistance Impact
To verify the resistance impact on the dynamic VVG, we replaced all the original parasitic resistances in each circuit by 10
(100) times of their own values. Then the VVG simulation results
of the new circuit with bigger resistances are compared with the
results of the original circuit. As shown in Table 1, the bigger resistance causes a maximum variation of 0.17% to the VVG values
in all three technologies. This experiment proves that resistance
can be neglected in the model.
BM.
C432
C1355
C2670
C3540
C7552
Gate
Cnts.
160
546
1193
1669
3521
32nm
10x 100x
0.02% 0.12%
0.01% 0.04%
0.01% 0.05%
0.02% 0.08%
0.01% 0.07%
45nm
10x 100x
0.02% 0.19%
0.01% 0.12%
0.02% 0.06%
0.03% 0.12%
0.03% 0.08%
65nm
10x 100x
0.04% 0.30%
0.01% 0.13%
0.03% 0.12%
0.07% 0.17%
0.02% 0.13%
Table 1: VVG Variations With Bigger Resistance
2) Experimental Results of Gate Level VVG Model
To verify our model at the gate level, we conduct experiments on
a 8-input AND gate in 32nm technology. This gate consists of a
2-input NAND gate, two 3-input NAND gates and a 3-input NOR
gate. Given a certain input vector as shown in Figure 9, this gate
includes all the serial and parallel structures that we have discussed
in Section 2.3.
VDD
A
B
1
A
1
0
B
0
0
C
C
OUTPUT
0
0
A
0
B
C
VIRTUAL GROUND
FOOTER
Figure 9: 8-input AND Gate Topology
According to our method, the leakage current of the gate is modeled as a VVG-controlled current source. So in the experiment we
set VVG to 7 different values and measure the leakage current of
the gate. The error between our leakage current model and HSPICE
results is shown in Table 2 and Figure 10. The error is negligible
when the VVG level is low (V V G < 500mV ). The error percentage is higher when the VVG level is high (V V G > 500mV ).
However when VVG is high, since the absolute value of the leakage current is very small, the error has minor impact on the dynamic
VVG value.
VVG(mV)
. Model Current(nA)
Sim. Current(nA)
0
56.9
56.9
100
24.7
23.9
200 300
10.7 4.6
10.2 4.5
400
2.0
2.2
500
0.9
1.2
600
0.4
0.7
Table 2: Correlation of Gate Leakage Current Model on AND8
60
Leakage Current of AND8 (nA)
regions and model the equivalent capacitance in each region. The
dynamic VVG model in Equations 19 is then revised as:
50
40
30
20
Model
Experiment
10
0
0
0.1
0.2
0.3
0.4
0.5
Virtual Ground Voltage (V)
0.6
0.7
Figure 10: Correlation of Gate Leakage Current Model on
AND8
Next, we apply ground gating to the 8-input AND gate and simulate its dynamic VVG values. As shown in Figure 11, 18 sampling
points are taken from the simulated VVG curve of the gate, starting
from the moment when the ground is gated to the point after the
VVG reaches its steady value. Then the VVG values of these 18
sampling points are compared with the model estimations. Table
3 shows the comparisons of the first 8 sampling points, since they
have the largest VVG variations. It shows that the gate level VVG
model has on the average 0.7%, and a maximum of 2.1% error for
the 8-input AND gate.
Sleep Time(ns)
10
20
30
40
60
80 120
Model VVG(mV) 92 140 172 196 228 247 270
Sim. VVG(mV) 94 141 172 196 227 246 269
Error
2.1% 1.3% 0.0% 0.2% 0.5% 0.6% 0.8%
160
282
280
0.8%
Table 3: Correlation of Gate Level VVG Model on 32nm AND8
Virtual Ground Voltage (mV)
350
300
250
600
500
400
300
200
Model
100
Experiment
0
200
0
50
100
150
Time After Ground Gated (ns)
200
150
Model
Experiment
100
50
0
100
200
300
Time After Ground Gated (ns)
400
Figure 11: Correlation of Gate Level VVG Model on 32nm
AND8
3) Overall Correlation of Circuit Level VVG Model
To verify the circuit level dynamic VVG model, we applied ground
gating to the ISCAS85 benchmark circuits and compare their VVG
simulation results with our model estimations. There are 30 sets
of comparisons for the 10 ISCAS85 benchmark circuits in 3 technologies. For each comparison, 18 sampling points are taken from
the simulated VVG curve of the circuit (Figure 12). The average
and worst case error of these 18 sampling points are given in Table 4. The model has less than 1% average error when compared
with HSPICE results in all three technologies. The maximum error is 3.59%. Figure 12 illustrates a typical case correlation for the
largest benchmark circuit C7552 in 32nm technology.
BM.
C432
C499
C880
C1355
. C1908
C2670
C3540
C5315
C6288
C7552
Overall
Gate
Cnts.
160
202
383
546
880
1193
1669
2307
2406
3521
32nm
Max. Avg.
1.23% 1.07%
3.03% 1.25%
1.93% 0.76%
0.98% 0.64%
0.59% 0.19%
1.74% 0.57%
1.43% 0.60%
2.14% 0.63%
0.82% 0.24%
1.54% 0.54%
3.03% 0.65%
45nm
Max. Avg.
1.01% 0.75%
2.70% 1.24%
0.89% 0.53%
1.62% 0.76%
1.28% 0.28%
0.67% 0.44%
0.75% 0.51%
0.67% 0.46%
0.83% 0.20%
0.64% 0.37%
2.70% 0.55%
65nm
Max. Avg.
2.52% 1.50%
1.97% 1.00%
3.59% 1.08%
3.45% 2.00%
3.31% 1.30%
2.02% 0.55%
1.80% 0.43%
2.12% 0.54%
3.51% 0.94%
1.74% 0.38%
3.59% 0.97%
Table 4: Error of Circuit Level VVG Model
The model is also computationally efficient. The CAD tool can
perform estimations on the largest benchmark circuit C7552 in 15
seconds, while HSPICE simulation takes 24 minutes. The speedup
in this case is 100 times. It can have even greater speedup on larger
circuits.
4.
700
Virtual Ground Voltage (mV)
.
CONCLUSION
In this paper, we emphasize the dynamic VVG estimation as the
key to make critical design trade-offs for future power gating applications, such as active leakage power reduction or fine-grained
power gating. For a given circuit, a model has been developed to
estimate the circuit VVG value at any time after its ground is gated.
This model can also give estimations on the leakage energy saving
as a function of time.
Figure 12: Correlation of Circuit Level VVG Model on 32nm
C7522
Experiment results demonstrate that in 32nm, 45nm and 65nm
technologies, the dynamic VVG model has on the average less than
1%, and a maximum of 3.59% error compared with HSPICE. The
model has been implemented by a CAD tool. The tool is able
to perform fast estimations with a 100× speedup compared with
HSPICE on the largest ISCAS85 benchmark circuit.
5. ACKNOWLEDGMENTS
This work was founded in part by National Science Foundation
of USA under grant CCF-0541103.
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