University of Bolton
UBIR: University of Bolton Institutional Repository
Research and Innovation Conference 2010
University of Bolton Conferences
2010
Simulation of energy dissipation for adiabatic
switching of CMOS based reversible logic circuits.
Thomas J. Hogan
Pathway Systems Cambridge
Gerard Edwards
University of Bolton, G.Edwards@bolton.ac.uk
Digital Commons Citation
Hogan, Thomas J. and Edwards, Gerard. "Simulation of energy dissipation for adiabatic switching of CMOS based reversible logic
circuits.." (2010). Research and Innovation Conference 2010. Paper 2.
http://digitalcommons.bolton.ac.uk/ri_2010/2
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SIMULATION OF ENERGY DISSIPATION FOR ADIABATIC SWITCHING OF
CMOS BASED REVERSIBLE LOGIC CIRCUITS
Thomas J Hogan1 and Gerard Edwards2
1
Pathway Systems Cambridge, CB3 8JQ UK. Tel. No. 01954 267166 thogan@pathwaysystems.co.uk
Department of Built Environment and Engineering, University of Bolton, Bolton, BL3 5AB, UK, ge3@bolton.ac.uk
2
Comparison of power dissipation characteristics for a range of reversible logic elements when operated with conventional
and adiabatic logic switching are investigated by SPICE simulation techniques. Results show reduced power dissipation
when using adiabatic logic switching but that this deviates from theoretical expectations due to the finite threshold voltage
of the pMOS and nMOS devices.
1
The family of logic functions was implemented using
hierarchical design structures based on a custom
transmission gate (TG) cell. The transmission gate is formed
from a single nMOS and pMOS transistor connected in
parallel with each gate driven from a complimentary control
signal [14]. All functions are dual rail (complimentary) logic
where -2.5 volts represents logic 0 and +2.5 volts represents
logic1. This class of logic implementation has the advantage
of requiring no power supplies. All energy into and out of
the gate is through the signal lines. The power dissipation
characteristics of this family of reversible logic gates and
T
Va
+2.5
Vb
Volts
Over the last few decades, there has been a continuous
process of integrated circuit device technology
development targeted at increasing circuit density by
decreasing feature size. At the same time operating voltage
has been reduced to keep power dissipation density within
acceptable limits. This technique of operating voltage
reduction has a lower limit due to circuit noise margins, so
researchers are actively looking for alternative methods to
sustain Moore’s Law. Landauer [1] stated that the loss of
information associated with a logically irreversible
operation, is accompanied by an increase in the entropy of
the environment and accompanying heat dissipation of
kTln2 for each bit of information lost (Landauer’s
Principle). Charles Bennett [2] discovered that any
irreversible computation could be transferred into a
reversible computation by accumulating a historical record
of all the information that would normally be discarded.
After which the procedure is reversed, disposing of the
historical record and leaving only the result and the original
data. Reversible logic gates have been devised by a number
of people namely Fredkin and Toffoli [3] with conservative
logic and Feynman [4] with controlled gates. These logic
gates form universal primitives, from which any other logic
gate or circuit can be constructed. More recently methods
for synthesis of reversible logic gates have been reported
[5]
.It is with this in mind, that two possible methods of
decreasing dynamic power dissipation, conventional and
adiabatic addressing, are investigated by means of
simulation techniques. Information loss contributes to the
overall dissipation of computer circuitry. However its
contribution is far outweighed by that generated by other
forms of switching dissipation. When the input conditions
on a logic gate change state, with the conventional CMOS
paradigm [6], power dissipation occurs due to the need to
charge or discharge the capacitances associated with the
circuit nodes. In the adiabatic logic switching paradigm the
signal is applied as a ramp rather than as a step function
Athos[7], Alioto[8], DeVos[9]. The adiabatic energy loss is
inversely proportional to the rise and fall times of the
switching signal, that is the slower the rise and/or fall times
the lower the energy dissipation. With adiabatic computing,
a penalty of slower gate switching time accompanies the
reduction in power dissipation. Here we report on the use
of SPICE simulation techniques to characterize the power
dissipation of a range of reversible circuits when operated
under conventional and adiabatic logic switching regimes.
When undertaking the investigation no consideration has
been given to the dissipation that may occur in circuits that
generate the switching waveforms or to energy recovery, as
this has been previously reported [10][11][12][13]. Our focus is
on the performance of the adiabatically switched reversible
logic circuits themselves.
t
0
Vc
-2.5
t midpoint
Fig.1 Adiabatic logic switching input voltage waveforms Vb
moves from – 2.5 to + 2.5 i.e. changing logic state 0 -> 1. Va
moves from + 2.5 to 0 and back to + 2.5 i.e. maintaining logic state
1.Vc moves from – 2.5 to 0 and back to – 2.5 i.e. maintaining logic
state 0
arithmetic functions were investigated by simulation under
conventional and adiabatic switching (Fig.1) regimes for a
range of rise times (τ).
The logic schematics were produced using Cadence IC
simulation tools Assura/Virtuosa and the net lists generated
from these provided the input to spectreS (SPICE) circuit
simulation software. Input voltage waveforms were
simulated using parameterized piecewise linear multiphase
voltage sources. The input signal current against the time
dependant input voltage were obtained by Spice simulation
for a range of rise times (1ps > τ < 4µs). Energy dissipation
for each of the circuits is calculated by the integration over
time of the voltage current product, for each of the circuit
signal inputs. The time interval for integration is over the
period of one complete clock cycle, as defined in Eq. (3).
N T
EDiss = ∑ ∫ Vn I n dt
1
(3)
0
where n is a particular input lead from 1 to N, N is the total
number of leads, T is the period of one clock cycle, Vn is the
voltage waveform on input n and In is the current waveform
of input n. Energy dissipation calculations are obtained by
post processing SPICE simulation data using Cadence
Analogue Artist functions.
The energy dissipation for the Controlled Not (CN) Gate
was obtained for two different input state transitions for each
of the two logic switching regimes. Each simulation consists
of keeping the logic state of one input constant while
changing the logic state of the other to its inverse then
returning it to its original state. (ie x ->_x -> x) . (Table 1).
2
SIMULATION
NUMBER
SWITCHING
CONDITION
A
B
C
1 (CN)
2 (CN)
3 (CN)
4 (CN)
5 (CCN)
6 (CCN)
7 (CCN)
8 (CCN)
9 (CCN)
10 (CCN)
Conventional
Conventional
Adiabatic
Adiabatic
Conventional
Conventional
Conventional
Adiabatic
Adiabatic
Adiabatic
0
0->1->0
0
0->1->0
1
0->1->0
0->1->0
1
0->1->0
0->1->0
0->1->0
0
0->1->0
0
0
1
0
0
1
0
NA
NA
NA
NA
0->1->0
1
1
0->1->0
1
1
INPUT CONDITIONS
conduction path dissipation. Simulations were also carried
out for reverse state transitions (_x ->x -> _x), energy
dissipation was nearly identical to those already reported,
reflecting the symmetrical nature of the logic topology.
Irrespective of the input state transition, adiabatic logic
switching results in energy dissipation decreasing for
increasing τ from 2.45pJ at τ = 1ps down to 10fJ at τ =
500ns, above 500ns energy dissipation stays constant at
approximately 10fJ (Fig.3).
Table1 Simulation test conditions for CN and CCN gates
E N E R G Y D IS S IP A T IO N F O R C N G A T E
A D IA B A T IC A D D R E S S IN G
S i m u la t i o n3
S im u lat io n 4
2 .5 1 E -12
2 .0 1 E -12
1 .5 1 E -12
1 .0 1 E -12
4 . 00 E -0 6
2 . 0 0 E -0 6
1 . 0 0 E -0 6
5 .0 0 E -0 7
1 . 0 0 E -0 7
5 .0 0 E -0 8
1 .0 0 E -0 8
5 . 0 0 E -0 9
1 . 0 0 E -09
5 .0 0 E -1 0
1 .0 0 E -1 0
5 . 0 0 E -1 1
1 . 0 0 E -1 1
1 .0 0 E -14
5 . 0 0E -1 2
5 .1 0 E -13
1 . 0 0 E -1 2
E N E R G Y D I S S I P A T IO N (JO U L E S )
The energy dissipation (Fig.2) displays two distinct
characteristics for conventional logic switching. These are a
function of the input state transition, attributable to switching
path differences. Input transitions which result in the
transmission gates not changing conduction state
(Simulation1) result in energy dissipation decreasing with
increasing τ. For this input transition, transmission gates
stay in the same conduction state and the input signals stay
connected to the same signal paths. At a first approximation,
energy dissipation is due solely to the charging/discharging
of node capacitances, resulting in a maximum value of 2.5pJ
at τ = 1pS and a minimum value of 37fJ at τ = 4µS. For
input state transitions that result in changes to conduction
state (Simulation2), dissipation increases with increasing τ
for τ > 5ns. Resulting in a minimum energy dissipation of
1.9pJ at τ =1pS and a maximum value of 2nJ at τ = 4µS. For
part of the rise/fall time (τ) of an input transition both
R I S E / F A L L T I M E (S E C O N D S )
Fig.3 CN Gate energy dissipation versus switching time for
adiabatic addressing.
Demonstrating that energy dissipation dependency on input
state transition has been removed. This has been achieved
by switching off the transmission gates before changing to
the next logic state, ensuring that conduction paths across the
E N E R G Y D IS S IP A T IO N F O R C N G A T E
input signals do not occur. There is however the limiting
C O N V E N T IO N A L S W IT C H IN G
situation where increases in τ do not result in a
corresponding reduction in dissipation. Examination of the
input and output voltage waveforms (Fig.4) show that for
linear ramp input signals the output signal consists of a step
change of 1.2 volts followed by a linear ramp. The finite
threshold voltage of the transmission gate results in the
circuit behaving in a non adiabatic manner during a portion
of the logic switching cycle. The input current waveform
(Fig.5) demonstrates this. There are two constant current
periods (adiabatic) with a superimposed current spike (nonadiabatic) coincident with the time the transmission gate
starts to conduct. This transient current is similar in character
Fig.2 CN Gate energy dissipation versus switching time for to that obtained when charging a capacitor from a step
conventional logic switching.
voltage change (non-adiabatically) and is responsible for the
lower limit that can be achieved for the energy dissipation.
E N E R G Y D IS S I P A T IO N (JO U L E S )
S i m u la t i o n 1
S im u l a t io n 2
1 . 0 0 E -0 7
1 . 0 0 E -0 8
1 . 0 0 E -0 9
1 . 0 0 E -1 0
1 . 0 0 E -1 1
1 . 0 0 E -1 2
4 . 0 0 E -0 6
2 . 0 0 E -0 6
1 . 0 0 E -0 6
5 . 0 0 E -0 7
1 . 0 0 E -0 7
5 . 0 0 E -0 8
1 . 0 0 E -0 8
5 . 0 0 E -0 9
1 . 0 0 E -0 9
5 . 0 0 E -1 0
1 . 0 0 E -1 0
5 . 0 0 E -1 1
1 . 0 0 E -1 1
5 . 0 0 E -1 2
1 . 0 0 E -1 4
1 . 0 0 E -1 2
1 . 0 0 E -1 3
R I S E / F A L L T I M E (S E C O N D S )
sets of transmission gates are partially conducting, resulting
in an impedance ( 2xRDS) appearing across complimentary
input signal pairs. The time this conduction path is present is
approximately proportional to τ. In this case, there are two
significant energy dissipation components, node capacitance
charging and inter signal conduction via the transmission
gates. As τ -> 0, energy dissipation is very similar for both
cases, reflecting the minimal contribution of conduction path
dissipation. As τ increases, the difference between energy
dissipation increases, reflecting the increased dominance of
3
E N E R G Y D IS S IP A T IO N F O R C C N G A T E
C O N V E N T IO N A L S W IT C H IN G
S im ula ti o n5
S im ula ti o n6
S im ula tio n7
ENERGY DISSIPATION (JOULES)
1 .0 0 E -0 8
1 .0 0 E -0 9
1 .0 0 E -1 0
1 .0 0 E -1 1
1 .0 0 E -1 2
1 .0 0 E -1 3
Fig.4 CN Gate Spice Simulation showing input output voltage
waveforms. [Triangular waveform – Input B, ramp waveform –
Output Q] . Highlights the dead zone where output does not react to
changes in the input due to finite threshold voltage of pMos and
nMOS transistors.
A similar methodology to characterise energy dissipation
for the different signal routing combinations of the CCN gate
was used. The energy dissipation characteristics for the CCN
gate (see Fig.6), when driven with conventional logic
switching are similar to that obtained for the CN gate. For
4.00E-06
2.00E-06
1.00E-06
5.00E-07
1.00E-07
5.00E-08
1.00E-08
5.00E-09
1.00E-09
5.00E-10
1.00E-10
5.00E-11
1.00E-11
5.00E-12
1.00E-12
1 .0 0 E -1 4
R IS E /F AL L T IM E ( S E C O N D S )
Fig.6 CCN gate energy dissipation versus switching time for
conventional logic switching.
Energy dissipation under adiabatic logic switching shows
similar characteristics against τ for all three simulation
conditions (see Fig.7). Simulation 8 (5.51pJ at τ = 1ps
decreasing to 27fJ at τ = 4µs ), simulation 9 ( 5.11pJ at τ
=1ps decreasing to 27fJ at τ = 4µs ) and simulation10 (1.17pJ
at τ = 1ps decreasing to 59fJ at τ = 4µs). In all three cases,
energy dissipation decreases with increasing τ until τ in the
range 100ns >τ<500ns at which energy dissipation limits.
E N E R G Y D IS S IP A T IO N F O R C C N G A T E
A D IA B A T IC A D D R E S S IN G
ENERGY DISSIPATION (JOULES)
S im ula tio n8
S im ula tio n9
S im ula tio n1 0
5 .0 1 E -1 2
4 .0 1 E -1 2
3 .0 1 E -1 2
2 .0 1 E -1 2
1 .0 1 E -1 2
4.00E-06
2.00E-06
1.00E-06
5.00E-07
1.00E-07
5.00E-08
1.00E-08
5.00E-09
1.00E-09
5.00E-10
1.00E-10
5.00E-11
1.00E-11
5.00E-12
1.00E-12
1 .0 0 E -1 4
R IS E /F AL L T IM E (S E C O N D S )
Fig.5 CN Gate Spice Simulation showing applied input voltages
and driven input current waveforms versus time in us. [Trace 1 Fig.7 CCN gate energy dissipation versus switching time for
(Uppermost) Input B current waveform, Trace 2 Input A
adiabatic addressing
current waveform, Trace 3 Input B voltage waveform Trace
4Input A voltage waveform.]
Examination of the input signal voltages and currents (Fig.8)
simulations 5 and 7 the energy dissipation was 5.47pJ at τ =
1ps, 86fJ at τ = 4µs and 6.42pJ at τ = 1ps, 419fJ at τ = 4µs
respectively. Both exhibited decreasing energy dissipation
with increasing τ. Energy dissipation for simulation 6 was
4.63pJ at τ = 1ps and 1.81nJ at τ = 4µs. For τ <10ns the
energy dissipation decreased for increasing τ. While for τ >
10ns, energy dissipation increased with decreasing τ (see
Fig.6). These differences are due to changes in the input to
output signal routing resulting in partial conducting TGs
(2xRDS) appearing across the controlled inputs and producing
conduction path currents.
shows similar characteristics to those for the CN gate. The
current transient on the C input is far larger than those present
on the A and B inputs. Due to the C input being disconnected
from, and reconnected to the output node capacitance. This
produces a potential difference across the TG at switch on
and results in a transient current flowing until the voltage
across the TG reduces to zero. The A and B inputs are
controlling inputs, their associated signal path node
capacitances are much smaller than those associated with the
controlled input (C). This results in much transient
currents and in a smaller
4
an approximate 1/τ relationship with energy dissipation
exists. The effect is due to signals containing uncontrolled
voltage steps now being used to control downstream circuit
elements. This results in these elements being driven non
adiabatically. An additional contribution is due to the
increasing capacitive load of the signal paths, resulting in
increased dissipation during the uncontrolled portion of the
switching transition. With increasing logic complexity
(depth) a situation where the 1/τ relationship disappears
altogether could be reached. One method of overcoming this
is the use of a buffer or repeater to limit the logic depth that
signal paths are required to drive.
Fig.8 CCN gate input voltages and currents versus time in s.
Trace 1 (Upper) Input C current waveform, Trace 2 Input B
current waveform, Trace 3 Input A current waveform, Trace 4
Input C voltage waveform, Trace 5 Input B voltage waveform, REFERENCES
Trace 6 Input A voltage waveform.
energy dissipation contribution. The overall lower
dissipation of simulation 10 is attributable to the controlled
output having the same final logic state as its previous state.
This results in a reduced voltage step being developed across
its associated TG. With correspondingly reduced current
transient and associated energy dissipation. It was also
observed that the characteristics of the complementary
signals were identical, reflecting the symmetry of the
circuits.
Transmission gate logic provides an efficient and elegant
method of realizing physically and reversible logic elements,
requiring only four nMOS and four pMOS transistors to
implement a CN gate. One characteristic of this circuit
configuration is increasing crowbar dissipation as the input
signal rise/fall times are increased due to the presence of
transient conduction paths across complimentary input
signal pairs. The effects of this are minimised by moving all
input signals to 0 volts before moving them to their final
voltage state (adiabatic addressing).
[1] R.Landauer, 1961 IBM Journal of Research and Development 5 183.
[2] Charles H. Bennett, 1973, IBM Journal of Research and Development 17
525.
[3] E.Fredkin T.Toffoli, 1982 Int. J. Th. Phys 21 219.
[4] Richard P. Feynman Lectures on Computation ( Penguin 1996)
[5]MingGu et al 2005 On synthesis of 3 x 3 reversible logic functions Int. J.
Comp. Maths. 82 4 38
[6 N. Weste K. Eshraghian, Principles of CMOS Design (New York
Addision-Wesley 1993).
[7] William C Athas et al 1994 IEEE Trans. V.L.S.I. Integ. 2 398.
[8] Massimo Alioto Gaetano Palumbo 2000 IEEE Trans. Ccts. Sys-I, Thry.
Apps. 47 9 .
[9] Alexis De Vos 1999 Prog. Quantum Elects. 23 1
[10] Jincan Chen 2001 Int.J.of Elects 20 88 145
[11] L.Vargo 2001 IEEE Int. Con. Proc. ASIC/SOC 14 208
[12] Pui-Tak So et al 2005 IEEE Int. Sym. Ccts. Sys. 3 2152
[13] Guoqiang Hang 2005. Proceedings of the 2005 Conference on Asia
South Pacific Design Automation 803.
[14] Alexis De Vos 1999 Prog. Quant. Comp. 23 1
Simulations reported upon in this letter demonstrate that
adiabatic addressing when applied to transmission gate logic
provides a method of decreasing the energy dissipation for
certain operating conditions compared to conventional logic
switching. This confirms previously reported experimental
results reported by DeVos [14]. Results also demonstrate that
there is a minimum limit beyond which no further
improvement in energy dissipation reduction can be
achieved, due to the finite threshold voltage of the MOS
transistors. This finite threshold voltage results in
uncontrolled ≈1.2 volt steps (25% total logic swing)
occurring on the output node of the transmission gate
switches. This results in non adiabatic charging of the node
capacitance for part of the logic transition. This component
of energy dissipation could be reduced by selecting a MOS
technology with a lower threshold voltage.
Other simulations performed as part of this investigation fon
the reversible half adder, full adder and ripple carrier adder
show a decreasing range of input signal rise/fall times where
5