400G-PSM4: Options for 500m Reach
Interconnects
Brian Welch
www.luxtera.com
Overview
• A comparison of three prospective solutions for 400G
interconnects up to 500m
− 2λx8x25GBaud-PAM4
− 2λx8x50GBaud-NRZ
− 1λx4x50GBaud-PAM4
• All prospective solutions use four fibers per direction
• Presentation compares cost, power, link budget, and
risk profiles of different solutions
IEEE 802.3bs 400Gbe Task Force July 2014
2
400G Design Options
• 2λx8x25GBaud-PAM4
– Two Wavelength WDM
– Eight Optical Lanes
– PAM4 Optical Encoding
• 2λx8x50GBaud-NRZ
– Two Wavelength WDM
– Eight Optical Lanes
– NRZ Optical Encoding
• 1λx4x50GBaud-PAM4
– Single Wavelength
– Four Optical Lanes
– PAM4 Optical Encoding
IEEE 802.3bs 400Gbe Task Force July 2014
3
λ2
λ1
2λx8x25GBaud-PAM4
8x50 Gbps
16x25 Gbps
Decoder
Decoder
Decoder
Decoder
Decoder
Decoder
Decoder
Decoder
IEEE 802.3bs 400Gbe Task Force July 2014
TIA
TIA
TIA
TIA
TIA
TIA
TIA
TIA
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
4x2λ DEMUX
I/O+DeMUX
I/O+DeMUX
I/O+DeMUX
I/O+DeMUX
I/O+DeMUX
I/O+DeMUX
I/O+DeMUX
I/O+DeMUX
4x2λ MUX
MZI
MZI
MZI
MZI
MZI
MZI
MZI
MZI
I/O+MUX
I/O+MUX
I/O+MUX
I/O+MUX
I/O+MUX
I/O+MUX
I/O+MUX
I/O+MUX
16x 25 Gbps
Max: 200G per Laser
4x100 Gbps
4
λ2
λ1
2λx8x50GBaud-NRZ
CDR
CDR
CDR
CDR
CDR
CDR
CDR
CDR
IEEE 802.3bs 400Gbe Task Force July 2014
8x50 Gbps
TIA
TIA
TIA
TIA
TIA
TIA
TIA
TIA
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
4x2λ DEMUX
I/O+DeMUX
I/O+DeMUX
I/O+DeMUX
I/O+DeMUX
I/O+DeMUX
I/O+DeMUX
I/O+DeMUX
I/O+DeMUX
8x50 Gbps
4x2λ MUX
MZI
MZI
MZI
MZI
MZI
MZI
MZI
MZI
I/O+MUX
I/O+MUX
I/O+MUX
I/O+MUX
I/O+MUX
I/O+MUX
I/O+MUX
I/O+MUX
16x 25 Gbps
Max: 200G per Laser
4x100 Gbps
5
1λx4x50GBaud-PAM4
λ
Max: 400G per Laser
I/O+MUX
MZI
I/O+MUX
MZI
I/O+MUX
MZI
I/O+MUX
MZI
16x 25 Gbps
8x50 Gbps
4x100 Gbps
I/O+DeMUX
Decoder
TIA
PIN
I/O+DeMUX
Decoder
TIA
PIN
I/O+DeMUX
Decoder
TIA
PIN
I/O+DeMUX
Decoder
TIA
PIN
IEEE 802.3bs 400Gbe Task Force July 2014
6
400G Design Options - Cost
2λx8x25GBaud-PAM4
2λx8x50GBaud-NRZ
1λx4x50GBaud-PAM4
Chipset Cost†
2λx8x25GBaud-PAM4
2λx8x50GBaud-NRZ
1λx4x50GBaud-PAM4
Chipset
5.95
5.82
3.92
Module Cost
2λx8x25GBaud-PAM4
2λx8x50GBaud-NRZ
1λx4x50GBaud-PAM4
@ 95% Yield
1.60
1.56
1.00
Using Methodologies Presented in welch_400_01_1113.pdf
† Chipset Costs Measured Relative to 100G-PSM4
IEEE 802.3bs 400Gbe Task Force July 2014
7
400G – Power
2λx8x25Gbaud- 2λx8x50Gbaud 1λx4x50GbaudPAM4
-NRZ
PAM4
CDAUI16 Electrical Interface (W)
3.0
3.0
3.0
PAM4 Encoder†
25G Optical Transmitters (W)
8x0.125 = 1
50G Optical Transmitters (W)
8x0.185 = 1.48 4x0.815 = 0.74
WDM2 MUX/DEMUX (W)
0.375
0.375
WDM2 Extra Light Source (W)
0.2
0.2
25G Optical Recevier (W)
8x0.05 = 0.4
50G Optical Receiver (W)
25GBaud-PAM4 Decoder (W)
8x0.075 = 0.60 4x0.075 = 0.30
8x0.250=2
50GBaud-PAM4 Decoder (W)
4x0.35=1.4
50GBaud-NRZ Retimer (W)
Total
8x0.2 = 1.6
7
7.25
5.4
† PAM4 encoding performed optical by MZI
IEEE 802.3bs 400Gbe Task Force July 2014
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400G – Link Budget Penalties
2λx8x25Gbaud- 2λx8x50Gbaud 1λx4x50GbaudPAM4
-NRZ
PAM4
WDM MUX+DEMUX (dB)
4-5
4-5
0
50 Gbaud TIA Noise Penalty (dB)
0
1.5
1.5
PAM4 Encoding Penalty (dB)
4.8
0
4.8
MPI & RIN Penalty (dB)
1.2
0.4
1.2
Linearity Penalty (dB)
0.3
0
0.3
Total Penalty (dB)
10.3-11.3
5.9-6.9
7.8
Link Budget Penalties measured relative to 100G-PSM4
IEEE 802.3bs 400Gbe Task Force July 2014
9
Risk Profiles
Technology Risks
Design Risks
•
What technologies are needed to support
the different solutions?
•
How much design complexity is inherent
in the different solutions?
•
25GBaud solutions can use 28 nm CMOS
technologies
•
NRZ solutions will use the same basic
architecture as existing 100G solutions
–
•
50GBaud solutions likely to need 20 nm
(or below) CMOS technologies
–
•
Same as used for 100G solutions
–
•
16 nm may be most likely intercept node
–
PAM4 solutions will need new element vs.
existing 100G solutions
–
–
Technology risks are time dependent
Decrease as technologies mature
•
PAM4 decoder on optical receiver
Several suitable architectures, however
power/performance tradeoffs may take
time
WDM solutions more complex than
parallel 100G solutions
–
IEEE 802.3bs 400Gbe Task Force July 2014
Assuming more advanced CMOS node
design risks should be moderate
Optical control system requirements
10
400G-PSM4 Scorecard
2λx8x25Gbaud- 2λx8x50Gbaud 1λx4x50GbaudPAM4
-NRZ
PAM4
Module Cost
1.60
1.56
1.00
Module Power
7
7.25
5.4
Link Budget Penalty
10.3-11.3
5.9-6.9
7.8
Max Throughput per Laser (Gbps) 200
200
400
Technology Risk Profile
Low
Moderate
Moderate
Design Risk Profile
High
Low
Moderate
Backward Compatibility (to 100G- Challenging
PSM4)
Challenging
Yes
Forward Scalability Limit
50G Serial
50G Serial
100G Serial
Breakout Potential (to 4x100G)
High
High
High
IEEE 802.3bs 400Gbe Task Force July 2014
11
A PAM4 ‘Anti-Penalty’
Jitter Composition
www.luxtera.com
Jitter Analyses - DJ
PAM4
IEEE 802.3bs 400Gbe Task Force July 2014
PAM2 (Inner Eye)
13
Jitter Analyses - TJ
PAM4
IEEE 802.3bs 400Gbe Task Force July 2014
PAM2 (Inner Eye)
14
Jitter Analyses – Deltas (Comparative Analyses)
• PAM4 TJ = 12 ps
• PAM4 DJ = 8.2 PS
• Therefore RJ = 3.8 ps
• PAM2 TJ = 5.97 ps
• PAM2 DJ = 0.24 ps
• Therefore RJ = 5.73 ps
• RJ addition is sub-linear in PAM4
− Non Dual Dirac Jitter Composition
IEEE 802.3bs 400Gbe Task Force July 2014
15
0.6
0.25
0.5
0.2
0.4
Random
Jitter
0.3
0.2
0.15
0.1
9.5
8
6.5
5
3.5
2
0.5
-1
-2.5
-4
0
-5.5
0
-7
0.05
-8.5
0.1
-10
Dual Dirac
Jitter Analysis – Dual Dirac vs. PAM4
-15
0.5
-10
-5
0
5
10
15
0.4
Deterministic
Jitter
0.3
Total
Jitter
0.2
0.1
-15
0.6
-10
-5
0
0
5
10
15
0.25
0.2
0.4
0.15
0.3
IEEE 802.3bs 400Gbe Task Force July 2014
9.5
8
6.5
5
3.5
2
0.5
-1
0
-2.5
0
-4
0.05
-5.5
0.1
-7
0.1
-8.5
0.2
-10
PAM4
0.5
-15
-10
-5
0
5
10
15
16
Jitter Analysis – Dual Dirac vs. PAM4
0.25
PAM4
0.2
Probability
Δσ
Dual Dirac
0.15
0.1
0.05
-10
-8
-6
-4
-2
0
0
2
4
6
8
10
Eye Location
PAM4 has significantly lower jitter probabilities around the outer DJ impulses than a Dual
Dirac model would predict
IEEE 802.3bs 400Gbe Task Force July 2014
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Summary
• Several Options Exist for 400G-PSM4 solutions
− 2λx8x25Gbaud-PAM4
− 2λx8x50Gbaud-NRZ
− 1λx4x100Gbaud-PAM4
• Each solution has strengths and weaknesses
− 1λx4x50Gbaud-PAM4 seems to have the most positives
o Lowest potential power and cost
o Higher technology risk
• PAM4 ‘penalties’ may be less significant than anticipated
− ‘Anti-penalty’ seems to exist due to non Dual Dirac jitter
o May be difficult to model empirically
IEEE 802.3bs 400Gbe Task Force July 2014
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Thank You
www.luxtera.com