EE 221 Midterm Solutions
October 30, 2002
1)
Figure 1
a) Determine and sketch the Thevenin’s equivalent circuit for the output terminals A and B.
Solution
First one should realize that R3, R5, and R7 along with I2 and V2 have no bearing on the final
solution. Thus the circuit to determine RTH is:
RTH = R2 + R4//R6 = 300Ω
Circuit to determine VTH is:
VA = I1 x R2 = 50 mA x 260 Ω = 13 V and
VB = V1
1
R4
120Ω
= 15V
= 10V
R4 + R6
120Ω + 60Ω
EE 221 Midterm Solutions
October 30, 2002
VAB = VTH = VA – VB = 13 V – 10 V = 3 V
Thevenin Equivalent Circuit.
b) At what value of load resistance will 600 µA flow through the load?
600µA =
VTH
RTH + RLoad
RLoad = _4.7 kΩ_
V
3V
∴ RLoad = TH − RTH =
− 300Ω = 4.7 kΩ
600µA
600 µA
c) At what value of load resistance is maximum power transferred?
RLoad = __300 Ω__
Maximum Power is transferred when RLoad = RTH = 300 Ω
d) What would be the minimum load resistance if this Thevenin’s equivalent circuit was to be a
stiff voltage supply?
RLoad(min) = ___30 kΩ__
From the definition of a stiff supply! RLoad(min) = 100 x RS. In this case RS is the Thevenin
resistance (RTH). Hence RLoad(min) = 100 x 300 Ω = 30 kΩ
e) What is the Norton’s equivalent circuit?
(Provide a circuit sketch as well)
V
3V
RN = RTH = 300 Ω and I N = TH =
= 10mA
RTH 300Ω
Norton Equivalent
Circuit.
2
EE 221 Midterm Solutions
October 30, 2002
2)
(Use the second approximation of the diode!)
Figure 2
NOTE: There is an error on the diagram, both D1 and D2 should be flipped so that the
anode is connected to ground. With the above configuration the output would be zero as
there is no ground connection for current flow.
a) What is the peak or maximum voltage across the load?
VLoad = __20 V_
For a primary transformer voltage of 120 Vac gives a secondary voltage of 20 Vac means that
120Vac
= 6 . Thus for a primary voltage of 90.8 Vac the secondary
the transformer turns ratio is,
20Vac
90.8Vac
= 15.133Vac = 15.133Vac × 2 ≅ 21.4VP
voltage is
6
Realizing that this is a bridge rectifier and the fact that we are using the second approximation of
the diode gives a load voltage of 21.4 V – 1.4 V = 20 V.
b) What is the peak to peak ripple voltage at the load?
Vripple = __0.250 VP-P__
VLoad
= 0.2 A and since this is a bridge rectifier circuit as well means that the rectified
RLoad
frequency is double the input frequency of 60 Hz. Hence the time between charging for the
1
capacitor is
= 8. 3 m sec
120 Hz
So to find the change in charge is as follows; ∆Q = 0.2 A × 8. 3 m sec = 1. 6 mC
I Load (max) =
Capacitance =
∆Q
∆Q 1. 6 mC
∴ ∆V =
=
= 249.9mVP − P ≅ 0.250VP − P
6.67mF
∆V
C
3
EE 221 Midterm Solutions
October 30, 2002
4
VB With Filter Cap.
VB Without Filter Cap.
VA
-22
-20
-18
-16
-14
-12
-10
-8
-6
-4
-2 0
0
4
6
8
10
12
14
16
18
20
2
V o lta g e
22
30
60
21.4 V
Vripple ~ 0.250 Vp-p
90 120 150 180 210 240 270 300 330 360 390 420 450 480 510 540 570 600 630 660 690 720
)
c) What rectifier configuration is this supply? Bridge Rectifier (well supposed to be
d) Using the graph on the next page, sketch the waveform at point ‘A’. Also on the same graph
sketch the resulting waveform at point ‘B’ both with and without the capacitor in circuit.
(You must indicate which waveform is which along with voltage levels.)
Please try to be neat! A sloppy diagram may lead to a misinterpretation and lost marks.
EE 221 Midterm Solutions
October 30, 2002
3)
(Use the second approximation of the diode!)
Sketch the waveform at each terminal, A, B, C, and D on the supplied graphs.
Please try to be neat! A sloppy diagram may lead to a misinterpretation and lost marks.
Figure 3
Circuit break down:
D1 and C3 = Peak Detector 1. Sets up a bias for Clamper 1.
C2 and D4 = Clamper 1.
D3 and C5 = Peak Detector 2. Sets up a bias for Clamper 2.
C1 and D2 = Clamper 2.
D5 and C4 = Peak Detector 3.
5
EE 221 Midterm Solutions
October 30, 2002
Question 3 Continued
2
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
-0.1 0
-0.2
-0.3
-0.4
-0.5
-0.6
-0.7
-0.8
-0.9
-1
-1.1
-1.2
-1.3
-1.4
-1.5
-1.6
-1.7
-1.8
-1.9
-2
30
60
90
120 150 180 210 240 270 300 330 360 390 420 450 480 510 540 570 600 630 660 690 720
Graph 1 for VA
3
2.8
2.6
2.4
2.2
2
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
-0.2 0
-0.4
-0.6
-0.8
-1
-1.2
-1.4
-1.6
-1.8
-2
-2.2
-2.4
-2.6
-2.8
-3
30
60
90
Vs
VA
120 150 180 210 240 270 300 330 360 390 420 450 480 510 540 570 600 630 660 690 720
Graph 2 for VB
Vs
6
VB
EE 221 Midterm Solutions
October 30, 2002
Question 3 Continued
3
2.8
2.6
2.4
2.2
2
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
-0.2 0
-0.4
-0.6
-0.8
-1
-1.2
-1.4
-1.6
-1.8
-2
-2.2
-2.4
-2.6
-2.8
-3
-0.7 V
0.9 V
30
60
90
120 150 180 210 240 270 300 330 360 390 420 450 480 510 540 570 600 630 660 690 720
Graph 3 for VC
3
2.8
2.6
2.4
2.2
2
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
-0.2 0
-0.4
-0.6
-0.8
-1
-1.2
-1.4
-1.6
-1.8
-2
-2.2
-2.4
-2.6
-2.8
-3
Vs
VB
VC
1.5 V
30
60
90
120 150 180 210 240 270 300 330 360 390 420 450 480 510 540 570 600 630 660 690 720
Graph 4 for VD
Vs
7
VD
EE 221 Midterm Solutions
October 30, 2002
4)
(Use the second approximation of the diode!)
With the given Vin sketch Vout on the same graph.
Please try to be neat! A sloppy diagram may lead to a misinterpretation and lost marks.
Because there are supplies attached means that the
diodes will have a forward biased region for an
input waveform. To determine what this region is
and how the output will look is as follows. First
let’s determine a relationship between Vin and
Vout. This can be done by choosing an
intermediate point such as V1.
Vout = V1 + 0.7 V and V1 = Vin – 0.7 V
Vout = Vin – 0.7 V +0.7 V
But this is not for all cases of Vin! The upper end
will be limited by the +4 V supply. In other words
for an input signal greater than 4 V D2 will be
reversed biased. To determine the lower limit we
have to find what V1 is when no input signal is
applied. In this condition current will flow from
the +4 V supply through R2, D2 and R1 to the –2 V
supply.
Figure 4
4V − 0.7V − (−2V )
I=
= 2.65mA
V1 = IR1 − 2V = 0.65V
R1 + R2
But we are interested in Vout = V1 + 0.7 V = 1.35 V therefore the lower limit is 1.35 V.
5.5
5
4.5
4
3.5
3
2.5
2
1.35 V
1.5
1
0.5
0
-0.5 0
30
60
90
120 150 180 210 240 270 300 330 360 390 420 450 480 510 540 570 600 630 660 690 720
-1
-1.5
-2
-2.5
-3
-3.5
-4
-4.5
-5
-5.5
Vin
8
Vout
EE 221 Midterm Solutions
October 30, 2002
5)
(Assume β = 100, VBE = 0.7 V and VCE(sat) = 0.3 V)
Figure 5
Find the following for the above transistor Schmitt trigger.
a) Determine the:
- Upper Trip Point? UTP = __10 V_
- Lower Trip Point? LTP = __4 V_
- Hysteresis Voltage? VH = __6 V_
UTP =
R4
1kΩ
VCC =
12V = 10V
1kΩ + 200Ω
R4 + R5
LTP =
R4
1kΩ
VCC =
12V = 4V
2kΩ + 1kΩ
R2 + R4
VH = UTP – LTP = 10V – 4V = 6V
9
EE 221 Midterm Solutions
October 30, 2002
Question 5 Continued
b) It is determined that a capacitor can be used in order to increase the switching time.
On the circuit diagram sketch where this capacitor is to be connected.
See CS on diagram (Figure 5)!
c) If this was a 621 pF capacitor, what would the maximum switching frequency be?
Fmax = _700 kHz_
C=
t re
1
tre =
2.3R
Fmax
⇒ Fmax =
R = R3//R2
1
R2 + R3
Fmax
∴C =
=
2.3R2 R3 2.3R2 R3 Fmax
R2 + R3
R2 + R3
2kΩ + 2kΩ
=
= 700.13kHz ≅ 700kHz
2.3R2 R3C 2.3 × 2kΩ × 2kΩ × 621 pF
d) List two advantages the transistor Schmitt Trigger has over a Basic Transistor Switch.
1) Different trip points for turn on (UTP) and turn off (LTP).
2) The output signal tracks the input signal. i.e. When the input is low the output is low
and when the input is high the output is high.
10
EE 221 Midterm Solutions
October 30, 2002
6)
(Assume β = 100, VBE = 0.7 V, VCE(sat) = 0.3 V, and at room temperature (300 oK))
Figure 6
a) Draw the DC load line and determine the Q point.
(Use the supplied transistor curve and label the X and Y axis’ values)
ICQ = _1.02 mA_
VCEQ = _5.42 V_
IC (mA)
1.41
1.40
1.20
1.02
1.00
Q
0.80
0.60
0.40
0.20
VCE (V)
2
4
6
5.42 V
8
10
12
11
14
16
18
20
EE 221 Midterm Solutions
October 30, 2002
Question 6 Continued
Page for Q point calculations
I C (max) =
VCC
20V
=
= 1.406mA ≅ 1.41mA
R3 + R4 + R5 12kΩ + 175Ω + 2.05kΩ
VBQ = VCC
R2
3kΩ
= 20V
= 3V
17 kΩ + 3kΩ
R1 + R2
V EQ = V BQ − V BE = 3V − 0.7V = 2.3V
I EQ =
I CQ =
VEQ
R4 + R5
=
2.3V
= 1.034mA
175Ω + 2.05kΩ
100
β
I EQ =
1.034mA = 1.024mA ≅ 1.02mA
100 + 1
β +1
VCQ = VCC − I CQ R3 = 20V − 1.024mA × 12kΩ = 7.72V
VCEQ = VCQ − V EQ = 7.72V − 2.3V = 5.42V
12
EE 221 Midterm Solutions
October 30, 2002
Question 6 Continued
b) Determine the input impedance (Zin), output impedance (Zout) and voltage gain (Av).
Zin = __2.26 kΩ__
Zout = _12 kΩ__
Av = __- 60 _
Z out = R3 = 12kΩ
Zin = R1//R2//β( r' e + R4)
r' e =
VT
I EQ
VT =
kT
0.02585V
= 0.02585V @ room temp. (300oK). ∴ r ' e =
≅ 25Ω
1.034mA
q
Zin = 17 kΩ//3 kΩ//100(25 Ω + 175 Ω) = 2.26 kΩ
AV =
− R3
− 12kΩ
=
= −60
r ' e + R4 25Ω + 175Ω
13
EE 221 Midterm Solutions
October 30, 2002
Question 6 Continued
c) Sketch the T and π transistor ac models for this circuit.
(Remember to label all components)
14
EE 221 Midterm Solutions
October 30, 2002
Question 6 Continued
d) Sketch the DC transistor model for this circuit.
(Remember to label all components)
e) Is this a stiff voltage divider bias?
(You must show proof to support your answer)
R1//R2 =
17 kΩ × 3kΩ
= 2.55kΩ
17 kΩ + 3kΩ
RE = R4 + R5 = 175Ω + 2.05kΩ = 2.225kΩ
Definition of a stiff voltage divider bias is R1//R2 < 0.01 β RE
Since β = 100 then 0.01 β = 1
and 2.55 kΩ is NOT less than 2.225 kΩ
Therefore this is NOT a stiff voltage divider bias.
15