Optimizing Voltage Selection
in Buck Converters
Understanding the impact of input voltage and
gate-drive voltage on MOSFET power losses
enables designers to achieve maximum efficiency
in the design of synchronous buck converters.
F
or several years, the dc-dc converters used to
power microprocessor core supplies in PCs
have been fed by a 12-V source. This voltage was
chosen to limit the current carried through the
harness of the ATX power supply as well as limit
the maximum current in the ATX output rectifiers. Although
this rationale makes sense with regard to the ATX supply, it
is contrary to the requirements of the core supply—typically
a synchronous buck converter—on the motherboard.
That’s because dynamic losses in the buck converter rise in
proportion to input voltage. Hence, the higher the input
voltage, the lower the buck converter’s efficiency.
Laboratory experiments show that both the input voltage
and the gate-drive voltage play a major role in power loss
in both the control or high-side (HS) MOSFET and the
synchronous rectifier or low-side (LS) MOSFET, although to
varying degrees. In this article, we will explore these effects
and formulate the governing equations, and investigate the
effects of different parameters on the converter’s power
losses.
A brief examination of the synchronous buck converter’s
By Alan Elbanhawy
Elbanhawy, Director, Computing and
Telecommunications Segments, Advanced Power Systems
Center, Fairchild Semiconductor, San Jose, Calif.
circuit reveals the dynamic losses may be calculated from:
1
PDYNAMIC = ID VIN FS (T
(TR +
+T
TF )
2
From this equation, we can see that this loss mechanism is
directly proportional to input voltage (VIN), the load current,
which is approximately the MOSFET drain current (ID), and
the switching frequency (FS). Therefore, the smaller any one
of these parameters, the smaller the dynamic losses. The
other major loss mechanism is conduction losses, which may
be calculated for the HS MOSFET from the equation:
PCONDUCTION = ID2 R DS(O
DS(ON)
DS
(ON)
N) ∆
where ∆ is the duty cycle:
∆≈
Output_Voltage
Input_Voltage
Efficiency (%)
The smaller the input voltage, the larger the conduction
losses for the same MOSFET on-resistance (RDS(ON)). Clearly,
there is a point when the input voltage has a value where the
combined dynamic and conduction losses are at a minimum,
and this point is of particular interest to us because it
represents the point of highest efficiency for
the core supply.
The effect of the gate-drive voltage is more
complex because it involves the nonlinear
relationship between the gate-drive voltage
and the MOSFET on-resistance. By driving
the MOSFET at the right drive level, RDS(ON)
may be reduced by more than 50% from that
of the nonoptimum gate-drive conditions.
We conducted two sets of tests: one to
verify the effect of the input voltage on losses
and efficiency and the other to verify the
effect of the gate-drive voltage on the same
efficiency and losses.
Fig. 1 depicts a voltage regulator module
(VRM) efficiency as a function of the input
Fig. 1. The measured converter efficiency of a VRM switching at 1 MHz is plotted as a
voltage at different load currents. Given
function of the input voltage over the 3.5-V to 12-V range.
Power Electronics Technology June 2005
24
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OPTIMIZING VOLTAGE
Efficiency (%)
an efficiency increase of about 3% may be gained
when operating at the optimal gate-drive voltage as
compared to driving at the conventional 12 V.
Fig. 3 shows the effective loss resistance (ROL)[9]
of the same converter in Fig. 2 as a function of the
gate drive at different load currents. At full load,
from 4.7-mΩ down to 3.9-mΩ, a gain of 17% can
be achieved.
Fig. 4 shows the gains that may be attained at
different load currents by optimizing the gate drive
individually at each point.
�
Fig. 2. The measured converter efficiency of a VRM switching at 200 kHz is plotted as
function of gate-drive voltage over the 5-V to 11-V range.
Mathematical Representations of
the Losses
First, we will derive formula to calculate the
input voltage that delivers the highest power
efficiency of a buck converter. To begin, consider
the power dissipation relationship with input
voltage for the top MOSFET. The power dissipation
equation for the top MOSFET is as follows:
OL
PD = ID2 R DS(ON)
Fig. 3. The effective output loss resistance for the VRM of Fig. 2 is plotted as a function
of load current and gate-drive voltage.
VO
1
+
VIN ID FS ((T
TR +T
+TF )
VIN
2
where TR and TF are the rise and fall times,
respectively; VIN is the input voltage; ID is the load
current; FS is the switching frequency; RDS(ON) is the
MOSFET on-resistance; VO is the output voltage;
and VO/VIN is the duty cycle.
Assuming that TR=TF , we get:
Efficiency (%)
PD = ID2 R DS(ON)
(Note that we have ignored the losses due to
the MOSFET output capacitance (COSS) because
this term plays a secondary role in the power
dissipation and it would complicate the solution
immensely.)
Taking the first derivative of PD with respect to
VIN, we get:
V
0 = -ID2 R DS(ON) O2 + ID FS TR
(Eq. 1)
VIN
Optimum Drive
Gate Drive = 12 V
Fig. 4. A plot of efficiency versus load current reveals the efficiency improvement
obtained with the optimized gate drive as compared with the standard 12-V gate
drive.
Then, taking the second derivative with respect
to VIN yields:
V
0 = 22IID2 R DS(ON) O3
VIN
The second derivative is positive, indicating a
minimum for power dissipation.
Solving Eq. 1 for the optimum input voltage (VINOPT),
we get:
the typical 1.5-V VRM output voltage, optimum efficiency
is achieved at an input voltage of 7 V to 8 V, not at the
current 12 V. In this particular situation, an entire four
percentage points in efficiency may be gained at full load,
and considering that at this point the total losses are only
16 percentage points (100%–84%), this gain represents a 25%
reduction in the converter los ses, a very sobering fact.
Fig. 2 depicts the efficiency of a different 1.5-V output
VRM as a function of the gate-drive voltage showing that
Power Electronics Technology June 2005
VO
+ VIN ID FS TR
VIN
VINOPT =
ID R DS(ON)T VO
FS TR
where RDS(ON)T is the top MOSFET’s on-resistance. For
an example calculation of VINOPT , assume the following
parameters: VO = 1.7 V, V IN = 12 V, T R = 15 ns, and
26
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OPTIMIZING VOLTAGE
RDS(ON)T = 0.012 . Plotting the optimal input voltage (VINOPT)
versus drain current for switching frequencies of 300 kHz,
500 kHz and 1 MHz, we get the results graphed in Fig. 5.
Now, consider the power dissipation relationship with
input voltage for the bottom MOSFET.
The power dissipation equation for the bottom MOSFET
is as follows:

V 
PD = ID2 R DS(ON)B  1 − O  + VD ID FS TR
 VIN 
where RDS(ON)B = bottom MOSFET on-resistance.
Taking the first derivative with respect to VIN:
0 = ID2 R DS(ON)B
VO
VIN 2
Now, taking the second derivative:
0 = -22IID2 R DSON(B)
VO
VIN 3
Fig. 5. Optimum input-source voltage for the top MOSFET alone is
plotted as a function of drain current and switching frequency.
between RDS(ON) and VG is linear for simplicity:
RDS(ON)VG = RDS(ON) – BVG
where VO is the amplitude of the gate-driver output
voltage and B is a constant.
Assume that VO=1.7 V, FS=1106 Hz, TR=1510-9 sec,
and CIN=510-9 F. Then, substituting in the equation for
PwrElec Ignition Coils1/4p 5/12/05 12:44 PM Page
two
points at VG=5 V and 10 V.
The second derivative is negative, indicating a maximum
as VIN approaches infinity. This clearly indicates that losses
in the synchronous rectifier do not have a minimum as a
function of VIN.
Next, let’s consider both the top and the bottom
MOSFETs’ losses together and attempt to find the optimum
input voltage that would result in minimum losses, and
hence, highest efficiency for the buck converter.
The equation for the combined losses in the top and
bottom MOSFETs is:


V 
V 
PD = ID2 R DS(ON)B  1 − O  + R DS(ON)T O  +
VIN 
 VIN 

VD ID FS TR + VIN ID FS TR
(Eq. 2)
Taking the first derivative of Eq. 2, we get:
 R DS(ON)B VO R DS(ON)T VO 
A = ID2 
+ ID FS TR
V 2
V 2 

IN
Transformers, Inductors,
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UL/CSA/CE Standards
IN
Solving for VIN yields two solutions:
-FS TR ID VO (R DS(ON)BB - R DS(ON)T )
FS TR
−
and
-FS TR ID VO (R DS(ON)B - R DDSS(ON)T )
FS TR
and taking the positive solution leaves:
FS TR ID VO (R DS(ON)BB - R DS(ON)T )
FS TR
For an example using this equation, assume that
VO =1.7 V, V IN =12 V, T R =15 ns, R DS(ON)T =0.01 , and
RDS(ON)B=0.006 . Once again, let us represent this equation
in a graph form at switching frequencies of 300 kHz , 500 kHz
and 1 MHz to derive the data plotted in Fig. 6.
Next, let us consider the dependency of power dissipation
on the gate-drive voltage. Assume that the relationship
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1
VINJ (V)
VINJ (V)
OPTIMIZING VOLTAGE
G1
IDJ (A)
IDJ (A)
Fig. 6. Optimum power-source voltage is plotted for the combined top
and bottom MOSFETs.
0.100 = RDS(ON) – B•5
0.008 = RDS(ON) – B•10
Solving Eq. 3 and Eq. 4 for RDS(ON) and B:
-5
A = (11 -10
-10 )
(RB
DS(ON)
DS(O
N)
) = A-1 i(0.010
0.008 )
Fig. 7. Optimum gate-drive voltage is plotted as a function of switching
frequency and load current.
I D 2 B∆
(Eq. 9)
2C IN FS
Next, let’s consider the situation where we determine one
optimum gate-drive voltage for both the top and bottom
MOSFETs:
0.012=RDS(ON)T – B•5
0.010=RDS(ON)T – B•10
(Eq. 3)
(Eq. 4)
VG =
(Eq. 5)
Solving Eq. 5, we get:
RDS(ON)=0.012  and B=4  10-4
The duty cycle () may be calculated according to this
equation:
A = (11
A = (11
Let us consider the losses in the top MOSFET:
PD = ID (R DS(ON) - BVG )∆ + VG C IN FS + PDYN
where CIN=total input capacitance measured at the gate
of the MOSFET, including the Miller capacitance.
Taking the first derivative of PD with respect to VG,
(Eq. 6)
-5
-10
)
(RB
DS(ON)B
B
) = A-1 i(0.008
0.006 )
0 = -ID2 B T ∆ - ID2 BB ((11 - ∆) + 2VG (C INT
)F
FS
INT + C INB )
(Eq. 7)
Then, taking the second derivative:
0 = 2(C
2(C INT
)F
FS
INT + C INB )
Now, let’s consider the bottom MOSFET given that
VIN=12 V and =1-(V
=1-(VO/VIN). In this case:
Now, solving the first derivative equation yields:
PD = ID (R DS(ON)
(ON) − BVG )∆ + VG C IN FS + PDYN
(ON)
2
VG =
Taking the first derivative of PD with respect to VG
yields:
ID2 B T ∆ + ID2 BB (1 - ∆)
2(C
C INT + C INB )FS
Assume that CINT = 2.2 x10-9 F and CINB = 4x10-9 F. Then
once again we may represent the equation for optimum gatedrive voltage in graphic form for switching frequencies of
300 kHz, 500 kHz and 1 MHz, as shown in Fig. 7.
Finally, using the equations derived previously, Fig. 8
0 = -ID2 B∆ + 2VG C IN FS
(Eq. 8)
Now, solving for Eq. 6 the optimum gate-drive voltage
VG, we get:
Power Electronics Technology June 2005
) = A-1 i (0.012
0.010 )
where BT and BB are the coefficients of the equation
for RDS(ON) as a function of VG, and RDS(ON)T and RDS(ON)B
are the other coefficients of the top and bottom MOSFET,
respectively.
Taking the first derivative with respect to VG:
Now, solving Eq. 6 for the optimum gate-drive voltage
VG, we get:
2
DS(ON)T
T
VG 2 ((C
C INTT + C INB ))F
FS + PDYN
2
I 2 B∆
VG = D
2C IN FS
(RB
The total power dissipation of both the top and bottom
MOSFETs is:
2
PD = ID2 (R DS(ON)T
(R DS(ON)B - BB VG )(1 − ∆) +
(ON)T − B T VG )∆ + I D (R
(ON)
2
0 = -ID B∆ + 2VG C IN FS
)
0.008=RDS(ON)B – BB•5
0.006=RDS(ON)B – BB•10
V
∆= O
VIN
2
-5
-10
28
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OPTIMIZING VOLTAGE
Intel Technology Symposium 2003.
3. Elbanhawy, Alan. Mathematical
Treatment for HS MOSFET Turn Off.
Proc. PEDS 2003.
4. Elbanhawy, Alan. A Quantum
Leap in Semiconductor Packaging.
Proc. PCIM China, pp. 60-64.
5. Alan Elbanhawy. The Road to
200 Amps at one Volt VRM. Proc.
PCIM Europe 2004, pp. 54-58.
6. Elbanhawy, Alan and W.
New berr y. Packag ing Parasitic
Fig. 8. Optimum input voltage as a function
Fig. 9. Optimum gate-drive voltage as a
Resistance Frequency Effect
Effects. Power
of the switching frequency FS and the load
function of the switching frequency FS and
Electronics Conference USA 2004
current ID .
load current ID .
PCIM San Francisco.
depicts the optimum input voltage as a function of the load
7. Elbanhawy, Alan, and J. Ejury. Investigations of the
current ID and the switching frequency FS. Examination of
Influence of PCB Layout Parasitic Inductances in DC/DC
the graph shows that the optimum input voltage for high
Converters on the Efficiency. Proc. PCIM Europe 2004,
frequency high current has a value of about 4 V to 6 V, a
pp. 31-36.
far cry from the current 12 V. Fig. 9 depicts the gate-drive
8. Elbanhawy, Alan. Are Traditional Packages Suitable for
voltage again as a function of ID and FS and clearly shows
the New Generation of DC-DC Converter? Proc. IPEMC China
that higher currents require higher drive voltage, while
2004.
higher frequency requires lower drive voltage for optimum
9. Elbanhawy, Alan. Is the Power Conversion Efficiency
power loss.
Running Out of Steam as a Comparison Tool? Proc. Portable
Several conclusions can be drawn from the experiments
Power Developer Conference USA 2005.
PETech
described here. We have shown in Figs. 5 and 6 that the
optimal input-source voltage is not 12 V, but rather in the
neighborhood of 3 V to 5 V, depending on the load current
and the switching frequency. The larger current drawn from
a 5-V source compared to a 12-V one can easily be dealt
with through proper motherboard layout. Unfortunately,
the off-line power-supply (silver-box) manufacturers have
championed the push for higher source voltage because this
allows them to continue using cheaper rectifiers instead of
synchronous rectifiers. This savings results in lower-efficiency
dc-dc converters and aggravates the thermal management
problem in PCs.
We also have shown that the gate-drive voltage has an
optimal value. This could be accommodated by PWM
controller manufacturers giving the end customer the choice
of gate-drive voltage.
The optimal gate-drive voltage, as seen from Eq. 7 and
Eq. 9, is inversely proportional to the switching frequency
and directly proportional to the square of the load current.
There is no optimal source voltage for the synchronous
rectifier on its own since a larger input voltage means longer
on-time for the synchronous rectifier and hence more power
dissipation.
References
1. Elbanhawy, Alan. Effect of Parasitic Inductance
on switching performance. Proc. PCIM Europe 2003,
pp. 251-255.
2. Elbanhawy, Alan. Effect of Parasitic Inductance on
Switching Performance of Synchronous Buck Converter. Proc.
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Power Electronics Technology June 2005