Characterization and Packaging of SiC JFET Power Modules
for Extreme Environment Motor Drives
Volodymyr Bondarenko and
Paul Martin
Center for Advance
Vehicular Systems (CAVS),
Mississippi State University
201 Research Blvd.
Starkville, MS 39759
Michael S. Mazzola, Robin
Kelley, and Janna Casady
SemiSouth Laboratories, Inc.
200 Research Blvd
Starkville, MS 39759
(662) 324-7607
mike.mazzola@semisouth.com
Cai Wang, Yi Liu, Shyam
Gale and Wayne Johnson
Laboratory for Electronics &
Packaging (LEAP)
Auburn University
162 Broun Hall/ECE Dept.
Auburn, AL 36849
(334)844-1880
johnson@eng.auburn.edu
Abstract
SiC power devices can be used to build modules for dc-dc converters and motor controls capable of high temperature
operation. This expands the opportunities for power electronic use in extreme environments or allows simplified cooling
systems in more conventional temperature range environments. In this work, power modules have been fabricated using
silicon carbide power vertical JFETs (VJFETS) with an inherently safe gate drive design. The VJFETs are paralleled in the
module, providing scalable current carrying capacity. The electrical characteristics of the module were measured over the
temperature range from 25oC to +400oC. The substrate, die attach and interconnection materials and processes used are
discussed. Thermal cycle test results over the temperature range from +35oC to +400oC and high temperature storage at
450oC results are presented.
Key words: SiC, high temperature, power modules
Introduction
The wide bandgap, high electric field strength and
high thermal conductivity make SiC an idea material for
fabrication of power electronic devices [1]. A number of
SiC power devices have been proposed and fabricated
including Schottky diodes, p-n diodes, and gate turn off
(GTO) transistors, bipolar junction transistors (BJTs),
metal oxide semiconductor field effect transistors
(MOSFETs) and junction field effect transistors (JFETs).
In this work vertical JFETs have been characterized and
used to build modules. The structure of the VJFET is
shown in Figure 1. VJFETs in SiC are especially
attractive for high power applications because of the
inherent stability of the p-n junction gate and the basic
maturity of all aspects of the JFET technology in SiC.
Individual devices are applicable to kilowatt-class
power supplies requiring 5- to 10-A, 600-V or 1200-V
ratings. However, the 100% unipolar structure of the 4HSiC VJFET allows die to be connected in parallel to form
an equivalent switch of much greater current; meaning
hundreds of amperes [2]. This makes the possibility of
developing IGBT replacements a realistic goal. The
resulting scaled switch can then have average and surge
current ratings comparable to silicon IGBTs while
exhibiting switching properties like silicon MOSFETs.
The SiC VJFET-based switching module will have lower
thermal resistance and higher rated junction temperature
than any available silicon devices due to the thermal
properties of the silicon carbide and the wider bandgap.
Figure 2 provides a screen shot of a switching event at
25oC, for a 600-V, 150-A rated part that was fabricated by
paralleling five 600-V, 30-A rated die [2]. These results
suggest that substantial power system benefits can be
realized in the near term with the SiC VJFET.
Figure 1. Cross Section of the Vertical JFET
substrate options are shown in Table 1. AlN has the
highest thermal conductivity and the best coefficient of
thermal expansion (CTE) match to SiC (CTESiC =
4.2ppm/oC). However, the fracture toughness of AlN is
lower than that of Al2O3 and Si3N4 which results in
fracture of the AlN during thermal cycling with thick Cu
foils. Si3N4 has the lowest CTE, intermediate thermal
conductivity and superior fracture toughness. DBC Al2O3
is widely used substrate for Si based power modules and
was used for the initial module construction in this work.
Wire Bond
SiC Die
Figure 2 – Performance of a 600-V, 150-A SiC VJFET
switch fabricated with five parallel die. This switch is
capable of a maximum operating frequency of 6 MHz.
When a normally off VJFET is configured as a socalled static induction (SIT) diode [3] by shorting the
gate-source terminals it can function as an efficient hightemperature rectifier. Figure 3 compares the forward
conduction properties of a SiC Schottky rectifier, a SiC
SIT diode, and a pure SiC pn-junction diode. A SIT diode
has cut-on voltage and reverse recovery properties much
closer to that of a Schottky barrier diode (SBD), but a
reverse leakage current much closer to that of a pnjunction diode. This means substantially lower conduction
and switching loss as compared to a pn-junction rectifier,
but a much lower reverse leakage current at high
temperature as compared to a SBD. The advantage is that
a separate Schottky rectifier does not have to be qualified
at 400˚C and a common VJFET component is used in all
applications.
Moly
Tab
Cu
Foil
Ceramic Substrate
Figure 4. Illustration of SiC Power Module
Construction
Table 1. Substrate Material Properties
Al2O3
Thermal
Conductivity
(W/m•ºC)
CTE (ppm/ºC)
Si3N4
20-27 30-90 150-230
6.7-7.1 2.8-3.2 4.2-4.5
Young’s Modulus 380
310
(GPa)
Fracture
3.3-3.7 5-6.5
toughness
(MPa ½ )
Flexural Strength 274
850
(MPa)
Figure 3. Comparison of forward conduction
properties of three different SiC rectifiers at room
temperature.
Module Construction
The module construction is illustrated in Figure 4.
The ceramic substrate options are direct bond copper
(DBC) on Al2O3, DBC on AlN and active metal braze
(AMB) on Si3N4. Material properties of the ceramic
AlN
330
2.7
400
A molybdenum tab was used in the module design to
serve as a CTE buffer between the SiC die and the copper
foil. In addition, indium (from the Au-In die attach braze)
is not compatible with Cu. In and Cu form weak
intermetallics. The Mo tab serves as a high temperature
diffusion barrier between the Au-In die attach and the Cu
foil on the substrate. The Moly tab was attached using a
eutectic Cu-Ag preform in a vacuum brazing furnace at
850oC. The Moly tabs were Ni clad only on one side and
Au plated on both sides. The Ni clad side was assembled
facing the Cu foil substrate. After brazing, the substrate
was Ni and Au electroplated. By selective plating, the top
surface of the Moly tab was only electroplated with Au.
The SiC die was attached using Au-In (81wt%/19 wt%)
performs. The die were attached using an SST vacuum
system and a peak temperature of 525oC. Multiple Au
wires were bonding using a Palomar Products 2460
Model V thermosonic wire bonder to make source and
gate electrical contacts.
and T = 400 ºC, validating the impressive blocking
performance of the SIT diode at extreme temperatures.
3
Electrical Test Results
The forward conduction characteristics of a module
consisting of four SiC VJFETs in parallel were measured.
Figure 5 shows the result at T = 25ºC; and Figure 6 shows
the result for the same devices at T = 400ºC. As expected,
the positive temperature coefficient of these unipolar
devices results in a steady increase in on-resistance (i.e.,
declining slope in the linear region) and a steady decrease
in saturation current. Over the temperature span tested,
the on resistance increases by 1.7%/ºC. It should be noted
that these devices are not normally on in the sense that a
small positive gate-source bias produces a lower on
resistance. In both figures, the gate-source bias was
limited to the range 0 ≤ VGS ≤ +2 V. Negative gate source
bias produces rapidly increasing resistance ultimately
leading to the ability to block voltage as high as 600 V.
The pinch-off voltage of the paralleled devices at 25ºC is
-3.7 V. The pinch-off voltage decreases slightly with
temperature at a rate of -450 ppm/ºC.
IS [V]
2
VGS = 0 V
0.5
1
1.0
1.5
2.0
0
0
1
2
3
4
5
VDS [V]
Figure 6. Forward conduction characteristics of four
VJFETs in parallel at T = 400ºC.
4.00E-06
3.00E-06
T = 400ºC
ID [A]
12
10
T = 300ºC
2.00E-06
T = 200ºC
1.00E-06
IS [A]
8
T = 25ºC
6
0.00E+00
VGS = 0 V
0.5
1.0
1.5
4
2
50
0
1
2
3
4
70
80
90
100
VDS @ VGS = 0 V [V]
2.0
0
60
5
Figure 7. The reverse blocking performance of the
three SIT diodes in parallel at four temperatures
ranging from 25 ºC to 400 ºC.
VDS [V]
Assembly Test Vehicle: Reliability Results
Figure 5. Forward conduction characteristics of
four VJFETs in parallel at T = 25ºC.
A module of three SIT diodes in parallel was
constructed to test the paralleling of these rectifiers. Of
greatest interest is the blocking performance over
increasing temperature. Figure 7 illustrates the leakage
current of the SIT diodes as a function of voltage from the
drain to the source (which is equivalent to reverse biasing
a conventional rectifier). The leakage current of the three
SIT diodes in parallel is less than 4 µA at VDS = 100 V
To evaluate the high temperature reliability of the
Au-In die attach system, test SiC die were assembled to
the Moly tabs. The Moly tabs were not bonded to ceramic
substrates since failure of the Cu foil in thermal cycle
testing has previously been reported by the authors [3].
The SiC test die was 3.8mm x 3.8mm in dimension. The
thermal cycle profile is shown in Figure 8. The shear test
results as a function of number of thermal cycles are
shown in Table 2. The shear test limit of the Dage
PC2400 is 100kg-f.
SiC/Moly tab test vehicles were also assembled and
subjected to high temperature storage at 450oC. The test
results are shown in Table 3. There was degradation in the
shear strength after 250 hours.
500
400
300
200
100
0
0
50
100
150
200
Figure 8. Thermal Cycle Profile
Table 2. Shear Strength as a Function of Thermal Cycling
Cycles
Shear Strength (kg-f)
>100
0
>100
120
>100
300
>100
600
>100
840
>100
1200
2400
88, 72, 79, 86, 70, 34, 41
2880
<10
Table 3. Shear Strength as a Function of Storage at 450oC
Hours @
0
100
250
500
450oC
Shear
Strength
(kg-f)
>100
>100
5 >100,
10-15
65, 71, 78
Failure analysis was performed. Figure 9 shows the
SEM and EDS results for the as-built SiC-on-Moly tab
assembly. Some voids were observed in the braze layer
as-built. The In is uniformly distributed between the Moly
tab and the SiC die.
Figure 10 shows the SEM and EDS analysis after 120
thermal cycles. The Au-In layer has vertical cracks. The
hypothesis is that the cracks result from the CTE
mismatch between the Au-In and the Moly tab and SiC
die. The Moly tab and SiC die have nearly the same CTE,
but the CTE of the Au-In is significantly higher. As the
cracks are vertical, the shear strength of the assembly
remained high since the individual columns were still well
bonded to the Moly tab and the SiC die. It was also
observed that the In had segregated to the defects (cracks
and voids). Thomas [5] has previously reported the
surface enrichment of In in evaporated Au (98%) – In
(2%) thin films at room temperature. The voids and
cracks create internal free surfaces for In segregation.
Figure 11 shows the SEM and EDS analysis after
1200 thermal cycles. The images are similar to those after
120 cycles, but some horizontal cracks are forming.
Figure 12 shows the SEM and EDS analysis after 2880
thermal cycles. There is complete failure at the Moly-tobraze layer interface. In has also segregated to the
exposed bottom surface of the braze layer (Figure 13).
SEM analysis of cross sections of Au-In braze joints
stored at 450oC also showed segregation of the In to the
surface of internal voids. These voids were formed during
the initial die attach brazing process. There was no In
segregation to the void surface in the as-brazed cross
sections (Figure 9). This segregation of the In is thought
to be the cause of the degradation in shear strength with
aging at 450oC.
Conclusions
The JFET is shown in this paper to be a highly
versatile device for extreme temperature application.
When the pinch-off voltage is negative, the device is a
conventional transistor which can be used in linear and
switching applications. The positive temperature
coefficient of the on resistance of the JFET allows many
devices to be paralleled to scale the power handling of the
composite switch to whatever value required. As shown
in this paper, hundreds of amperes are entirely feasible.
In applications, it is very common for a rectifier to be
required along with a transistor. For example, switch
mode power supplies based on the buck, boost, and halfbridge topologies always require a free-wheeling rectifier
to operate correctly. Rather than qualify a different
rectifier type for extreme temperature (e.g., Schottky
rectifier), it was shown in this paper that a normally off
JFET can be configured as a SIT diode to provide an
extreme temperature rectifier. Since the device design and
fabrication is the same for both the JFET transistor and
the SIT diode (only the pinch-off voltage is different),
then the same rugged performance with respect to
reliability and radiation tolerance is expected for both
types of devices.
Based on the high melting point of Au-In braze, it
was evaluated as a potential high temperature die attach
material. However, the indium in the Au-In die attach
segregated to defect surfaces (cracks and voids) during
high temperature exposure (thermal cycling or high
temperature storage). Indium surface enrichment of
evaporated Au-In thin films has been reported at room
temperature. This segregation does appear to negatively
impact the reliability of the die attach. Alternate high
temperature die attach materials must be evaluated for
SiC power module assembly operating at 400-450oC.
Acknowledgements
This work was funded in part by NASA and the
Center for Space Power and Advanced Electronics at
Auburn University under contract NASA NCC8-237.
Sample_650_Img1
SiKA
MoLA
InLA
AuMA
Figure 9. SEM and EDS Analysis of As-Built SiC-on-Moly Tab Construction.
A1_423_Img1
SiKA
MoLA
InLA
AuMA
Figure 10. SEM and EDS Analysis after 120 Thermal Cycles.
A1_24_Img1
SiKA
MoLA
InLA
AuMA
Figure 11. SEM and EDS Analysis after 1200 Thermal Cycles.
A1_599_Img1
SiKA
MoLA
InLA
AuMA
Figure 12. SEM and EDS Analysis after 2880 Thermal Cycles.
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Figure 13. SEM Micrograph of Au-In Braze
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