Programmable
Cellular
Logic
Arrays
by
Richard
G.
Shoup
Computer
Science
Department
Carnegie-Mellon
University
Pittsburgh,
Pennsylvania
March,
1970
Submitted
in partial
for the
to Carnegie-Mellon
fulfillment
of the
_egree
of Doctor
of
University
requirements
Philosophy
This
work
was supported
by the Advanced
Research
Projects
of
the Office
of the Secretary
of Defense
(F_620-&7-C-0058)
is monitored
by the Air
Force
Office
of Scientific
Research.
document
has been approved
for public
release
and sale;
its
bution
is unlimited.
Ageacy
and
This
distri-
-il-
Carnegie-Mellon
Programmable
University
Cellular
Richard
Logic
G.
Arrays
Shoup
Abstract
In
recent
designer
years,
of
computing
batch-fabricate
large
semiconductor
of
:ident ical
cells.
and
customizing
more
to
the
may
number
perform.
presence
is
numerous
have
logic
manufacture.
range
of
presented
shown
to
for
manufacturing
and
be
creating
the
arrays
arrays
by
a
physical
advantages
manufacture,
to
their
they
generality,
are
designed
different
examples
analyzed.
One,
effective
shift
defects.
of
tolerance.
which
more
of
by parameter
aften
according
tasks
a single
cellular
Potential
failure
the
using
than
variability
enhanced
on
to
investigated
by
rather
the
ability
determined
cell,
cla_sified
are
techniques
of
are
the
the
considers
significantly
arrays
array,
conventional
be
Two
low-generality
register
and
and
digital
functional
testing,
Arrays
in
during
include
efficient
of
provided
components
researchers
functions
gates
operation
logic
dissertation
cell
logic
technique
i.e.,
kinds
This
individual
flip-flops
this
various
with
of
Numerous
have
advances
hardware
numbers
slice.
synthesis
whose
technological
registers
a
of
shift
than
some
in
the
-iii-
new
important
cell
in
schema
synthesis
for
are
presented
design
the
target
of
central
programmable
using
control
is
a pp roach.
processoc
logic
detail
introduced
the
Techniques
and
is
these
compared
class
of
tasks.
control
logic
A
to
a
the
As
is
small
techniques.
more
exhibits
properties
high-generality
improving
of
array.
which
This
match
an
functions.
between
example,
the
approached
computer
method
conventional
in
is
an
array
problem
terms
of
implemented
of
synthesizing
microprogramming
a
in
-iv-
_C know ledge
I
and
many
wish
guidance
the
also
this
important
help
personal
this
work.
in
support
were
indebted
topic
early
Finally,
her
Professor
suggestions
am
suggested
thank
during
helpful
I
to
to
and
special
typing
during
C.
His
of
this
Bell
enthusiastic
Dr.
T.
Jesse
the
Quatse,
guidance
his
and
who
advice
and
his
originally
direction
during
work.
are
due
proofreading
long
for
interest
appreciated.
thanks
and
Gordon
sincerely
provided
phases
me n ts
effort.
to
my
and
wife,
for
Nancy,
her
for
continuing
--V--
Table
of
Contents
A b s tract
ii
Acknowledgements
i v
Table
List
of
of
Table
I.
Contents
v
Tables
of
vi
Figures
vii
Introduction
1
I. I Background
2.
and
1.2
programmable
1.3
The
1.4
Overview
logic
n-space
of
of
Rssumptions
3.
S.
2.3
Failure
3. I
The
3.2
A shift
and
logic
problem
7
arrays
18
the
standard
logic
of
testing,
33
system
35
defects
and
42
diagnosability
50
arrays
register
High-generality
56
arrays
58
array
82
arrays
4. I
A previous
PL
4.2
High
properties
4.3
Connection
4.4
Cell
R ef er en ce s
LSI
topics
arithmetic/parity
array
array
102
and
a generic
cell
type
107
114
functions
122
application
and
101
functions
nucleus
Conclusions
the
29
distribution
modes,
Low-generality
a. 5 An
5.
and
12
work
preliminary
2. I Evaluations
Yields
and
cellular
this
and
2.2
definitions
and
further
analysis
research
138
169
176
-vi-
List
3.1
Evaluation
4.1
The
4.2
Three-variable
4.3
Overlapped
_.4
Inbus
4.5
States
of
equivalence
and
of
At
arrays
c.l_ss
of
function
microco_e
outbus
the
for
signals
.Rosin
of
Tables
A2
76
AAL_^C
127
classes
129
and
Rosin
for
machine
machine
the
Rosin
156
machine
159
160
-vii-
Table
1.1
Idealized
1.2
Lewel
1.3
Several
fabrication
of
of
integration
vs.
interconnection
2. I Standard
set
of
2.2
Examples
of
cell
2.3
Representatiwe
2.4
Experimental
2.5
Cluster
2.6
A special
3.1
Array
3.2
Complete
3.3
Primary
3.4
Secondary
3.5
control
3.6
Functional
3.7
Complete
3.8
Primary
3.g
Secondary
Figures
logic
blocks
number
of
4
unique
parts
structures
logic
36
complexity
cell
defects
form
yield
on
of
39
Petritz
vs.
cell
data
size
a hypothetical
cell
9
24
elements
slice
case
of
45
46
slice
failure
49
53
AI
61
cell
AI
62
functions
of
functions
logic
of
of
AI
cell
array
diagrams
cell
cell
64
AI
65
kl
of
66
array
A2
69
A2
functions
70
of
functions
of
42
of
array
71
A2
72
3.10
Control
logic
3.11
Minimal
synthesis
of
the
primary
3.12
Minimal
synthesis
of
the
secondary
3.13
Functional
3. lq,
Cell
3.15
Example
of
3.16
Control
logic
diagram
of
A2
73
array
S1
$I
functions
functions
77
78
83
84
array
of
$1
array
85
SI
87
-viii-
3.17
Shift
register
4.1
Four
cells
4.2
Complete
4.3
_
flip-flop
4.4
A
high-g
4.5
Adjacent
4.6
Parity
of
4.7
Busing
schemes
4.8
Functions
4.9
Cell
array
in the
Wahlstrom
Wahlstrom
in
PL
cell
array
103
104
Wahlstrom
array
106
schema
112
1-outpl, t cells
116
]-input
of
g]
cell
the
paths
examples
in
arraTs
118
120
3 variables
function
126
FI
131
4. 10
Cell
function
F2
131
4.11
Cell
function
F3
132
4.12
Cell
function
F4
132
4.13
Cost
vs.
number
4.14
Data
and
control
_.15
Control
4.]6
Functional
4.17
C section
of
cell
GI
147
4.18
F section
of
cell
GI
I_8
4.19
Control
_.20
Detail
of
control
parameters
4.21
Timing
of
typical
GI
_.22
Block
4.23
Flowchart
a.2.
PL control
of
functions
for
example
cells
submachines
139
machines
diagram
parameter
diagram
and
of
141
of
cell
section
logic
Rosin
for
G]
of
146
G1
cell
of
cell
I_8
GI
150
chain
153
machine
instruction
array
134
Rosin
set
155
for
machine
Rosin
machine
157
161
--I--
1
Chapter
Introduction
1 . Introduction.
The
design
rules
are
times,
advanced
that
constantly
real
race
to
make
LSI
structure
a
can
design
in
remainder
appropriate
to
and
of
section
this
throughout
of
relate
thi rd
to
to
summarizes
study.
this
the
ThroL1gh
study
arrays,
this
set
the
Related
manner
in
far
the
between
and
what
of
a type
our
of
dissertation
some
define
all
work
work
the
important
of
concept
aspects
to
cellular
which
will
be
of
programmable
circuitry
attempts
of
at
large-scale
thus
supply
integrated
chapter.
of
Realization
section
has,
neglected
gap
chapter
systems.
ground
gap.
this
it
whose
devious
advent
can
that
large-scale
structure
of
narrowing
a
been
largest
logic
task
:in such
The
use.
sections
a
Technology
often
the
programmable
two
The
interrelating
last
opened
computing
terms
has
effectively
logic
of
it
and
capabilities
contributes
first
pace
developments.
has
is
changing.
rapid
of
new
called
discussed.
The
of
programmable
logic
such
hardware
rapidly
manufacturing
The
the
use
techniques
hopefully
of
and
circuitry
our
design
at
computing
understanding
integrated
what
of
is
impart
logic
also
some
arrays.
follows
in
the
cited
whenever
-12-
I. I Background
In
strong
resulting
or
density
on
from
integrated
gates
the
have
a
had,
and
square
are
years
one
It
is
million
ago,
all
to
and
with
etc.
densities
further
of
believed
per
on
machines
resistors,
gates
the
continue
designer
available
inch.
in
fabrication
will
systems
few
made
batch
transistors,
chips
than
been
and
logical
discrete
per
more
has
only
circuit
more
of
trend
hardware,
constructed
10,000
a
effect
advances
miniaturization
This
computing
Today,
large
with
components.
a
w ere
years,
associated
logic
have,
definitions.
recent
technology
of
and
that
square
inch
decrease
in
is
possible.
For
relative
this
the
cost
would
If
were
(including
with
benefits
can
various
feasible.
in
logic
elements
has
only
all
applications
of
zero
Examples
terminals
central
such
as
lower
in
line
and
cost
buffering
In
not
and
pre-editing
vast
of
be
places
been
and
logic
reductions
of
system
a
few
carries
particular,
caches
Use
the
cost
various
have
cost
computer
only
circuitry
scratchpads,
permit
of
the
itself,
overall
would
at
by
present-day
total
logic
would
can
a
support)
system
processors.
these
in
the
potential.
the
which
Taken
in
the
and
muclh greater
are
occurred.
decrease
cost,
, this
included
significant
circuitry
software,
organizations
in
small
logic
at
However
be
remote
memories
a
the
hardware,
lower.
logic
a
available
percent
it
reasons,
mean
computing.
system
of
same
more
and
in
previously
facilities
associative
circuitry
in costs
in
of
-3-
software
and
efficiency
maintenance,
at
the
same
However,
technology
•fabrication
resulted
Figure
fabricating
a
a
silicon
good
packages
wafer.
are
are
in
gives
of
and
cost
back-plane
of
to
Therefore,
some
at
least
into
testing
the
thrust
and
build
computing
the
sort
are
tested
and
retested.
a
printed
of
the
upon
is
in
of
many
(ICs),
fabricated
diced
into
Later,
on
chips.
the
board
assuming
to
good
form
a
large-volume
costs:
of
$0.002
/ circuit
$0.27
/ circuit
$0.73
/ circuit
>$2.00
/ circuit
accumulated
machine.
not
and
burden
the
used
are
circuit
assembly
final
test
are
cost
process
circuits
and
[20]{0}
the
of
testing,
1000
a
of
integrated
following
after
etc.
levels
IC after
packaging
device
test
wired
and
is
the
other
flip-flops,
breakdown
of IC after
onto
module,
proportion
benefit)
cost
of IC
dicing,
cost
a factor
or
circuits
with
design
of initial
fabrication
IC on the
slice
cost
system
fabrication
idealization
Identical
onto
production
cost
boosting
micrologic
mismatch
of
packaged
A
1968
an
gates
soldere_
in
to
module
All
chips
packaging
shows
several
module.
is
a severe
computers.
functional
Thus
progress
necessary
logic
representing
Tihe
in
1.1(a)
third-generation
each
rapid
techniques
hardware.
significantly
time.
this
has
while
Clearly,
(and
will
even
costs
not
density
of
the
(as
as
much
system
well
designer.
before
It
of
be)
IC
processing,
decreasing
ICs
of
the
in
themselves.
the
behooves
resulting
him
now
-4.-
--5--
%0
organize
his
large-scale
are
using
is
to
1.2.
logic
cellular
arrays
in
slice.
The
array.
is
determine
the
shown[24]
cell
e tc.
:is
the
particular
inputs
and
that
it
in
to
Tihere
cells
is
logic
which
reasonable
the
perform
no
function
possible
need
for
by
set
it
that
slice
dicing,
cells
the
is
are
silicon
called
a
logic
8innick[23].
of
parameters
performs
in
active.
any
packaging
array
has
been
functions
and
required
function
which
the
It
cell
Therefore,
desired
of
circuits
microcellular
choose
so
array.
the
of
on
use
process
method,
the
are
to
ways
on
survey
a
the
duplicate
pattern
area
given
outputs
by
the
excellent
later
the
conventional
set
in
the
levels
fabrication
of
to
allow
various
inherent
regular
of
time,
the
idealized
the
themselves
same
between
Each
in
an
is
synthesized
parameterized
intact.
in
the
chosen
Research
interconnections
be
some
entire
summarized
Each
an
Unlike
lend
problems
approach.
a cell.
connected
or
shows
at
match
in
a cellular
wafer
better
Section
which
and,
Some
I. I (b)
called
ways
techniques.
discussed
already
can
a
Figure
now
and
(LSl)
provide
fabrication
LSI
in
integration
technology
of
systems
the
function
array
and
and
can
then
be
used
reassembly,
-6-
The
of
parameters
ways.
The
parameterizing
within
of
each
control
the
state
by
cell.
lines
other
to
methods
programmable
date.
Institute)
will
of
outside
the
array
the
(by
discussed
logic
(PL)
presented
Wahlstrom
[ 44]
detail
in
at
4.
number
by
the
several
one
truly
literature
Stanford
Chapter
a
control
Only
the
to
enabled
I. 2 describes
in
number
memory)
via
and
parameters.)
been
a
refers
gates
function
(Section
these
loaded
Logic
cell
in
(parameter
are
array.
the
in
supplied
flip-flops
cell.
has
be
flip-flops
supplying
array
be
state
state
from
of
may
means
_etermine
logic
This
cell
programmable
from
and
each
term
These
flip-flops
connections
to
Hesearch
to
-7-
1.2
Programmable
logic
and
the
LSI
problem.
,
Efficient
hardware
requires
significant
of
raised
with
and
This
section
LSI.
respect
I. 2. I The
circuit
cost
of
of
these
testing,
etc.
circuit
is
is
due
permits
divided
among
Specialized
in
its
perform
of
16
are
4 inputs,
number
is
in
number
to
of
theoretical
partitioning
manufacturing
excess
of
the
with
and
constraints
the
major
PL
concept
some
design
current
is
issues
discussed
approaches.
to
The
associated
function.
different
functions
on
increase
plane
decrease
in
wiring,
cost
per
components
with
the
as
a
the
slice.
as
more
A device
having
101_different
back-
an
Gf
the
functions
and
decrease
densities
slice,
are
continued
packaging,
increasing
circuits
a
themselves
components.
single
of
show
components
dicing,
the
a
65,536
of
manufacturing
costs
all
onto
any
in
largely
the
absorbed
i
computing
problem.
the
total
to
a
both
functional
several
along
cost
the
be
issue
trends
in
as
applicability
each
of
of
relate
as
well
presents
Current
the
which
as
customizing
in
such
ion
in
repeatability.
The
to
problems
design,
yield
integration
considerat
These
organization,
by
large-scale
careful
machine
processor
as
of
problems.
aspects
such
usage
of
those
possible.
functions.
slice
But
slice
2
becomes
binary
inputs.
With
The
whole
to
logic
more
inputs
If
can
there
6 inputs,
more
complex
the
a
-8-
device
becomes,
given
machine.
(components
per
required
Each
for
as
inventory
affects
represents
and
the
or
costly
failures
exist,
customizing
array{2}.
A
organizing
number
and
of
could
number
Another
problem
of
process
yields
of
centimeter
distributed
different
be
done
as
quite
defect
improved
a
pattern{4}.
by
a
form
by
an
per
as
called
fact
LSI
connections
are
studying
so
are
percentages
If
this
did
not
outside
the
as
that
chip
package)
by
to
the
problem
of
minimize
the
connections[20]{3}.
issue
during
at
component
of
LSI
defect
Yields
at
manufacturing
higher
levels
make
high
customization
an
of
10
of
entire
consider
these
each
the
the
currently
densities
fashion,
concerns
can
Since
of
the
manufacture.
leads
satisfactory.
quasi-random
costs
is
significant
problem
faulty
and
sizes[l}.
design
to
after
occurring
_anufacturers
a
devices
tradeoff
customizing
serious
one
This
designs
the
percent
in
machine
of
20
various
outputs
researchers
form
because
faulty.
be
intra-part
more
of
initial
within
integration
(CPUs)
200
and
a
device
to
Defects
of
different
compounded
and
parts
yield.
are
integration
of
level
of
for
150
partitioning
unique
is
responsible
about
used
problem.
and
during
be
number
costs.
problem
occurring
to
the
significant
part-number
are
(currently
how
units
inputs
and
likely
the
replacement
the
is
shows
processing
supplying
limitation
may
device)
customization
connections
it
1.2
customization
relatively
times
Figure
part
This
of
fewer
central
unique
well
the
the
per
chip
square
failures
slice
will
integration
which
are
have
a
levels
avoids
or
-9-
1000"
05 circuit
CPU
100
Number of
unique
parts
104 circuit
10
CPU
0 3 circuit
1
CPU
10
100
1000
Level of integration
(circuits/part)
Figure 1.2. Level of integration
vs. number of unique parts
-10-
eliminates
the
defective
One
defec
such
technique
t-av oidance
can
discretionary
control
probing
probes.
which
are
w il I
function.
cells
plotter
and
proper
metalization
repeated
for
for
every
production
fairly
is
the
low-volume
proposed
by
method
uses
appropriate
the
tested
points
which
a set
of
cells
are
good
pattern
cells
present
which
is
slice.
The
therefore
photomasks
a
is
form
is
then
drawn
used
above
fast,
to
has
desired
a CRT
produce
sequence
been
or
the
must
inexpensive
To
and
compensate
on
to
fine
which
the
essential.
production
computer
with
to
pattern
called
under
together
are
and
is
a connection
This
made
LSI
technique,
Minnick
for
points
fuses
on
the
damage
larger-than-normal
are
of
commercial
cutpoint
be
method
date,
only
feasible
These
using
currents
has
arrays[22][21].
in
fuses
surrounding
LSI
logic,
cellular
(cutpoints)
chip.
to
slightly
actual
called
customizing
small
(without
known
of
customizing
wiring.
Another
blown
rows
slice,
of
discretionary
cells
on
is
test
generates
ones[41].
photomask
slice
determines
then
or
which
s i multa neously
various
good
defective
a
at
It
only
Extra
the
done
computer
faulty.
by
Each
it
The
connect
for
be
wiring[33].
by
wire
cells.
signal
may
circuits)
through
production
them.
which
be
been
This
paths
at
selectively
by
passing
No
examples
uses
cutpoint
1 og ic.
Both
of
the
above
approaches
are
attempts
to
minimi_e
-11-
customization
stage
in
third
costs
the
by
physically
manufacturing
approach
process.
to
thi s
int erconnec
tions
in
an
flip-flops
which,
in
turn,
state
flip-flops
advantages
of
I)
are
PL
No
discretionary
turn-around
some
mask.
P L,
2)
a
done
procedure
slow-write
hold
the
virtually
a
the
fault
these:
are
required
in
These
the
as
of
to
be
can
with
cost
and
wiring
application
avoidance
setting
Briefly,
are
need
and
cells.
savings
currents
and
the
discretionary
during
unusual
can
be
function
at
corresponding
problem
The
disturbance
mechanism
allows
yield
array
different
customizing
I)
masks
a
often
the
final
present
take
and
place
at
speeds.
The
The
be
in
no
or
by
array.
customizing
addition,
customization
element
perform
In
loss
With
functional
logic
This
time.
involves
to
the
late
functions
within
outside
a
provides
determined
gates
alterations
wiring.
be
at
logic
Cell
can
from
slice
Programmable
control
respect
physical
the
problem.
array
loaded
with
customizing
for
some
reloading
reprogrammed
to
time.
of
operation
power
the
"program
like
the
used
with
pre sen t- da y
stored-charge
is
might
much
eliminated,
later
be
PL
with
respect
to
the
are:
electrical
parameter
and
disadvantages
customizing
of
altered
initial
type
of
is
permanent.
occasionally
into
an
machines.
memory
commonly
done,
or
necessitate
This
program
a
could
loading
_ Iternatively,
element
Power
_ loss
array.
supervisor
information.
as
U
not
sight
failures
by
the
use
a
be
used
to
can
also
be
of
back-up
-12-
power
sources.
circuitry
can
remain,
some
of
2)
extra
logic
10
up
each
1
transistor
per
which
The
each
extension
small
on-site
monitored
shipping
and
be
power
required
controlled.
loading
propagation
must
of
a programmed
program
extra
is
be
slower
into
signal
LSI
problems
In
probably
often
by
Some
device.
will
introduced
gates,
significant
in
5 to
in
amount
general,
desirable.
because
paths
of
to
the
control
tions.
3)
up
small
easily
Signal
gates
i nt erconnec
of
be
however,
form
use
The
amounts
cell
or
more.
of
the
logic
can,
of
in
flip-flops,
area
some
on
the
cases,
control
lines,
slice.
be
The
increased
should
be
noted
that
this
current
trend
of
using
more
transistors
element.
gate
commonly
Many
and
use
second-generation
4
or
5
gates
5 transistors
per
a
gate
and
can
be
is
to
used
flip-flop.
of
factor
increase
maclhines
per
etc.
amount
by
It
per
ICs
state
an
make
only
Today's
6 to
8 gates
flip-flop.
In
during
addition,
run-time
would
permit
given
task.
possible
concept
a
perform
computer
Greatly
over
is
to
however,
today's
unfortunately
PL
arrays
different
to
alter
increased
beyond
functions.
:its own
efficiency
fixed-structure
the
reprogrammed
This
structure
is
machines.
scope
of
to
suit
theoretically
This
this
ability
work.
interesting
a
-13-
1.2.2
Testing.
Effective
utilization
of
distinct
LSI.
input
exhaustiwel
tested
This
is
a
gross
pads
silicon
area.
tend
A
high
the
is
make
number
of
of
of
be
best,
as
component
The
great
probing
less
researchers[1_][40]
I/3
and
and
[I]
the
the
number
of
in
order
to
current
mentioned
area
as
densities
in
Nost
technique
however.
sometimes
concern
applied
astronomical.
probing
internal
serious
integration,
must
becomes
at
Increased
to
levels
internal
method
alone
a problem
which
a slice
using
testing
At
is
patterns
T test
are
layers
testing
taken
of
more
less
are
above.
Qp
the
ICs
by
the
available
metalization
attractive.
presently
involved
....
with
the
testing
problem.
pessimistic
results
connections
only
assumed
defect
other
fixed
to
cells
concerning
at
the
structure
obscure
in
Tammacu[40]
the
some
array.
testing
edges
of
other
has
of
these
the
arrays,
faults
or
of
given
some
regular
array.
it
prevent
relatively
arrays
Because
is
using
of
possible
testing
the
for
of
some
a
-14-
Programmable
with
respect
I)
designed
in
PL
effect,
variability
and
bypass
2)
and
physical
to
logic
the
testing
Efficient
arrays.
to
allows
them
Edge
and
is
probing
of
to
possible
state
recommend
sequences
test
slice.
the
to
with
parameters
connections
permits
the
is
because
break
thoroughly
testing
advantages
it
problem:
testing
to
several
edge-testing
This
make
has
in
the
can
properly
be
circait.
disconnect
used,
This
faulty
cells
array.
elimination
of
testing
pad
area
-15-
1.2.3
Alterations
As
design
software
systems
not
a state
debugging
more
by
continual
changes
metalization
severe
on
at
higher
time
of
IC
the
be
complex,
Not
a
piece
service{5}.
point
is
much
changed
again.
_Iterations
and
difficult
with
Thus
debugging
changed
more
of
Large
where
exists.
cannot.
of
in
system
course,
chip
levels
the
often
can
more
difficult.
useful
reached
the
wiring
an
and
discovered
of
debugging
are,
Back-plane
is
years
already
complete
of
hardware.
error
given
have
more
increasingly
obscure
has
really
becomes
becomes
an
which
but
hardware
validation
hardware
Thus
repairability.
computing
infrequently,
is
and
some
the
in
difficulty
problem
becomes
integration.
•
One
assurance
approach
of
hardware.
can
to
the
circuital
are
circuits
a
crucial
Programmable
to
the
most
has
hardware
is
factor
logic
in
it
is
is
or
far
times
those
a
maximum
committed
by
not
design
building
been
shown
parallel
at
not
practical
on
models
on
laboratory
along
to
highly
Breadboard
on
propagation
thus
usually
approximating
achieve
provide
automated
simulation,
computers.
lengths
impossible
high-speed
often
wire
serial
to
before
Simulation
simulation
in
is
employing
extensive
level,
limited
that
by
Since
essentially
are
done
task.
today's
chip
be
"breadboards".
adequate
problem
correctness
including
laboratory
this
design's
This
techniques,
the
a
to
the
are
actual
bench.
these
very
IC
For
connections
design.
can
provide
the
ability
to
easily
-16-
alter
hardware
capability
greatly
problem
more
functions
and
--
and
discretionary
entire
etc.,
unit.
can
be
reliability
([41],
In
existing
levels
can
circuits,
to
this
redundancy
and
summary,
will
then,
has
the
of
be
in
to
with
be
integration
terms
make
of
failure
necessitate
replacement
majority
voting
somewhat.
been
much
potential
both
in
a
of
techniques,
Enhancement
discussed
explicitly
made
run-time
transistor
problem
not
comes
problem
single
correctness
additions
Higher
array
lessen
and
design
This
elsewhere
considered
advantages
of
here.
of
PL
over
are:
Electronic,
rather
than
physical,
customizing
and
enhancement.
2)
3)
design
A
manufacture.
the
bonus
Redundant
example)
methods
I)
yield
used
of
important
serious
cutpoint
through
for
more
repair.
or
after
improvements
more
a
time
severity
repairability.
failures
diagnosis
the
a
any
the
allows
But
variability
run-time
reduces
also
easily.
at
8ore
efficient
Functional
correction,
fault
edge-testing
variability
repairing
and
after
and
fault
diagnosis.
manufacture,
machine
including
restructuring.
-17-
The
discussed
following
disadvantages
are
inherent
to
PL
here:
I)
Significantly
increased
amounts
2)
Propagation
delays
are
])
Customizinq
is
physically
of
logic
are
sometimes
r eq uired.
not
increased
5y
added
permanent.
gates.
as
-18-
I. 3 The
n-space
We
arrays
has
by
have
on
these
points
In
efforts
be
of
only
be
the
choice
thelr
Thus
the
an
uncharted
section
described
of
in
any
of
abstract
will
be
discussions
characteristic
properties
the
unless
cellular
cases,
logic
emphasis
uniqueness
has
such
a
which
been
of
the
given
to
comparison
exist
are
is
mainly
attempt
to
relate
hypot[hetical
A
some
few
rough
What
is
to
serve
space
of
of
some
of
these
dimensions
these
of
dimensions
measure,
but
at
as
dimensions,
the
can
most
really
issue
an
can
here
is
not
precision.
axes
the
will
by
characteristics
these
attention
designs
arrays.
qualitatively.
quantitative
in
we
of
space.
several
logic
of
and
other
array
number
most
little
each
quantitatively
meaningful
a
in
cellular
As
noted
Usually
describing
grasped
In
a
capabilities
to
this
by
n-space
the
arrays.
referenced
arrays
unavoidable{6}.
isolated
far
question.
relating
logic
researchers.
placed
in
cellular
thus
previous
been
array
of
the
ca n
array.
orthogonal.
which
be
follow.
examined
this
Many
kind,
not
dependencies
Indeed,
it
independent
is
ly
all
will
seldom
of
the
be
that
other
-19-
].3. ] Generality.
This
work.
the
primary
Generality
variety
given
one
is
of
functions
various
sets
level
sense,
array
we
a
choose
to
characteristics
strong
customization
of
problem
of
the
generality
no
variability
the
array
of
inputs
and
for
of
generality
to
dimension
the
t hese
devices
is
any
and
strongly
range,
the
is
various
all
(i.e.,
any
tlhe other
exists
a
range
of
part-number
At
fixed
extreme
one
or
extreme
function
are
with
arrays
efficiently.
the
In
with
the
1.2.1.
simple
to
states.
there
the
and
performing,
all
addition,
functions
related
of
associated
and
this
number,
pervades
other
orient
control
strongly
the
the
we
capable
Section
have
At
to
generality
in
we
which
In
between
discussed
around
property
here.
all.
perform
is
This
scale,
at
refers
which
mentioned
a pp lica bill ty )
this
array
create.
relationship
attempt
an
of
dimension
which
Clearly,
programmability
of
the
array.
In
t he
attempting
real-world
usefulness
course,
of
a
units
have
power
to
however,
certain
the
in
is
which
functions
general
the
high
a
measure
costs
highly
efficiently
to
we
parallel
generate.
but
it
can
sense.
The
generality
in
they
structures.
that
computer.
efficient
on
the
few
IV[3]
are
each
The
aggregate
a class
of
neglect
machine
perform
ILLIAC
cannot
efficiency
A Turing
real-world
really
we
represent
machine
general-purpose
only
generality,
and
is,
of
functions
processing
equivalent
problems
:in
machine,
having
-20-
It
speak
of
have
a very
the
by
also
means
of
other
hand,
the
a
of
this
of
any
of
the
connected
in
One
a
of
as
from
which
the
device
the
cell
real
in
cost
how
have
are
reflected
many
in
a
Chapter
4 which,
depending
their
inputs
and
upon
outputs,
being
and
cases,
goals
array
to
is
cells
grid.
the
range
of
about
as
capable
The
Increased
at
the
generality
to
the
generality
functions
the
as
functions
array
important
area,
arrays
design.
can
serve
designed
unneeded
can
the
fixed
perform.
low-generality
the
is
wide
semiconductor
design
a rectangular
required
fundamental
In
on
knowledge
to
generality
several
specific
specific
required
money,
very
goals
be
for
obtained
a
variables.
definition.
needs
be
with
match
may
structure.
cascade
device
array
ion
in
fewer
may
generality
might
the
we
high
arrays[18]
2 or
the
attain
cascade
process
task
of
designs.
time,
discuss
the
of
level
array
of
An
function
cell
of
design
lack
degrees
resulting
will
any
will
cell
that
machine.
generality
configuration
specific
a
of
Each
example
interconnect
Maitra
functions
by
from
The
The
a
yet
flexible
level
IV
in
and
general
fiKed
required
result,
at
same
power)
well
we
16
functional
may
very
approach.
goal
generality
a
ILLIAC
levels
function
structure.
example
the
various
fairly
an
one
from
cell
by
interconnection
(or
at
specific
combining
are
clear
generality
overall
On
is
be
effects
etc.
In
and
attempt
Cells
synthesize
and
and
on
generality
realized
permutations
level
the
has
Chapter
to
how
a
3,
show
these
are
presented
in
and
negations
of
many
different
-21-
functions.
I. 3.2
Size
(logical).
The
of
the
size
array
description
an
a cell
extreme,
the
large
I. 3.3
in
thr_
possible
are
IV
are
components)
obvious
general,
complex
computer
only
a regular
and
hexagon),
of
the
arrays.
more
of
can
we
are
be
and
the
parameters
can
its
say
in
that
the
functions.
thought
of
as
ways
arrange
size
the
more
At
an
one
array
o:f
geometry.
cells
where
unique
on
a plane.
by
each
its
Also,
geometries
approach
(not
regular
vertex
affects
way.
three
pattern
coverings
array
interesting
cells)
In
the
ILLIAC
(number
of
array.
is,
There
certain
cell
cells.
Array
analogous
the
(number
of
complex
very
of
These
polygons
represents
a
necessa['ily
pattern
functions
identical
correspond
to
(triangle,
cell.
interconnection
certain
to
to
The
square
geometry
possibilities
are
symmetric).
transformations
better
See
using
the
in
suited
[10]
for
hexagonal
an
to
an
-22-
1. 3.4
Cell
function.
Several
affect
be
the
properties
capabilities
possible
to
interconnection
binary
given
can
of
is
of
also
an
of
array
n-bit
full
in
each
then
be
This
be
the
complexity.
in
the
large
interacts
while
cell
number
of
For
any
which
a
cell
array.
example,
of
the
has
very
few
of
the
16
all
On
the
additions
strongly
structure.
structure
cell
number
the
functions
a flip-flop.
The
by
nearly
parallel
from
not
other
might
hand,
have
components
per
variability
of
an
cell
the
zero.
interconnect:ion
interconnection
var iables
cell.
essentiall_
dimension
also
for
fairly
of
may
a function.
the
for
function
cells it
ordered
of
of
cell
function
forms
variety
measure
and
adder
would
cell
synthesis
strictly
function
be
or
some
cell
celi[22],
designed
could
the
permits
2 variables
nucleus
including
the
useful
nucleus
(In
may
the
cutpoint
but
cell
array.
Cells
which
a
the
separate
variables,
Minnick's
functions
the
control.)
number
components
of
entirely
variables
perform
of
varies
function
with
Usually,
directly
and
in
with
several
the
the
proportion
others
density
of
number
of
to
its
-23-
1.3.5
Interconnection
Arrays
may
int erconnection
structure
any
paths
strong
through
be
that
used
in
up
as
to
and
The
and
This
a
passing
it
signal
flexibility
in
symmetry
any
the
in
(east)
and
south
last
exists
in
down
their
of
this
paths
from
and
this
direction.
Interconnection
by
Lines
wire
column,
never
which
Notice
can
left
compass
allows
only
(west)
points
by
to
neighbor
a
Figure
move"
neighbor
alternative
connections
bus.
propagating
shows
but
buses.
no
line
in
to
or
Much
1.3(c)
Each
east
nearest-neighbor
an
variables
width.
propagation
a "knight's
connections
path
Several
signals
the
via
for
Example
nearest-neighbor
use
provides
column
array
or
these
1.3.{7}
continuous
row
called
of
array.
Figure
south
by
cell
entire
the
1.3(a)
1.3(b)
west
to
a
be
grid.
connection
cell
of
will
geometry
(so_th),
to
Figure
and
and
its
Figure
a rectangular
west
--
direct
array
in
in
continue
buses,
an
bus
cell
cell
in
from
:in the
shown
a
each
The
properties
are
shall
on
along
other
among
2)
by
right
on
connection.
to
properties
direction
indicate
structure
connections
passing
on
input
We
cells
number,
graphs
directions
south
basic
complexity.
nearby
outpoint
the
The
than
other
a cell
(north).
indicate
path
effects
an
the
propagate
or
to
connection
passing
according
interest:
connections.
possible
can
of
cell
have
delineated
Three
Interconnection
given
neighbor
be
structures.
are
1)
structure.
to
more
south
complete
Figure
1.3
-24-
I
(a)
_
_"
;
dr
dr
_r
q'
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_P
(b)
(Minnick's
T
(C)
(Minnick's cutpoint cell)
_
I
LT
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.
I_
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i_
IN'I
cobweb cell)
T
(complete nearest-
neighbor connections)
Figure 1.3. Several interconnection structures
-25-
may
represent
simple
one
connection
transmit
many
3)
may
permit
and
outputs
way,
bits
set
of
of
its
a
parallel
at
simply
and
Chapter
3,
register.
The
4
of
paths
to
a
the
shift
nearest-neighbor
arrays
which
simultaneously
It
should
throQgh
be
clear
a
at
the
which
whose
of
a
is
larger
cell
and
nucleus
outputs{8}.
a small
taken
Chapter
this
the
cell
and
be
forming
In
Kautz[15]
no
nucleus
In
inputs
from
of
have
may
cell,
through
inputs
register
a cell
cell.
nucleus
inputs
array
capable
might
within
the
networks
cells.
are
to
of
its
arrays
cell
with
function
control
inputs
cell
between
present
input
The
sorting
as
array
cells.
to
other
An
cell
outputs
inputs
The
thought
we
and
route
parallel.
complex
between
the
and
form
in
between
nucleus,
choose
be
data
variability.
outputs.
can
patlhs
and
inputs
to
several
paths
cell
might
cell
the
of
connections
the
Batcher[4]
of
bits
in
various
directly
all
more
Interconnection
a cell
In
or
4,
shift
from
we
several
any
I
describe
different
cell.
this
point
that
the
interconnection
•
structure
is
mentioned
here.
(COF)
to
as
the
used
arrays.
as
the
number
an
heavily
In
to
particular,
ratio
in
related
of
the
indicator
the
we
total
define
number
nucleus
or
of
design
cell
most
cell
of
the
of
the
other
cel_____l
overhead
components
function.
efficiency
dimensions
in
The
for
COF
some
factor
the
cell
will
be
types
of
-26-
1.3.6
Degree
It
and
type
of
is
of
also
On
array
cells,
no
which
forming
arrays
register
bits
memory,
lit
generally
degree
called
of
parallel
bit
Kautz[16].
by
their
each
group
The
-scratchpads,
of
Words
with
bits.
at
highest
the
In
Although
data.
arrays
form.
time
degree
are
of
],
have
any
most
of
The
etc.
is
number
of
shift
cell
where
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higher
basically
sorting
can
be
with
array
ordered
retrieved
the
no
be
arrays
included
later
simply
--
are
may
of
yet
the
array
and
of
shift
class
logic
writing
capable
of
represents
memory
cutpoint
class
each
processing
memory
memories,
a
of
combinatorial
are
arrays
this
of
the
and
point
Minnick's
is
amount
particularly
this
but
example
the
endpoints
These
such
a
from
serially.
into
the
can
some
is
is
Chapter
which
One
written
scale
Nearby
well.
to
well-defined
combinatorial
cellular
associative
on
all.
This
discussed
memory
cell.
but
magnitudes
sequence.
be
accessible
in
according
cell.
its
"logic-in-memory"
memory,
or
the
presented
only
memory
of
performed
in
each
can
at
as
is
is
of
arrays
of
basically
flip-flops
register
each
end
memory
are
in
arrays
low
having
order
because
existing
the
to
contained
dimension
many
view.
useful
memory
interesting
because
memory.
memory
function
in
array
is
-27-
1.3.7
Defect
density.
Cellular
perform
useful
defects
may
is
required
3,
we
will
errors
designed
level
tradeoff
is
lower
discussed
in
detail
by
the
of
yield
a
requires
interconnections
cells
more
errors
and
such
communication
rows
are
outputs
a
size
may
order
of
expected
to
the
that
have
the
to
near
may
long
buses
be
done
be
via
Arrays
zero
may
of
raised
of
cell
to
any
those
This
to
is
a considerable
expected
(a
during
greater
its
number
path-building
around
in
edges
of
possible.
are
be
3.
necessary
array
between
testing.
yield
the
view
intitial
signals
be
of
percentage
influenced
route
Chapter
discarding
which
may
point
yield
In
simply
Chapter
cell
These
percent
array.
elaborate
to
cells
the
to
operation.
difference
by
is
lower
more
in
or
array
100
artificially
percent)
environment
Clearly,
defects)
Spare
an
defects.
certain
be
in
of
actual
From
a
ability
intolerable.
per
at
their
that
large
may
is
manufacture.
of
yield
yield
design
is
obviate
100
The
such
a
by
during
expected
(including
whose
or
arrays.
is
errors
course,
presence
failure
such
to
ranked
designed
there
more
be
the
cell
several
or
Of
be
one
specifically
desired
inputs
may
even
one
failures.
extent
manufacture
designer
and
arrays
during
present
array
also
in
arrays
and
may
functions
occur
Some
the
arrays
faulty
some
the
If
failure-
neighbor
and
cells.
arrays.
array,
the
_rone,
connections.
of
If
fewer
array
is
most
-28-
I. 3.8
Degree
By
program
among
of
commutativity,
itself
arrays
In
for
cell
outside
each
cell
various
the
fed
in from
step-wise
fashion
successor
until
array
the
of
future
research.
itself
it
its
must
cell
control
will
themselves
be
simply
by
bits
of
one
program
the
Each
was
and
cell
in
allowing
more
of
its
according
to
in
instruct
The
Chapter
be
solel_
propagated
would
programmed.
discussed
or
itself
array
some
lines.
might
done
to
common
have
than
of
array
not
rather
array.
Wahlstrom[44],
a
its
_rogrammable
4,
possesses
ability.
Another
self-healing
processor
within
edge
is
array
cells,
might
the
entire
and
an
other
state
one
across
for
of
which
connections
This
array
ability
property
paths
by
the
the
a
program
and
times
to
Then
parameters
to
data
array.
access
neighbors.
array
its
is
the
promise
functions
at
from
this
an
mean
This
holds
between
controlled
logic
which
order
some
we
internally.
but
connections
Thus
co mmutativif.y.
possible
within
might
itself
Capabilities
of
be
an
use
of
array.
capable
A
of
and
re programming
this
kind
are
commutativity
beyond
is
sufficientl_
detecting
around
the
some
complex
failures
the
scope
•form
which
offending
of
this
work.
of
array
occur
parts.
-29-
I._
Overview
It
should
this
be
is
array
will
is
of
is
this
a
major
contention
tailored
to
that
effort
any
the
misdirected.
attempt
to
accomplished
assumptions
PL
2
plus
assigned
examples.
modes
this
objective
task
to
a
design
some
in
set.
that
An
any
the
which
of
cellular
following
this
design
implication
highest-generality
in
ways
thesis
chapters
tailoring
we
may
be
arrays.
presents
a
set
relative
Distributions
failure
of
Therefore,
show
with
Chapter
their
work.
are
also
some
of
preliminary
logic
costs,
of
definitions
elements
which,
will
used
be
manufacturing
discussed
in
and
together
in
the
defects,
relation
following
yields
to
with
the
and
testing
problem.
Low-generality
Properties
related
significantly
detail.
of
the
to
different
Comparisons
same
arrays
functions.
are
are
considered
low-generality
examples
made
with
are
are
more
in
discussed
presented
conventional
and
Chapter
3.
and
two
analyzed
realizations
in
-30-
Chapter
arrays.
Severa
s tructure
and
example,
in
the
Characteristics
discussed.
terms
_ addresses
cell
control
of
a
PL
detail
m icroprogra
new
function
logic
and
for
Control
comparisons
of
to
approaches
for
a
are
synthesis
the
interconnec
are
is
machine
made
with
PL
are
presented.
processors
small
in
array
to
problems
central
high-generality
tion
As
approached
is
an
in
implemented
conventional
mined control.
Chapter
r es ea rc h.
important
I
array.
problem
5
gives
conclusions
and
suggestions
for
further
- 31 -
Foot no tes
0)
in
the
Numbers
including
This
[32]
2)
commonly
ind:icate
shift
the
n replaced
references
cited
(Fairchild
actual
to
logic
several
origin
the
to
not
known.
microprogramming
by
and
concept
gating
controlled
arrays
publications,
is
Register
centrally
goal:
in
and
commands
various
from
microprogramming
regularize
unstructured
a
have
control
_.5.
we
n-bit
register
shift
would
lines
can
on
leads
register
cequire
the
Section
trade
for
at
only
the
programming
edge
one
input
a discussion
of
of
and
the
speed
slice.
would
drive
slice.
2.2
for
the
distribution
defects.
5)
LSI
are
crucial
See
its
today.
Cellular
an
appeared
similarity
Furthermore,
including
_)
but
machines
Section
This
an
in
one
See
these
the
memory.
common
has
[29],
operations
3)
of
and
Note
data
logic.
by
diagram
used
read-only
in
brackets
bibliography.
I)
other
in square
At
this
device
3751
writing,
produced
12-bi%
a
for
A
to
bug
some
has
recently
months
D converter).
by
been
a
major
discovered
manufacturer
in
-32-
6)
For
7)
_iI
two
dimensions.
an
array
are
a
arrays
arrays
if
to
see
date
connections
made
[24].
have
to
feasible,
been
the
restricted
interior
of
three-dimensional
to
such
arrays
possibility.
The
an
interesting
exceptions,
cellular
eventually
distinct
in
notable
However,
are
8)
fully
some
networks
earlier
to
which
note
are
published
report
that
from
these
virtually
by
Batcher
Goodyear
two
described
more
Aerospace[35].
researchers
identical
are
have
except
for
It
studied
a
45
is
some
degree
....
rotation
of
the
paper
conceptualizations
references
the
of
other.
on
which
them
are
they
very
are
drawn,
different
yet
and
their
neither
-33-
Chapter
2
Assumptions
This
and
chapter
notations
logic
is
blocks.
defects
are
discussed.
conclude
PL
arrays
by
have
a
with
present-day
future.
circuit
etc.
good
Several
literature
are
cell
array
to
here
construct
and
assumptions
on
arrays
depth
testing
and
restricted
at
of
applies
we
or
to
We
although
In
fact,
crossover
will
attempt
that
of
slice
capabilities,
LSI
cells,
permits
work,
technology
of
technology.
impossible.
which
this
are
current
intrinsically
summaries
restrictions
capabilities.
by
the
of
to
be
clearly
areas,
yield
propagation
times,
technology
are
the
match
One
such
definition,
needed,
either
or
must
they
used
comments
by
planar
drive
improve
are,
of
are
available
in
[32] [9][11][_7].
Certain
substantially
imposed
Th is
probabilities,
A system
Several
considered
limited
Throughout
foreseeable
be
not
etc.{3}
be
Some
2-dimensional
today's
an
to
are
,
chapter.
constraints
only
ICs
the
definitions
follows.
logic
arrays
technical
which
other
3-dimensional
the
work
and
consider
consistent
the
assumptions,
arrays
levels
signals,
to
some
will
The
will
present
topics
which
diagnosability
various
preliminary
described
PL
concerning
will
pertaining
elements
evaluate
and
they
be
in
2
between
be
the
restriction
identical.
must
adopted
If
combined
separate
arrays.
design
is
2
to
because
that
different
form
This
they
and
existing
all
cells
cell
a single
in
types
larger
restriction
is
-3 _-
imposed
because
which
can
lower
cost
of
produce
than
edges
IC
slice
Thus
of
of
cannot
all
the
the
control
step-and-repeat
much
other
Similarly,
the
the
higher
photomasking
densities
over
technique
larger
areas
at
to
be
at
to
an
processes.
we
restrict
array.
be
paths
At
done
and
all
external
present,
bonding
at
data
arbitrary
paths
connections
of
points
must
connections
within
originate
the
at
slice.
the
edges
array.
In
introduced
realizations
the
following
section,
which
is
related
in
integrated
a
to
set
and
electronics.
of
logic
restricted
elements
by
will
physical
be
-35-
2. I Evaluations
and
Yarious
complexity
with
ways
of
elements
is
to
some
earlier
count
may
suffice.
today,
however,
fan-in
and
functions
(RS,
A
D,
JK,
flip-flop
functions
would
could
the
a
of
With
be
wide
or
slice
any
range
of
gates
and
complexities
logic
of
elements
are
at
system
digital
(i.e.,
of
types
suited
encompassed
component
no
longer
the
gate
level,
and
exact
their
of
flip-flop
a certain
the
at
task.
different
but
this
reliability
our
but
fan-out
being
and
focusing
of
different
available)
usage
form
currently
all
commercially
gate
a range
and
type
for
case
integrated
in
ways
logic
a simple
have
are
Each
a
was
fan-in
non-trivial
are
the
costs
flip-flop
which
as
or
attention
on
the
of
level
itself.
flip-flops
aggregates
logic
from
we
addition,
particularly
of
in
Gates
arbitrarily.
built
problem
Thus,
complex.
In
in
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LSI,
part-number
chip
is
inefficient
standpoint.
the
etc.)
(indeed,
be
of
chosen
available
cost
family
then
relative
differ
not
RST,
more
different
flip-flops
small
computers,
circuits
number
a
relative
machines,
capabilities.
&
the
If
entire
somewhat
system.
measure
circuits.
construct
have
were
to
Logic
fan-out
These
exist
logic
transistorized
are
technologies.
used.
standard
digital
used
v aria bilit y
the
these
logic
and
costs)
elements.
which
will
which
intends
functions
a method
to
must
for
elements
Figure
be
used
to
2.1
efficiently
provide
:for a
assignment
in
shows
throughout
the
cover
of
relative
system
the
this
range
and
to
standard
set
work.
The
-36SYMBOL
t
,
,
DESCRIPTION
C-UNITS
(non-inverting,
n-input
AND gate can
2_n_4
only drive I OR input)
n-input NAND gate
n-input NOR gate
I_<n_<4
I_<n<4
n
n+1
n+1
RS flip-flops
6
or shift flip-flop
D flip-flop
6
JK flip-flop
8
RST fl ip-flop
8
Figure 2.1. Standard set of
logic elements and their c-unit values
-37-
set
contains
range
or
of
I
to
logical
since
2
basic
4.
NOT.)
the
(K
l-term
In
addition,
AND-NOR
present-day
These
c on form
were
introducing
sections,
in
The
or
related
to
all
I)
vague
gates
and
have
a
as
in
column
a
unit
an
three
the
costs
in
we
are
thus
to
compare
2)
"Complexity"
nearly
an
inverter
is
included
all
types
and
are
above,
any
be
also
these
particular
without
evident
is
the
functions
possibilities
will
the
from
their
stated
of
in
later
a significant
arrays.
Figure
2.1
define
of
-"cost
It
is
gives
the
a
value
to
c-unit.
unit"
or
intended
each
A c-unit
"complexity
as
a
measure
these.
_cost"
world
of
are
hard
in
flip-flops
unit'.
that
way
of
now
gate
represent
Rs
of
AND
a fan-in
abstractions
existing
abbreviation
of
LSI
as
As
logic
_component
Notice
term
real
of
even
the
simply
types
to
use
programmable
terms
taken
not
the
right-hand
in
be
in
is
with
flip-flop
viewed
inefficiencies.
economy
consideration
basic
be
cover
each
available
de finitions.
to
undue
gate
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chosen
but
NOR,
non-driving
is
may
and
NOR
Four
usual
implementation,
the
function
the
f lip- flops
or
a
commercially
to
unit"
NAND
flip-flops
corresponding
may
NAND
realizations.
included.
element
gates,
LSI
not
to
(even
and
particularly
directly
subdivide
logic
relative
in
associated
to
blocks
cost)
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that
PL.
with
level.
differ
is
very
Nany
of
individual
Yet
only
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at
we
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the
gate
I ev el.
of
circuital
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only
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to
actual
properties
cost
as
well
in
terms
--
for
-38-
example,
number
the
important
of
likelihood
of
a failure
logic
within
in
arranged,
most
related
of
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to
exist
failure
both
MOS
ICs)
and
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cost
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rela tire
building
blocks
a single
component
nearly
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element.
amount
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the
the
element
the
values
&
of
Section
about
thus
the
most
electronic
(see
require
to
entire
between
_nd
circuit.
circuit.
of
the
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components
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Failure
to
probability
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a given
failure
seems
the
are
in
points
lexity
elements.
results
relationship
and
comp
_Components"
digital
always
crossover
a ii,
of
3)
of
circuit
2.2).
same
strong
area
Properly
amount
of
area
number
of
components
is
and
its
likelihood
of
failure.
It
is
represent
the
believed
best
cost,
complexity,
values
have
t eras
discussed
the
these
and
actual
Figure
2.1
relationships
above.
following
other,
count
with
in
to
The
given
justifications:
values
are
realistic
cost
in
commercially
in
ICs.
Certain
c-unit
values.
c-unit
value
3)
number
with
each
component
2)
the
to
shown
correspondence
components
assigned
Relative
of
available
available
and
beem
I)
that
most
important
(See
For
outputs
)
identities
2.2
two
for
of
produce
these
and
identical
examples
of
exists
with
one
of
number
of
inputs
+
assignments.)
gates,
commonly
of
Figure
logical
_
a
used
=
fan-in
close
close
cost
+
correspondence
functions
--
I.
correspondence
exists
with
several
IC
-39-
.
A
•_
C__D
•
i
is equivalent
AABVCAD
2 gate
delays
complexity
= 9
complexity
= 9
complexity
= 6
complexity
= 6
to
A
,_
AABVCAD
_
2 gate delays
£
1
,i
0
is equivalent
to
S
1
6
0
Figure
2.2.
Examples of cell
complexity
technologies.
most
{I}
cases
c-unit
equal
value
In
fact,
to
the
is
also
relative
5)
terms
and
bias
units
which
changes
6)
additive,
in
the
driving
rules
to
be
the
each
for
that
component
of
actual
same
these
uninfluenced
in
The
for
a
TTL
element.
A
intentional.
physical
of
is
circuit.
count
the
is
element
realizations
elements
by
(in
permits
normal
the
improvements
etc.
values
is
are
of
etc.)
technology,
system
count
NO S technology
area,
the
for
realization
from
follow
Since
I/3
toward
of
value
component
logic)
Independence
of
analyses
NOS
c-unit
about
(transistor-transistor
slight
the
are
easy
integers
to
avoided
work
and
the
with.
without
combinations
Complex
sacrificing
are
loading
a close
and
link
to
reality.
One
any
inverting
It
of
10
limit
be
the
the
array,
the
as
wired-AND
elements
to
be
as
fan-out
drive
long
as
function
gates.
a
the
is
Most
a function
also
of
bus
real
within
assumed
actual
assume
this
that
the
be
time
arbitrary
to
array
limit
possible
realizations
through
delays.
fan-out
this
impose
circuits.
fan-out
to
gate
practice,
necessary
overall
of
an
In
is
propagation
two
that
output.
it
the
require
noted
but
may
will
defined
every
,ith
permit
We
also
restrictive
array
simple
is
Flip-flops
should
consistent
to
delay
gate.
applies
seldom
A
gate
limit
some
A gate
or
limit
will
finite
internal
leading
out
is
not
exceeded.
at
the
output
of
these
of
of
logic
type.
the
actual
circuits
for
these
- 4 I-
elements
are
to
excessive
draw
discupt
the
designed
power
in such
power,
to other
a way
disable
cells.
that
a
failure
a _ power
bus,
is not
or
likely
otherwise
-_2-
2. 2 Yields
and
Tihere
integrated
to
of
or
their
output
its
A
its
for
them
which
:it will
beyond
can
not
be
occur
in
necessary
a description
of
the
state
will
one
in
in
Section
is
one
in
which
which
at
2. I)
at
least
of
by
the
logic
description
of
its
input
variables
The
also
defined
is
is
least
I
produced
variables.
cell
defined
some
element
(as
input
variables.
derivatives
defects
purposes,
logic
defective
(as
control
our
value
of
value
produced
of
characterize
defective
state
2)
types
For
output
some
defects.
effects:
A
incorrect
of
many
circuits.
I)
for
are
identify
range
distribution
words
be
"fault"
used
with
and
the
for
I incorrect
the
cell)
is
some
state
of
"failure"
same
and
connotation
their
as
the
a bo ve.
Notice
defective
that
logic
elements
not
affect
the
or
wires
between
par ts
of
the
connection
may
be
cell
in
two
consideced
as
We
long
will
elements
s
or
cells
is
4
utilized
in
as
defective
define
cells
defective
or
cell
array
in
any
c-unit
or
do
an T connections
(except
one
have
states
buses)
to
be
Thus
if
a
respectively.
faulty,
an
may
cell
the
also
or
cells,
faulty.
be
(non-defective)
it
outputs.
element
may
good
logic
between
functional
a
both
which
of
of
the
cells
:is partially
its
functional
states.
i
In
effort.
Section
To
avoid
2.1
we
dealing
defined
with
the
the
actual
unit
components
of
circuital
making
up
a
- _]-
1 ogical
element,
h ypothetical
meaning
for
slice,
we
probability
of
a c-unit
assumption
independent
certain
is
c-units
m
areas
by
that
on
the
=
the
a
P=
p
likelihood
of
With
periphery
real-world
has
have
1-p
slice.
the
of
will
the
good
is
like
on
define
defective
independently
c-units
first
being
being
location
ann lyses
analyses
We
c-unit
Justified
fail
complexity
defect-free
of
these
here
high-failure
assumption
failure
c-units.
=
that
of
of
a given
this
cell
aggregates
implicit
our
practice,
of
of
assume
In
probability
is
exception
base
=
An
failure
will
c-unit.
only
p
we
the
of
experience.
one
another,
probability
the
If
then
of
a
being
of
m
If
p
is
close
enough
to
I,
we
have
.,
= p =
P
or
the
p<0.01,
better.
today's
1 og ic
familiar
the
exponential
value
technology
e le me nt s.
of
and
- e
distribution
approximation
This
-up
(l-p)
is
?
is
is
accurate
of
to
well
within
necessary
for
random
within
the
any
defects.
I/2
percent
capabilities
useful
number
If
or
of
of
-44-
Several
h ave
presented
independent
and
higher
than
useful
at
the
4
slice
those
this
is
to
show
that
tend
to
cluster
,
area
of
functional
Hypothetical
postulated
and
they
were
laid
area
of
the
researchers
with
slice.
represents
variations
reasons).
asymptotic
for
the
to
comparison.
published
Two
the
and
the
4,
8,
by
inner
I of
on
after
this
probe
boundary
The
etc.
cells
these
the
of
the
Cell
edges
data
The
due
have
shaded
to
proprietary
which
data
as
of
largely
for
were
if
statistical
sizes
comparison.
distributions
be
non-statistical.
within
(necessacy
will
cell
counting
summary
experimental
yields
analysis.
being
uncertainties
data
on
the
2.4.
easier
exponential
bounds
The
patterns
Figure
for
2,
cell
shows
shown
as
calculated
condensed
in
c-units
I,
regular
A
given
into
other
in
chip
in
rejected
of
yields
out
translated
are
used
quite
2.3
Each
packaging.
slice
areas
their
is
of
each
area
ICs
and
IC
not
It
Figure
Petritz.
conventional
dicing
are
theory.
data.
by
Seeds[37],
permitting
defect
these
and
failures
thus
random
published
a
before
by
discuss
slices
the
the
brevity
to
actually
designates
Petritz[32]
data
point
but
notably
predicted
typical
testing
of
researchers,
are
are
also
both
been
area
the
and
roughly
shown
-45-
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xxxxx xxxx./
Figure 2.3. Representative slice
from Petritz data
X
sl ice
nctional
area
x_e
X X
X
X X_
X
X_
X
X
XX
XX
X
XX
XX
X
X X
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X
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X XlX X
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xjV
_"
X
area
used in
analysis
-46-
I00'
90'
80'
70'
60'
30_
cell
yield
-------"
J
20
experimental
data
.___
I
10
0
i
, I
20 ' 40
,, a
60
"
80
"
IO0
,
120
;
140
_
cell size - c-units
Figure 2.4. Experimental
cell yield
vs. cell size
"
160
p =0.010
p -" o.o12
,i,
180
200
" 220
-47-
Notice
the
that
exponential
below
about
40
are
not
arrays
However,
should
near
percent.
likely
the
drawing
of
boundary
is
considerable
all
the
edge
it
may
be
that.
designed
slice
but
he
With
the
may
to
the
such
edge
account
for
area
are
some
of
any
from
arbitrary
effects
the
data
areas
rationale
Figure
more
for
2.3
completely
choice
the
PL
point.
failure-prone
gives
analysis
that
mind:
the
Indeed,
and
and
drops
this
technology
neither
yield
below
in
data
chapters
operate
ignore
an
the
the
later
points
did.
that
until
in
advancing
Seeds
between
occur
seen
following
where
effects.
not
be
and
doubt
and
will
with
the
the
do
be
Petritz
outside
apparent
to
with
Both
the
It
improve
viewed
1)
differences
distributions
yields
be
significant
of
there
avoids
boundary,
pervasive
than
non-randomness
was
of
the
d ata.
2)
to
some
For
It
degree
example,
of
Inaccurate
The
a
edge
minimization
in
not
the
random
etc.).
optics
nature
improvements
specific
mask
can
area
can
increased
cause
recognized
used.
As
remaining
(impurities
on
by
previously
a
are
these
are
causes.
in
every
a
human
materials,
rates
inspector.
largely
are
high
slice.
failure
specific
defects
in
fault
result
specific
easily
the
in
a
yield
of
inaccurate
masks
mentioned
eliminated,
air,
technological
or
of
pattern
in
increasingly
the
of
faults
effects
inadequacies
from
result
alignment
periodic
gradually
a
that
a defective
likelihood
in
appears
due
causes
likely
to
are
to
particles
be
-48-
3)
As
yield
defects
tends
to
increase.
slices,
each
with
3 clusters
has
been
improved.
and
therefore
It
appears,
approach
For
the
reasons,
and
of
c-unit.
exponential
and
thus
thus
even
we
will
consider
Even
if
distribution
represents
a
of
of
the
more
use
useful
of
each
to
assumption
be
a
worst-case
2 the
cluster
they
good
lower
design.
tend
presently
theory
at
the
for
to
do.
in
pessimistic,
bound
less
greater.
will
independent
overly
yield
is
is
2.4
defects
is
clustered
hypothetical
defects
than
random
2
slice
Figure
closely
the
provides
in
remaining
curves
even
shows
For
defects
the
of
2.5
defects.
failures
this
randomness
Figure
of
that
lines
the
number
randomness
therefore,
study
the
improved,
The
straight
these
is
this
level
the
yields
-49-
i
II
xx, xx
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x
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I
Figure 2,5. Cluster defects
on a hypothetical slice
-50-
2. 3 Failure
cells
modes,
The
problem
is
not
[41][17][40]
combinational
having
m
logic
derived.
This
of
m
set
to
failures,
the
input
dominant
input,
function
by
than
m
gates
only
such
m+l
and
however,
we
of
it
a
more
from
all
of
for
been
is
OR
the
and
NOR
logic
tests
can
to
element,
the
logic
For
of
--
--
function)
can
be
values
are
than
stuck
to
all
2v_
the
gate
of
less
one
faults
(which
are
ignored,
completely
of
output,
simplify
m variables
be
classes
less
faults
of
the
certain
of
element
of
types
gate
a
considerably
of
arrays
combinations
input,
one
researchers
essential
it.
types
other
automatic
presented
are
large
to
must
failure
tests
of
for
logic
tend
to
simple
tested
with
tests[lg].
involve
order
within
ineffective
NAND,
sequences
often
applied
Three
If
AND,
has
In
those
and
method
test
general
of
that
set
of
of
fixed-structure
known
a
faults
states.
essential
structures
such
any
complexity
as
A
when
reducing
the
is
arrays
Several
of
consists
which,
variables.
increase
It
I output,
number
possible
testing
tests
detect
large-scale
understood.
cells.
of
inputs
sufficient
well
and
diagnosability.
edge-testing
considered
inputs
the
of
yet
have
and
testing,
often
numbers
present
any
assume
the
mode
complex
includes
nature
generation
by
Jones
limited
of
and
to
a
tests
for
Nays[14].
small
LSI
However,
class
of
arrays
tests.
meaningful
most
the
of
treatment
general
above
(changing
failure
of
failures,
mode.
special
cases
as
of
into
XOR,
NAND
The
well
as
etc.).
-51-
The
implication
arrays
is
states
simple:
of
2mpossible
of
a
PL
data
every
to
will
be
large
as
the
In
adequate
must
from
array.
array
output
of
cell
the
under
These
sufficient
array.
tests,
detect
Sn
stating
exist
in
located.
arrays
can
the
cell
inputs.
for
reflects
not
the
state
This
nearly
an
m path
outside
of
above,
of
as
for
a _sensitized
to
of
in
array.
described
the
set
condition
occurrence
test
outputs)
the
but
that
test
adequate
cell
necessary
every
complete
possible
in
array
fault
wlhich
detect
conditions
(but
not
information,
in
to
have
locate)
possibly
order
each
some
output
in
been
any
single
the
form
locate
the
result
by
shown
to
be
fault
in
an
of
defective
additional
cell
or
to
also
worth
faults.
interesting
here:
all
states
necessary
necessary
multiple
every
the
input
test.
Additional
is
exist
two
to
that
an
of
arrays,
above
possible
means
must
the
that
some
Tammaru[40]
every
This
for
possible
to
test,
:for every
to
PL
of
essential
equal
means
of
testing
set. of
is
application
number
all
addition
array
exist
of
cell
This
state
large
diagnostic
the
examination
control
set
the
states.
(and
for
cell,
test
include
values
a fairly
given
fully
must
possible
assumption
any
input
array
input
this
for
necessary
set
the
of
If
general
which
more
This
result
never
negative
be
failures
than
one
suggests
adequately
are
assumed,
defective
that
Tammaru
is
no
cell
fixed
can
always
non-programmable
diagnosed
from
the
arrays
be
cellular
edges
of
the
-52-
array.
Another
important
arrays
is
the
cells,
We
will
ceil
only
can
then
(i.e.,
used
elsewhere.
be
will
be
is
each
found
it
a
cause.
all
the
both
cells
is
In
we
will
4
or
entire
row
is,
or
the
would
that
full
case
isolation
to
input
"short"
in
prevent
3.
our
By
input
to
functional
where
can
a cell
causes
an
arrays
where
tests
be
its
5
fault
fault
performed
In
marked
must
cell
examining
inputs.
be
is
example,
must
a
which
interference
tests
suspected
ihave
In
cell
within
5
additional
later.
additional
to
important
resistors
Notice
guarantee
it
its
cell
cell
inputs
and
another
cell
cell
their
structure
where
In
an
defective
changing
possible,
if
connected
defect
a
or
A
of
neighbor
a
affect
be
testing
another
array
detected.
If
2
by
to
connected
them.
case
affect
sooner
of
assume
diodes
to
determined
capable
the
on
affect
the
2.6,
be
and
the
to
failure
connecting
cells
neither
can
from
known
defective
patterns,
possible
only
indirectly
cell
can
neighbors
Figure
4 to
cell
is
regard
failure
between
input
In
with
paths
exception
cell
cell
for
one
normal
one
interaction
made
that
its
one
from
a cell
predictable
The
causes
this
the
ways
cell
of
assume
affect
functions.)
output
effect
along
in
consideration
this
is
on
case,
defective
since
performance.
one
be
of
the
inputs
provided
failure
from
in
is
the
a
form
affecting
bus,
of
an
column.
that
failure
in
mode
the
real
world,
independence
however,
of
even
we
cells
cannot
very
totally
distant
-53i
_
_
"short"
J
_----_"
2
,5
3
6
Figure
2.6.
A special
case of
ceil
failure
between
2 inputs
-5_-
from
each
other.
through
some
connection
this
studT,
negligible
for
I)
the
By
a
to
the
2)
visually
the
or
regularity
the
go
manufacturing
is
the
remote,
process
crea%ed.
other
For
a
the
possibility
than
the
causal
purposes
of
normal
that
of
any
paths
cell
to
be
reasons:
of
PL,
any
number
diagnosable
of
from
undetected,
in
however
it
between,
defect
signal
an
this
paths,
outside
must
of
the
affect
occurrence
type
would
buses,
array.
For
and
such
only
the
2 distant
even
more
unlikely
itself.
by
of
this
a pattern
of
that
independence
e arli er.
by
nature
& defect
Note
as
cell
are
exists,
consider
following
nothing
fault
cells
a significant
which
and
the
we
the
components
defect
such
other
cross
cells
of
howewer,
any
usually
possiblility
fluke
between
affecting
than
The
the
type
_ecognition
nearly
always
inspection
be
detected
scheme
based
is
the
on
array.{2}
independence
of
could
failure
of
failure
occurrences
modes
in
cells,
not
as
same
discussed
-55-
Footnotes
I)
For
a
comparison
2)
& start
between
MOS and
bipolar
ICs,
see
[451.
by
using
this
intensity
technique,
has
been
spacial
all
made
on
filtering
types
the
on
solution
IC
of
this
of non-periodic
photomasks[46].
errors
are
problem
Using
directly
d et ecta ble.
3)
always
It may
sufficient
feed-throughs
are
be
noted
in
for
any
used.
passing
depth
that
of
a depth
of
crossovers
2 layers
if
is
enough
-56-
Chapter
3
Low-generality
This
be
used
as
specific
as
chapter
an
logic
to
compare
same
Two
to
the
these
in
arrays
parity
Several
related
show
approach
and
array.
will
functions
examples.
arithmetic
arrays
how
the
low-generality
problem
LSI.
Three
represent
efficiency
arrays
results
of
with
arrays
the
these
more
will
is
will
be
An
conventional
a
can
several
be
described
approaches
third
arrays.
PL
synthesizing
different
functions;
analytical
of
(low-g)
to
shift
derived
some
register
which
attempt
is
realizations
are
made
to
of
the
functions.
low-g
only
a
small
inputs
and
i.e.,
no
functional
The
have
several
choice
of
its
outputs.
The
variability
of
a
logic
part
in
remains
maximum
functions
limiting
Thus
case
we
array
is
would
fixed
function.
common.
properties
more
by
efficiency
in
_rom
It
will
the
PL
be
that
the
seen
designer
that
can
addition,
structure
subset
of
as
the
amount
of
until
no
arrays
Judicious
be
used
to
it
will
shift
the
functions
to
can
the
its
function,
also
In
array
one
fixed
arithmetic/parity
efficiently.
changes
a
between
diminishes,
the
synthesizing
expect
--the
into
of
possible
diminishes
in
small
capable
cell
properties
functions
many
is
each
built
these
which
given
functions
that
another.
the
all.
be
of
of
one
at
the
point
is
variaDility
synthesize
shown
array
subset
programmable
programmable
PL
-57-
For
been
the
assumed.
sec ious
Since
100
of
array,
percent
less
on
emphasis
on
register
array
or
the
more
the
is
are
does,
functional
and
on
arrays,
a_rays
It
the
yield
directly
percent
the
assumption.
demonstration
register
arithmetic/parity
other
hand,
defective
of
assumes
the
of
significant
cells.
yield
this
permit
arrays.
functioning
not
a
shift
less
than
aspects.
this
low-g
has
clearer
The
considerably
functional
is
a
possible.
variability,
aspect
percent
small,
variability
functional
capable
fairly
however,
de-emphasizes
reliability
100
array
With
focuses
The
even
shift
with
30
-58-
3. I The
arithmetic/parity
The
a re
operations
common
etc.
of
fu ncti on s
straight-forward
defined
and
here
is
which
the
2-operand
addition
which
are
occur
often
simplest
and
non-tr
in
form,
even/odd
ivia 1,
computers.
with
no
carry
parity
yet
The
fairly
addition
look-a-head,
:
S
=
C'=
where
A
the
and
CA (A^Bv_^B)
stage,
The
B each
represent
sum
and
parity
C"
A
function
parity
and
of
function
as
for
on.
AAB
of
an
represents
(odd)
the
carry
is
defined:
operand,
S represents
the
carry
in
out
from
this
from
the
stage.
v A^B
2 operand
can
bits.
be
defined
Sotice
in
terms
follows:
=
A^BAC
v
A^B^C
=
(_ABvAAB)AC
=
P(A,B)^C
=
P(P (A,B),C)
v
v
&^BAC
= P(P(A,B),P(C,D))
v _^B^C
(_ABv&^B)AC
w P(A,B)^C
4 bits:
P(&,B,C,D)
so
=
bits
P(A,B,C)
Similarly
C
represents
B represent
three
I bit
bit,
function
P(A,B)
where
vC^ (A^BvA^B)
&^BvAACVB^C
corresponding
previous
and
arrays.
that
of
a parity
the
2-bit
-59-
The
equations
XOR),
repeated
suggests
written
intended
to
that
A-B,
to
possible
occurrence
this
be
these
A^BvA^B
operation
would
perform
of
a
in
(exclusive
good
cell
_unctions.
the
OR,
nucleus
Rearranging
preceding
abbreviated
in
an
array
terms,
it
is
get
S
=
(A*B) oC
C'=
&^(AoB)vC^(A-B)
and
P {A,B)
= A"
P(A,B,C)
Note
that
Further,
the
A-B
operator
as
been
equation
is
well.
In
line
(&°B)-C
for
equivalent
C"
to
is
A_8
very
and
nearly
may
be
in
used
XOR
as
form
an
also.
equality
{I}
with
designated
arithmetic
=
as
arrays.
the
the
They
above
primary
observations,
functions
to
defined
as
above
A>B
defined
by
G'=A^BvG^(&vB)
Parity
defined
by
P'=P
-
2
bits
at
Parity
be
functions
performed
have
by
the
are:
A+B
(n-bit,
4
serial,
defined
by
P=(A3-A
(&£°
A/.i)
a time)
z)
•
(A,-A o)
(4-bit)
Other
be
re£erred
designed
functions
to
to
as
incidentally
secondary
perform
the
functions.
,
primary
performed
Both
by
the
arithmetic
functions
as
array
will
arrays
are
efficiently
as
-60-
possible.
The
necessarily
correspond
to
inefficient
constructions
generally
be
We
variables
3.1.1
will
as
Array
and
the
AI
two
not
of
are
via
of
slightly
and
has
the
as
shows
n.
to
each
All
one
array
may
not
other
arrays
and
will
these
senses
functions.
(A and
0 and
Each
A)
of
I are
to
or
a complexity
XOR
the
input
available.
logic
gates
by
the
control
flip-flops.
The
At
_.36.
means
This
cell
used
cell
and
in
payload
the
of
that
logic
in
the
cell
is
the
one
given
is
is
given
the
in
the
XOR
ions
may
be
switches
itself.
Figure
the
control
each
(COF)
programmability
to
Control
tlhe switches.
for
factor
cells
these
of
nucleus
of
above
In% eEconnect
including
place
its
below.
array
c-units.
the
from
inputs
(Alternately,
of
are
corresponding
{2}
11
Cells
diagonally
identical.
overhead
that
3
and
Note
cell
3.1a.
left
a cell
of
f_nction
has
to
the
"switches".
complete
performed
cell
go
are
Figure
right,
cell
of
nucleus
in
the
cells
diagram
the
and
length
cutpoints.)
the
flip-flops
is
of
constants
diagonally
three
6
alters
function
the
functionally
from
The
which
made
of
of
both
logical
above,
functional
function
3.2
rows
shown.
3. lb.
thought
shown
below,
A
Figure
is
Outputs
left,
are
those
tlhat
the
immediately
right.
paths
as
functions
At.
in
neighbors
assume
well
Array
arranged
secondary
state
The
of
the
for
the
cell
of
the
cell
-61-
__b ...... _-_rLJ
2*n cells
2n+2 inputs
n+2 outputs
(a) Array AI
I1
.
I..
aI
aI
I
I
I.
I
:
I
o,J,,[
2
,
I
',
I
L
I
I
L1mm
lJ,
el_
_
I
m
_
lJJ
_
_
_=D m=. _
lJm,,_==- _I
payload = 11 c-units
O1
(b) Cell A1
Figure 3.1. Array Al
3
-62-
I1
2
C2
•
<
I3
_
C0
Cl
o1
y
iD
X
|c o
iD
i cI
iD
I-9-2
-
nucleus = Ii c-units
cell total = 48 c-units
COF = 48/11
C0
CI
C2
01
= 4.36
02
o o o
h^%vh^h
_I
0
0
i
IIAI3VIIAI 3
_i
0
1
0
IIAI2VI3AI 2
_i
0
1
1
_Vl
3
L
1
1
0
IIA_2V[3^I 2
Figure
3.2. Complete cell A1
andIts
functions
0-"
1
-6 3-
increases
the
amount
Figures
the
cell
of
3.3
logic
and
3.4
perf or ming
respectively.
indicate
Three
its
control
binary
digits
are
shown
as
except
for
0 and
I are
from
array
may
Equality
as
(A=B),
secondary
delays
or
circuitry
3.5.
One
column
of
array,
the
is
appropriate
and
C2
and
sides
as
either
of
sense
the
in
B
the
the
union
each
cell
CI,
and
the
same
operand.
input
to
of
and
array.
C0,
the
inputs
(_^B),
tlhis
of
functions,
on
obtained
of
It
array.
is
and
Outputs
desired
Propagation
C2,
wa T
variables
(&vB)
to
function.
are
possible
time
is
4
gate
more
detail
less.
Figure
cells
botlh
available
of
is
negation
intersection
Control
of
the
be
functions
flip-flops
subtraction
that
constants
the
i.e.,
4.36.
configurations
secondary
state,
before,
various
of
and
that
as
the
a factor
primary
Notice
assumed,
detail
by
%he
respectively.
addition
necessary
line
line
load
on
causes
the
the
runs
control
presented
X
to
bus
of
cell
along
is
shown
each
row
information
the
each
corresponding
Y
to
buses.
cell
in
Y
in
and
be
one
loaded
A single
the
input
row
into
to
along
•into
pulse
shift
CO.
in
each
a
row
on
the
CO,
CI,
•
-641
A
A.
B.
l-/'
'
i
L_
A + B
.........
/S
i
"H'-_i
C
i_
C.
Oi0
= A ^H'-Sv C
^HS
i
i
i-I
i
i
Ii
:-1
(_I
i-I
_'.
I
s,
I
_,/
_,_,/
I
_
A > B
,
i
i
t
= _.AB V A AB'.
HS
i-I
i
IAi
H-Di
Gi
t
i
i-
i
t
-
.i
i
= AiAH-'D"
i v Gi_IAHD i
o ^.o
i
--
HPi."
p
i
PI
P
2i_2
i-
i
i-I
v
i
2 _
I
i-I
-
is [odd if P 1= 0
= 1
Leven if P_I
0
P
Figure 3.3,
j
= P'I-2AHPi v Pi_2AHPi
i
m
.... /__3 /
i
i
_,
I
n-bit
parity
i-I
Primary functions of cell A1
-65-
A
/
Bi
LJ
A = B
i
eelIoiI
A^.
EI
= Ei-I^(Ai=Bi)
A.=B.
!
I
I
I
A.
B.
En-1 = (A=B)
i
A,
IA'
^"'I_:'^_'-I
q,;,I
'
I,,,1.,p
I "
A i AB.I
A.t-1ABi-I
,=...
_--L_._
1011,
- I
A vB.
i i
II0 U
l,o,p
i
A. vB
I-I i-I
Flgure 3.4. Secondary functions of cell AI
-66-
!
l
_
Y3
Y2
(a) Array
yj
D
X.
I
A1 showing
C
(b)
Control
3.5.
Y1
control
C
circuitry
Control
logic
.!
buses
C
of
cell
of array
x0
YO
io 0 1
1
Figure
[
_
i,j
A1
2*nce]]s
n+2 buses
-67-
The
total
number
2n+2
data
inputs
n+2
data
outputs
n+2
control
_n +6
is
well
hawe
g_16+6
within
=
70
connections
to
the
array
is
buses
connections
This
of
.
manufacturing
pins
on
the
feasibility
resulting
package.
todaT;
if
n=16,
we
-68-
3. I. 2 :Array
_ 2.
Array
A2,
shown
cells
arranged
in
a
same
as
in
array
those
connection.
of
The
11
c-units.
diagram,
Figure
logic
:is
Figure
3.7.
opposed
to
the
3.6b,
quite
4.36
for
possible
in
time
Control
is
R I.
Total
3n+3
data
inputs
2n+]
data
outputs
control
At.
connections.
them
of
3 gate
3.9.
the
shown
connections
is
3-throw.
cell
At,
in
a
of
in
the
The
factor
is
detailed
Two
extra
a
in
parity
functions
the
vertical
a complexity
can
around
similar
are
second
as
are
or
up
having
shown
3 secondary
delays
of
ace
overhead
functions
made
connections
function
organized
Figure
is
addition
XOR
cell
mainly
to
buses
of
that
cell
logic,
array
6n.9
to
the
addition
the
"switches"
that
in
3.6a,
Intercell
the
one
Primary
functions
n.3
2
are
array.
with
is
but
Figure
array.
AI
similar
Notice
Propagation
n
Only
secondary
of
3 by
nucleus
Functions
:in
in
functional
entire
be
seen
only
4.09
vertical
Figure
cell
from
as
column
3.8
functions
and
are
of
array
At.
to
that
less.
Figure
3.10,
:is analogous
to
array
number
the
-69-
•
t
3+,n ce 11s
3n+3 inputs
2n+3 outputs
(a)
12
I
z3
!
I
!
I
I
]
I
-
'
I
!
I/
'
'
!
,
I
I
I
I
!
02
I
]
0
payloadI = 11 c-units
1
(b)
Figure
3.6.
Functiona]
diagrams
i
of array
A2
-7012
I1
13
_
,C1
C2
14
Co
02
cell
total
= 45
c-units
payload
= ii
c-units
Ol
y -
COF = 45/11 = 4.09
On
C2
.
X''
C0
Cl
C2
01
02
0
0
0
12
i1^i3vi1^i3
0
0
1
12
[I^[4VIIAI4
0
i
0
.12
IIA (I2VI3)VIIA (I2VI3)
0
1
1
12
IIAI2VIIAI 2
1
0
0
12
IIA_3V[4AI3
1
0
1
12
[lVi 4
1
1
0
12
IIA(I2VI3)VI--4A
(i2vi3)
Figure 3.7. Cell A2 and its functions
-71AiT.
j,_
B.
I .
I
-
A + B
_.
I_SIjL.j
Ai
11' --.
i
--'_I_H__,_i
C
C.
i i i
= A.AHS vC
S,
•
= E.,
ii-1
, i
i-I AHS
"vC i-IAH'S-.
fC
i
-
= A.AB vA AB.
HS
i
_j
S.
i
AHS.
i
i-I
I
A.A.B.
HD. = A'.A'B.vA.AB.
A
B
G
HD IAI_[_
i
Ei/_..-.,,, ,,--- E,.,i- 1
Gi
_
D.
ii
D.
Gi-1
= A.AHD vG
AHD
i __-i
i ii-Ii
i
= E i_ ] AHDi vG i- 1AH'-Di
t
I
• Ai_ 1
•
!
HPi = A.AA
I
i-1 VA.AA
I
i -1
H-Pi
Pi-2
P
Pi
-
_
= P.i-2AHP ivP i-2AHPI
n-bit
parity
Pi
is
n-1
odd if P i=0
even if P_I=I
A3 A2 0 A1 A0
I;
4-bit
parity
_
J
HPI : A'2AA3vA2A_3
p
= HP%AHPIVHPoAH_ I
o
P
Figure 3.8. Primary functions of A2
-72OA i B.
[-(
)0
A = B
Ai=B i
0
Ei = Ei.IA(Ai=Bi)
E"i ---[11
--E"i_1
En_1= (A=B)
N
N
Be
i
•
'
m
A.AB
I
AAB
AiABi_A
iABi
i 1
B'i
AivB"
AVB
A.VB
,
.VB.
!
I
3-bit
5-bit
A0OA OA
parity
1
4
_
par'tY
Ao°AI°A2
Ao°A__
Ao°AI°A2°A3°A 4
Figure 3.9. Secondary functions of A2
30A
-73-
1212
....
-
1,3
-'_
1,2
i
"-
1,1
X2
"-_
1,0
J
[
i
!-
!
i
0,3
_I
i_-"
_
0,2
.. 1
0,0
l
A2 showing
!
1
Y2
(a) Array
xo
Y1
control
YO
buses
]ii
i*J
x._
.....
j0 ,,Co
'[_iJc c°
I
(b)
Figure
I
Ii
0,1i
l
i
Y3
--_
!
Control
circuitry
of
3.10.
Control
logic
cell
i,j
of array
A2
3_,ncel Is
n+3 buses
-74-
Notice
that
connections
for
although
than
several
(e.g.,
than
for
3.1.3
array
of
8-bit
impractical
way
combinations
of
states
of
test.
Obviously,
actually
the
used
possible
tests,
performs
cells
the
neighbor
it
the
a given
n,
more
value
of
n
cells
fewer
Thus,
have
a nd
cells
for
a
required
are
given
will
more
required
task
length
he
less
for
be
100
A2
is
of
this
doing
2n+2
cells
but
error
detection
for
2 faults
would
be
cell
can
another
it.
without
connection.
to
of
cell
Thus
is
at
we
simple
n.2
other
consequence
as
control
outputs
of
at
each
tests
to
be
Even
if
it
throughout
long
but
possible
possible
assured.
each
percent
all
number
thus
as
the
all
array
defined.
it
is
and
test
its
assume
the
2.3.)
that
connecting
cell
distance
effects
:_ection
to
a
a greater
considerinq
(See
a
buses,
can
A
the
the
large
as
control
to
apply
of
observe
obscure
no
affect
to
each
approach
only
the
is
too
functions
a
array
to
is
primary
to
then
arrays
straightforward.
for
this
practical
nearer
inputs
and
A2.
these
diagnosis
the
of
and
reguired
more
of
A1
arrays
A
use
operation
in
the
of
we
their
Without
has
At.
functional,
within
for
array
functions.
add),
Since
the
At
the
Diagnosability
were
this
cells
between
fault
neighbors.
cannot
affect
without
from
a
affecting
right
cells
the
to
left
beyond
one
-75 -̧
3.1.4
Evaluation
A
Table
and
summary
3. I.
secondary
functions
(POF)
is
nuclei
combine
components
to
efficiency
TOF
better
of
• COF.
of
the
two
a
3.67
better
vs.
2)
the
A2.
and
of
in
of
the
desired
of
TOF
is
the
how
the
and
3.11
and
factor
payloads
by
the
efficiently
sum
the
The
of
all
of
logic.
the
in
overhead
a measure
in
given
primary
function.
control
values
is
Fiqures
cell
of
k2
the
a payload
ratio
The
A1
measure
including
has
of
AI
The
AI
set
is
table
total
the
the
cell
overall
Notice
that
represent
the
o£
is
If
it
were
3)
Although
eliminated,
POF
is
the
POF
that
that
(2.2
of
A2
vs.
(I._6
arrangement
A2
is
functions.
lower
A>B
than
suggests
clearly
function
average
greater
primary
a
noteworthy:
better
much
This
has
A2
are
a slightly
2.75).
to the
whereas
functions.
arrays.
AI
to
Array
functions,
a
the
of
comparison
sum
comparisons
range
1.27
"fit"
form
and
arrays.
Although
POF
is
Underl[ned
following
the
POF
is
array,
POF
I)
the
_I
each
function,
minimum.
=
The
2.3),
the
of
for
each
to
(TOF)
the
array
functions
given
The
factor
the
dividing
synthesis.
overhead
to
is
by
of
synthesis
For
computed
minimal
all
minimal
respectively.
the
of
A
3.12,
cell
comparison
and
TOF
for
the
superior
on
the
2 arithmetic
clearly
entire
suboptimal
TOF
range
2
parity
with
would
be
both
5
to
10.
lower
for
average
Al).
TOF,
Since
the
AI
has
owing
cell
a
lower
average
mainly
to
n_Iclei
are
its
the
POF,
lower
same,
array
COF
less
(4.09
cell
A2
has
vs.
the
4.36
overhead
-76-
-77C
A + B
,_'_
i-lB.
I
A.
l
B.
26 c-un its
I
C.
C.
i-I
A>B
I
B.
l
Gi_
A. 1
Gi
I
12 c-uni
n-bit
par i ty
ts
A.
_1-1
A.
-'
Ao
Pi -2
!_
_
I
15 c-un its
4-bit
AI
parity
A_I
_
A2
!
A3
Figure 3.11. Minimal synthesis
of the primary functions
Podd
22 c-units
-78-
A = B
Ai
Ei.I_
E.
'
B.
I
11 c-units
AAB
A.
--m
B.I
"
A AB.
i
I
3 c-un its
A v B
AI
_.
A.vB
l i
I
pa r i ty
3 c-units
A1
3-b't
A° r
A2
15 c-un its
5-bit
parity
A0
A1
•
-------
A2
A3
A4
30 c-units
Figure 3.12. Minimal synthesis
of the secondary functions
Podd
-79-
exists
in
follows
set
cell
A2.
that
of
the
primary
4)
arrays
functions
are
that
creating
these
to
somewhat
that
set
are
more
the
unused
the
natural
the
2-stsp
in
choice
the
of
functions
they
all
can
The
choice
of
as
easily
to
obviously
have
as
building
success
XOR
was
been
for
range
XOR
Indeed,
at
to
all
NOR
much
less
of
(the
redesigning
the
gates
due
primary
because
one.
of
XOR
which
functions.
could
arrays
to
be
just
also
this
was
still
result.
could
could
But
goal
These
similarity:
We
functions.
above
be
function.
the
their
either.
operator)
and
when
to
is
of
could
which
in
careful
of
The
desired
values
equality
a
combinations
which
in
9.0)
parity
This
because
NAND
This
2 functious.
was
efficient.
the
TOF
these
=
are
A2.
both
parity
seems
the
that
for
involved
{3-bit
functions.
possible
used
(TOF
of
arbitrary
or
necessary
all
of
chosen
the
as
than
functions
reduced
not
AI
version
been
chosen
form
the
A2
shape
above.
function.
This
functions
by
primary
easily
large
instance
instead.
be
block
is
parity
have
have
combined
nucleus
tree-like
done
_2
it
the
differ.
XOR
functions.
to
(I)
_effort"
primitive
&2,
suited
c-units
of
by
notion
efficient
incidental
the
better
total
functions
surprisingly
other
cells
7
required
distributions
certain
secondar
is
of
the
the
is
supports
number
but
a
A2
This
from
efficientI¥
The
primary
the
are
to
Notice
is
overhead
array
total
functions
of
parity)
compared
this
4
of
identical
there
Two
cell
given.
average
nearly
suggests
5-bit
less
arrangement
The
5)
Since
be
would
choose
_sed
as
A measure
Notice
have
with
a
of
that
been
a
in
used
XO---Ras
a
-80-
nucleus
nearly identical
produces
Relatively
minor
interconnections
Array
AI
g2
is
can
is
more
in
cells
bit
per
rather
{TOF=16.0).
would
permit
thereby
have
(A=B)
be
would
than
to
be
4,
done
rearranged,
functions.
be
One
per
function.
performed
it
bit
Other
and
would
while
additional
(2 c-units)
2 cells
however,
.
eliminating
inverter
with
that
to
or
functions,
roles
(A>B)
structure
between
arithmetic
thereby
an
array
balance
parity
allow
of
improving
the
the
Addition
greatly
to
A]
the
the
on
in
cell
in
upset
superior
efficient
connection
point
changes
sharply
clearly
results.
with
as
to
2
a weak
cell
instead
At
of
functions
4,
would
undoubtedly
suffer
s omew ha t.
Notice
inflexible.
only
6 or
that
also
Only
7 out
data
is
opposite.
that
nearest
of
interconnection
neighbor
a possible
restricted
This
the
to
severely
16
connections
of
moving
structure
those.
only
limits
It
left
the
are
and
topology
is
used
also
is
very
and
then
important
down,
never
of
functions
the
the
realizable.
Some
other
I)
directed
possibilities
Groups
to
I or
of
more
for
distribution
of
a
group
primary
function
functions
of
outputs
where
depending
sets
are:
I input
on
a
is
given
parameter.
2)
decoder
Groups
functions
3)
_
of
selector
(binary
group
of
to
(multiplexor)
octal,
boolean
I out
operations
functions,
of
on
10,
a
encoder
or
etc.).
given
set
of
2 or
-81-
more
words.
4)
counters,
Various
n-bit
The
can
be
(lower
cell
and
g
point
of
or
the
the
same
made
a
a
over
effects
a
latching
here
these
small
of
is
carefully
paths,
functions
try
registers
such
simply
in
length
this:
chosen
set
are,
the
by
small
an
can
be
array
In
larger
The
following
and
more
etc.).
array
functions.
The
better
the
fit
in
the
changes
"tuned"
2 array
(up/down
A low-g
of
Further,
others.
scale.
given
registers,
functions
overhead).
data
on
show
"fit"
less
this
to
be
similar
demonstrate
of
registers,
to
to
more
implies
nucleus
certain
shift
designed
smaller
types
to
examples
chapters
general
favor
given
we
shall
arrays.
-82-
3.2
A shift
register
The
yield
previous
in
order
group
a
of
low-g
array,
of
array
frow
and
north.
from
in
its
only
of
4
the
cell
is
n,
5.8_,
n=8
but
the
long
of
90
path
It
even
of
drops
off
COF
is
By
connecting
shift
an
bits
that
percent
is
of
as
easy
a
may
many
very
to
cell
4
included
in
with
the
in
path
example
of
register
the
problem
defects.
{3}
as
nucleus:
a
its
has
connections
east,
south,
of
the
the
is
cell.
addition
west,
shift
Figure
of
n=1,
on
the
shift
bit
3.1_.)
dependent
If
to
direction
last
(See
factor
the
of
numerous
neighbors.
overhead
rapidly
cells
(or
the
all
on
determine
output
cell
the
COF
bits.
=
At
1.60.
register
array
when
only
The
the
shift
focuses
cell
flip-flops
an
The
function
Each
percent
realization
present
of
100
and
the
designated
received.
the
we
presence
bits.
to
nucleus
on
3. 13,
simple
state
transmitted
shift
the
more
to
emphasis.
neighbors,
is
that
Now
Figure
sinqle
control
Notice
number,
a
cell
effects
opposite
in
I or
data
the
their
in
nearest
The
which
the
the
functionally
has
on
restricted
functions.
with
register
and
focus
functionality
cell
were
and
predetermined
maximum
shift
better
structure
shown
Each
examples
to
interconnection
a
array.
several
contain
good
as
see
25
a
shorter
many
can
to
percent
that,
unsophisticated
unless
shown
ones)
defective
cells
30
as
usually
of
defect
algorithm
in
can
cells.
be
the
Figure
be
built
In
included
cells
densities
can
3.15,
up
fact,
in
are
are
utilize
a
out
85
a
to
single
defective.
too
a
high,
good
-83-
I*J
cells
2(l+J)
inputs
2(l+J)
outputs
Figure 3.13. Functional diagram of array Sl
-84-
'
(E)
(E)
CO
CI
(S)
(S)
CO
(w)
CI
_
D
I
Ii..._.
r---I
,
,
_
C'-"
0
Y
(N)
j
C
'
CI
T
i
,,
,m
Y----" D
X
[ Cn
Im
i
II
,
--'J
(w)
,
F/_
I
other shift bits,
if any
i ii,ii,,,
)
[ -F
_
payload
6n
data gates 17
control ffs 12
29+6n
COF = 29/6n + I
Figure 3.14. Cell Sl
n_l
, (N)
-85-
"-
"I
I-I
ix
l
]I
IxiITII
I
OUT-J
F--l
(_a) A path of
length
10 cells
iii
qv
_
I
Ixi
,N
U
OUT
Cb) Two paths
of lengths 5 ceils and 6 ceils
Figure 3.15. Examples of a 16 cell
array with 5 defective cells
-86-
percentage
of
The
the
control
analogous
to
associated
with
the
usable
control
cells.
circuitry
that
each
for
of
arrays
row
and
flip-flops
are
each
presented,
Strobing
of
shifted
into
control
flip-flops.
used
t_igger
each
cell
cell
made
the
on
is
also
nucleus
up
of
Y lines
the
(Figure
all
the
to
simultaneously.
control
flip-flops
appropriate
3.14).
cells
and
in
the
array
Pulsing
except
&2.
when
(Figure
One
Data
one
X
Thus
the
array
column.
buses.
the
the
_I
this
row
line
to
at
a
causes
Notice
shifting
that
of
control
be
time,
the
the
shift
is
triggered
by
the
the
X
Y
lines
buses
the
to
Y
be
Y line
in
in
the
register
pulsing
has
are
on
data
composite
is
into
bits
the
is
bus
loaded
the
of
3.16)
no
all
effect
actiwated.
-87-
I
I
X2
|
•
,
,
I
X1
,
[
|
-- 0,0
xo
i
"
,,L
I
t
I
|
_- 0,1
1 _
!
1
,
1,2
-
l
.
"- 0,2
I _
"-'--"
-
--
[
I*J
YO
Y1
"----"
Y2
I+J control
(a) Array S] showing control buses
YJ
Xo
I
(b) Control circuitry of cell i,j
Figure 3.16. Control logic
ce]I s
of array Sl
buses
-88-
3.2. I Choice
of
As
utility)
here
for
previously
is
included
in
mentioned,
dependent
each
on
cell.
the
There
which
bears
on cellular
a given
array
of
only
a
fixed
increases
so
probability
does
of
can
determine
shift
parameters
the
of
arrays
complexity
some
knowledge
value
over
of
the
given
n
COF
n,
in
total
the
which
will
array
register
trade-off
bits
involved
shift
wiill result
bits
exist.
cell
yield
we
7
other
n increases
However,
and,
technology
array,
and
the
As
the
about
technology
shift
thus
general.
cells
of
whole
of
(and
interesting
defective
failure.
the
an
sore
cell
the
bits
of
the
number,
is
cells,
number
Given
of
n.
with
to
the
begin
as
it,
be
of
array:
p - probability
N - total
number
P s rmn M T -
of a c-unit
of c-units
being
good
(defect-free)
possible
in the array
probability
of a cell
being
defect-free
number
of c-units
per
shift
bit
number
of c-units
cell
overhead
(.not a function
total
number
of c-units
per cell
number
of shift
bits
per cell
number
of cells
in array
expected
number
of qood shift
bits
in array
of
we
number
defining
parameters
n
the
used,
maximum
by
if
n)
2
the
-89-
The
cell
of
has
probability
a
a cell
of
total
of
r+ns
having
no
defects
failure
c-units
is
of
in
any
it,
given
and
c-unit
thus
is _.
the
Each
probability
just
-(r+ns)p
P =
assuming
the
Section
e
defects
to
be
independent
at
the
c-unit
level
{See
2.2).
N
included
represents
in
number
of
a
single
cells
we
the
largest
array
can
number
while
have
in
of
maintaining
an
array
c-units
yield
of
which
p.
N c-units
can
The
is
be
total
clearly
M =Ir--_nsl
where
[x]
cells
signifies
the
themselves
independence)
greatest
as
and
thus
integer
simple
the
mean
.in x.
Bernoulli
or
We
may
trials
expected
number
treat
the
(assuming
of
good
cells
is
g
and
the
Each
number
standard
cell
of
deviation
contains
good
shift
n
bits
+n
is
sh ift
in
the
bits
array
and
:is
therefore
the
available
-90-
T =nM
=
e
.
g
We
wish
array
parameters
value
n
which
register
to
maximize
p and
N inherent
yields
bits.
the
Setting
T for
dT/dn
register
each
the
shift
yield
equation
per
cell
bit
and
in the
p.
as
the
= 0 and
2s
array.
Given
technology,
of
solving,
the
there
functioning
is a
shift
we get
_r
the
a function
cell
given
number
represents
bits
parameter
to
greatest
opt
This
any
optimal
of
control
Since
n must
be
n
=
In
actual
the
number
number
and,
more
an
integer,
+0.5]
of
shift
of c-units
importantly,
in
of
we round:
.
opt
E xa mp le:
Given:
The
technology
parameters
N_<5000,
shift
parameters
r=29,
optimal
cell
number
of
shift
bits
per
p=.002
s=6
cell
is
29
n
=
-
opt
For
this
example,
we
will
use
=
17.8
.
.002,29
n=16,
close
to
the
optimal
yet
-91-
more
COF
convenient
for
this
for
cell
usage
with
data
lengths
of powers
of
2.
is
29+ 16,6
COF =
=
1.31
.
1 6*6
The
maximum
number
of cells
possible
M=
in
the
array
is then
= 40
=
.
[29+ 16"6J
The
the
maximum
the
necessary
5
by
in
8 cell
a nearly
busing.
array
square
The
M .= IMP]
E
the
standard
And therefore
the
deviation
expected
in Figure
configuration
number
= _ O*e
=
and
shown
of
good
which
cells
- (29+16,6),.
[40,0.778]
3.17
= 31
provides
simplifies
expected
002_
.
is
number
T = nM
=
E
of good
16,31
=
shift
496
bits
.
is
is
-92-
Figure
[M(I-p}]=g
3.17a
defective
A
shift
register
as
a path
through
shift
register
the
=
432.
of
Figure
30
shift
of
arrays
case
utilizes
The
shows
good
of
cells
are
and
the
of
but
a
yield
for
any
is
is
of
useful
of
shown
then
the
total
X.
used
with
number
for
with
cells
bits
used,
with
actually
shift
the
array
marked
good
cells
instance
increase
this
random
number
same
of
of
number
the
to
at
most
The
27.
also
which
of
this
implemented
The
manufacturing
to
testing
yield
chip.
constant
yield
Mcst
any
in
16#27
addition
cells.
16#30
all
but
{4}
This
on
we
say
chip
this
256-bit
and
N
each
is
o_
=
480
7 or
slice
so
it
defect-free
on
about
a
is
produced
as
all
wiring.
economically
at
single
each
there
memory
is
element
100
percent
c-units.
chip
enough
(array)
by
available
writing,
2000
actual
used
circuits
this
be
A special
discretionary
that
control
can
discarding
currently
random-access
large
slices
simply
desired.
ICs
At
represents
number
consider
the
array
procedure
the
enough
manufacturer's
assume
a
of
manufacture.
decoding
yield"
given
by
that
redundanc
high
a
level
than
percent
is
during
address
over
we
desired
lower
_100
available
available
If
the
discard
commercially
8-bit
any
yields
without
point
with
to
have
is
the
commercially.
are
feasible
that
inflated
manufacturers
then
selected
array.
is
instance
bits.
artificially
is
the
31
Notice
all
which
connections
the
an
cells
3.17b
external
Here
shows
No
data
yield.
so
that
p is
by
the
same
a
group
of
nearly
process,
Bernoulli
-93-
i
r:q b:l--T lif'-'
,_,._ I:"! m
r-q ,--Fq m P r--t:d
FqEJ'=,'"
! l_,-qF,
OUT
_I::1
total cells
good cells
cells used
(b)
F_gure 3.17. Shift register array examples
= 40
= 31
= 30
-94-
trials
(cells).
Each
(success)
and
1-P
If
are
H
there
exactly
k good
cell
has
probability
of containing
cells
cells
in
one
a binomial
P(_
=
=k)
or more
the array,
follows
P
P
of being
defects
then
the
good
(failure).
probability
of
distribution
(l-P)
g
w he re
k
Then
tlhe probability
of
k !(n-k) !
having
P(_
g
Using
we
require
arrays
the
arrays
meeting
>_k) =_
i=k
previous
to
this
have
k or more
35 or
with
more
we
are
we
willing
p ro duce d.
could
to
discard
an
and
cells.
M=40,
The
suppose
fraction
of
is
(.778)
35
achieve
is just
•
P=0.778
good
this
(.222)
i
= 0.133
Therefore
(I-P)
>_35) =
g
cells
x
example
requirement
p(_
P
good
or
goal
average
of
about
using
1/7.5
the
13 out
given
of every
.
process
if
15 arrays
-95-
Notice
shift
register
using
a
c-units
what
would
example
be
necessary
in
the
100
percept
yield
are
necessar
y
register.
Given
assumptions,
the
the
in
build
conventional
process.
an
same
Tield
to
Since
technology
for
s=6,
q32-bit
way
sT=6,_32=2592
conventional
(p=.002)
this
above
nonprogrammable
equivalent
expected
the
and
shift
shift
our
previous
register
is
given
by
-sTp
-2592_.
e
That
is,
on
produced
were
in
the
willing
overall
average,
this
way
to
yield),
be
could
9
be
the
of
-6,T,
T
utility
of
177
10
if
T were
the
shift
registers
slices
if
(10
such
we
percent
that
.002
shift
vein,
.
Alternately,
=
_- 192
practical
of
every
- e
or
illustrate
out
achieved
-sTp
a more
I
0. 0056
defect-free.
out
e
In
=
only
would
throw
this
002
= e
the
0.1
bits.
following
programmable
example
logic
will
shift
best
register
array.
As
N_3000
c-units
nearly
Use
before,
on
constant
the
particular
same
let
p=.002
a slice.
Assume
regardless
logic
length
cell
shift
and
of
as
the
before
register
suppose
that
exact
(r=29,
(say
256
the
we
cost
number
s=6,
bits)
are
of
of
the
the
to
slice
is
on
it.
c-units
n=16)
as
limited
and
goal.
take
a
-96-
A
put
2
hope
that
yield
100
256-bit
for
at
percent
yield
shift
registers
least
this
I of
process
approach
the
on
2
That
is,
registers
shift
about
The
M=2_
cells
256
bits
cells
of
of
, then
cells
out
of
100
Overall
of
100
approach
shift
the
we
good
need
to
would
be
(N=2,256,6=3072)
be
good.
The
to
and
expected
.002
yield
to
this
form
will
can
16/0.85
=
of
problem
I or
is
in
the
we
need
be
19
19
would
then
both
9.2
path.
or
more
more
alg)
=
g
good
(l-P)
i=19
=
O. 530.
=
If
good
as
In
256/n
connected
or
be
array.
is
P(R
have
exFected
a shift
cells
probability
.
shift
256-bit
slices.
register,
to
0.092
slices
(N=(29+16,6),24=3000)
The
24
PL
interconnected
percent
path
out
problem
slice
out
=
operational.
registers
this
is
2,e
9
the
turns
-256*6*
P =
to
follows:
order
256/16
we
=
assume
together
to
cells
per
cells
in
an
let
to
have
16
good
that
form
85
this
array.
array
of
-97 -̧
I.e.,
100
overall
yield
slices,
process.
yield
or
If
we
increases
expected
is
nearly
6
include
arrays
53
256-bit
times
shift
that
with
18
registers
of
the
I00
or
more
out
percent
good
of
yield
cells,
the
to
P(H
>18)
=
0.704
g
or
nearly
8 times
Notice
increases
the
also
(and
N
This
combination
function.
cells
of
Furthermore,
technigues)
the
cell
COF
decreases
per
shift
gets
bit
that
as
is
48
due
process
the
p
the
PL
mainly
closer
with
the
there
is
arrays
to
reduced
are
1.0.
decreasing
cell.
there
are
to
PL
again
register
approach
rapidly
are
more
waTs
get
20
good
r and
s
thus
lead
are
there
more
increasing
fo
get
cells
higher-yield
the
length
becomes
the
in
p and
shift
to
(by
If
yield.
desired
the
I.e.,
than
if
in
percent
inc teases),
persuasive.
out
100
40
out
good
of
24.
manufacturing
since
held
is
the
constant,
less
COF
of
the
overhead
-98-
3.2.2
Testing
and
Due
to
systematically
by
a
sides
by
at
4
few
compared
to
other
usable
takes
In
additional
conventional
of
trivial
make
(small
all
state
edge
done
to
this
path,
we
obstructed
for
3
been
same
will
also
each
the
cell
easily
or
more
included
process
cell
testing
can
on
have
every
changes
left
be
leftmost
the
of
may
can
lower
cells
repeat
order
the
This
we
the
is
Eventually,
using
be
2
tested
necessitates
individual
test
orderings.
a
than
of
cell
which
is
4 directions)
the
functional
examples
we
partially
could
be
parts,
functional
used
thereby
in
a
path
increasing
yield.
the
above
cost
of
testing
one.
(per
process
nature
testing
computer,
the
SI
since
for
shift
fairly
testing
have,
a
all
the
PL
and
Since
operator,
ignored
array
must
slice)
high-yield
simple.
course,
slices
good
register
jig,
of
programming
resulting
than
of
of
and
However,
testing
low-yield
to
it
we
This
less
from
time
When
path,
that
advantage
a
array,
array.
with
unless
possible
in
at
edges.
also
tlhe effective
cost
such
this
extending
cells.
cell
Notice
which
cell
cell
one
the
beginning
directions.
relatively
(e.g.,
one
adjacent
all
paths
defective
least
Sl.
of
outside
array,
adding
other
from
test
the
of
simplicity
it
defective
different
in
of
By
locate
in
up
edge
alone.
the
test
building
bottom
diagnosability
be
is
the
higher
Also,
low-g
the
etc.)
over
tested,
process.
of
the
the
the
the
for
a
the
array
testing
apparatus
must
physically
-99-
exist
in
either
additional
computing
We
example
2.2,
have
how
problem
in
100
percent
part-number
$I
array
of
various
in
there
SI
and
can
the
be
are
more
the
array.
the
shift
effective
may
be
that
can
that
register
array
As
:in Section
noted
higher,
by
clustering
of
the
the
because
the
of
the
to
benefit
effectiveness
in
approach
predicted
only
is
SI
LSI
of
the
o_Ir exponential
case
for
the
defective
array
PL
cells
than
are
to
the
random.
al so
offers
a
problems
programmed
(all
to
the
available
partial
for
function
multiples
increases,
cells
PL
situation.
than
inventory
lengths
array
r eg ister.
at
an
yield
notice
to
scattered
lrray
be
This
damaging
defects
can
difference
the
via
cells
Furthermore,
less
show
defects,
cost
for
to
larger
function.
approach.
main
needed
PL
of
distribution
time
tried
for
clustering
the
low-g
a <
yield
is
case,
of
shift
as
n).
perimeter
to
serve
sol ution
registers.
several
As
the
becomes
as
shift
&
single
registers
number
of
longer
and
endpoints
of
a
cells
thus
shift
-100-
Foot no tes
I)
Section
For
made
out
is
as
in
discussion
of
the
universality
of
A-B
,
see
If
this
4._.
2)
array
a
Shape
the
array
is
to be fabricated
on
tall
possible
that
3)
discretionary
4)
of
and
thin
as
not
a square
important
slice,
by
having
here.
each
its
cell
could
components
be
laid
pattern.
For
an approach
wiring,
Itel
1101,
to this
see
Tammaru
see
[43].
and
problem
using
Angell[41].
redundancy
and
-101-
Chapter
4
refers
As
discussed
to
the
different
will
.1
a
of
the
different
of
research
chapter.
Section
will
4.2
Iuterconnection
array.
facilitates
Section
suitable
for
length.
Rn
are
4.4
discussion
chapter.
in
of
the
In
to
a
this
appropriate
the
of
chapter,
we
logic
Further
cell
form
arrays
in
references
which
is
at
Section
throughout
properties
g)
variety
a discuss:ion
array.
where
(high
to
the
a high-g
introduced
as
solutions.
4.3.
discusses
A
the
area
Section
both
bus
of
Functions
application
perfor_
cellular
with
generic
routing
high-g.
presented
made
generality
to
high-g
structures,
Section
high
variables.
begin
devoted
A
of
of
cellular
be
is
1,
device
of
We
PL
a class
in
a
number
possess.
representing
greatly
a
levels.
previous
discussed
of
properties
previous
should
Chapter
ability
consider
array
in
functions
several
arrays
High-generality
for
scheme
is
variables
nature
of
of
PL
Analysis
of
to
this
and
cell
of
a
the
functions
considered
detailed
the
are
which
within
nucleus
are
and
buses,
introduced
points
3 variables
high-g
4.5.
feasibility
neighbors
example
example
application
at
close
and
a
the
-102-
4. I
A previous
PL
array.
Although
in
the
a
substantial
area
of
cellular
logic,
logic
array
is
known.
The
4.1,
is
capable
of
flip-flops)
with
through
each
cell
buses,
several
adjacent
bus
which
Y program
which
program
and
all
each
also
buses
bits
both
1.3.8)
inputs
at
the
The
than
bus
has
in
Section
an
inputs,
wire-AND
the
cells
through
each
that
shifted
and
the
the
a
to
flip-flops
via
pass
to
the
cell
an
with
X and
a
Y
in
(0
first)
I,
be
It
should
the
next
This
shift
pulses
or
to
a
on
depending
loaded
be
on
into
noted
cell's
CI
that
program
commutatiwity
programmed
the
(see
iteratively
from
corner.
of
result
single
bit
to
be
addition
Coincident
down.
the
wire-AND,
itself
or
array
buses
each
done
Figure
(including
connected
direction.
left-hand
function
output
sugges%ed
came
Y
(actually
_ND
be
edge
the X
lower
involving
leading
parameter
in
cell.
4.2).
connections
allows
with
{Figure
In
done
programmable
data
connect
is
been
shown
Y directions.
the
a
functions
paths
a
of
Two
flip-flops
cause
to
example
has
array[44],
neighbor
basic
OR
cell
one
research
arbitrary
and
pass
buses
other
cell
X
parameter
control
X and
both
of
programming.
Programming
Thirteen
register
synthesizing
nearest-neighbor
cells.
program
only
Wahlstrom
suitable
in
amount
gated
is
cell
seen
to
be
nothing
inverted
on
output)
to
of
its
outputs.
so
that
also
inversions
be
is
formed
each
available
are
using
of
X
or
all
its
The
functions
facilitated.
the
more
Y data
It
is
buses
-103-
_f
X data
buses
X neighbor
connections
_
_
_r
"
-•
....
>
),
X program
bus
':
Y program bus-'__
connect
ions
Y data
buses
Figure 4.1. Four cells
in the Wahlstrom array
-104-
Z
Z in
u
to next
lu
py
X1
'
Py ZB
PX
p
Zu
Py in YI
Coi nc i dence
Y2
3
detector
Figure
,
4.2.
Complete
Wahlstrom
cell
-105-
as
feedback
paths
A
of
the
all
short
a few
c-units
logic,
c-units.
On
used
to
functions
buses
2
to
are
are
2-input
set
in
a
In
coincidence
only
Many
single
signal
the
example
term.
In addition,
assigned
across
(using
X bus
into
array.
the
efficient
it
is
balanced
following
sections
to
some
the
we
also
felt
will
and
cells
that
be
a class
high-g
system
of
arrays
balance.
are
be
where
the
above,
I of
no
formed
3
the
data
more
than
in any
busing
problem
about
witlh a single
Thus
PL array
127
probably
shown
least
with
to the
present
of
this
will
array.
can
for
13 gates
to a cell
at
interferes
solution
properties
flexibility,
feedback)
the
_S flip-flop
entire
array
requires
flip-flop
and
reset
4 of
cell.
reader
approximately
logic
3 or
the
Wahlstrom
contains
a single
formation
efficiency,
each
route
Flip-flop
treat
cell
average,
convince
of the
to form
Overall,
an
the
will
necessary
flip-flops
signals
period
Each
performed.
is thus
row.
the
4.3.
inefficiency
assuming
be enabled
entirely
cells
and
functions.
of
likely
in Figure
experimentation
inconvenience
but
10
as shown
given
does
of external
of
not
exhibit
arrays
high-g.
which
and
In
attempt
relate
to
-106-
Set logic
Flip-flop
X data buses
I
Cl
),
C2--_
C3
'
c3
C1
C
I
II
'll
I
Reset
logic
Y data
buses
Figure 4.3. A flip-flop
in the Wahlstrom array
|
-107-
4.2
High-g
array
In
is
order
useful
have
the
already
numbers
of
trends
in
finite
to
a
cell
so
high-g
times
array.
universality
be
Indeed,
is
not
but
here
a
noted
increase
in
Current
only
into
PL
of
gate
this
both
be
components
by
time
faster
maintained
delays
chapter
component
to
are
how
kept
high-g
PL
count
conventional
a
cells,
propagation
should
control
to
ignore
indefinitely
resolve
more
We
altogether
numbers
compensated
in
arrays.
disadvantage
large
in
PL
which
methods.
additional
shown
here
no
it
is
proper
should
are
high-g
it
an_
technigues
in
tasks.
class
it
where
other
general,
particular
large,
learned
in
area
favorably
of
of
logic,
properties
designed
additional
with
should
gates
be
the
cannot
of
strong
will
groups
arrays
a
It
compare
large
one
that
of
this
we
be
cellular
synthesis
offset
type.
a considerable
Similarly,
A
It
be
involved.
minimum.
several
high-g
parallelism.
propagation
with
the
cannot
can
ordinary
use
gates
the
arrays
implies
Therefore,
the
with
some
often
can
in
or
PL
cell
effectively
efficiency
technology
in
generic
and
over
added
a
describe
components
necessarily
organize
any
how
and
more
to
extent.
gates
to
try
seen
particularly
due
deal
flexibility
inefficiency
are
to
to
determine
properties
those
of
that
although
universality
a
major
contention
goal.
Every
applications
not
be
in
:infinite.
involved
claim
in
array
we
are
will
of
The
matching
be
this
must
mind.
be
This
real
speaking
made
work
for
that
designed
class
lessons
a design
of
to
may
to
a
be
task
-108-
class,
not
in
4.2.1
High-g
making
array
Several
that
class
as
large
as
possible.
properties.
properties
a
high-g
array
should
possess
are
the
f o I io wi ng :
1)
Efficient,
synthesize
a
routing
and
between
or
to
other
primary
paths
Buses
order
may
to
fan-out
more
ma T
are
link
negation
in
redundancy
short
as
speed
local
T
and
transit
neighbor
use
and
in
buses.
where
array
inputs
and
their
they
become
faulty
arrays
must
but
be
with
are
These
crossing
avoiding
of
function
fan-in
Branching
signals
point
facilities.
while
large
connections
the
signal
particularly
possible
to
permit
from
connection
cells,
des iraDle
some
between
the
to
the
where
order
other
cells.
flexible
possible
and
high
in
joining
fan-in
and
forming
any
needed.
simplify
input
as
of
other
to
be
Clearly
given
design
kept
used
fan-out
must
cells
routed
points
In
arcay
between
be
the
building.
an
as
must
signal
efficientl
capability
well
cells,
passing
be
to
as
to
in
path-
f_actions,
entry
be
paths,
transfer
cells
concern
should
signal
of
Variables
generation
a
variety
outputs.
inputs
flexible
redundancy
two
problem
the
a
cell.
in
path
path
mast
cells.
of
or
For
structure
This
the
cell
by
fault
is
be
available
redundancy
function
allowing
can
by
also
be
permitting
permutation
avoidance
mandatory.
in
and
of
used
to
signal
variables
repairability,
-109-
2)
cell
function
must
be
is
on
to
a
be
functions
are
realized
that
cascading
combinatorial
of
cell
inputs
the
of
The
as
to
cell
most
many
without
At
function
cells
number
the
same
is
a
or
number
complex
it
group
of
straining
of
of
variables
cells
time,
too
the
memory,
unduly
the
which
when
some
function
suitable
used.
Whether
contains
minimize
_artially
a
or
desired
so
only
synthesis.
the
structure.
chosen
function
perform
subset
connection
must
flexible
purely
able
functions
the
Efficient,
it
whose
must
simple
can
logic
b.lock
be
cause
is
s yn th esiz e d.
In
shown
the
[31]
that
functional
to
be
at
BAND
gate.
of
rather
than
as
Some
This
can
different
may
be
fault-avoidance
3)
building
the
and
Balance
often
routing
the
repair
desirable
problem
when
have
and
shown
than
further
the
results
a substantial
flip-flop
feedback
is
in
in
path
each
between
cell
two
array.
is
in
functions
requiring
a
has
desirable
module
some
array
one
variables
redundancy
An
have
to
"WOS"
gives
Part
are
3-variable
probably
the
appropriate
asymmetry
should
redundancy
input
addition,
functions.
by
functions,
3-variable
4._
Wahlstrom
ease
His
Section
form
the
of
a11
memory
in
types
synthesizing
3-variable
amount
combinatorial
blocks.
better
concerning
of
certain
building
3-input
gates
case
by
forming
several
cell
the
allowing
a
a
cell
choice
particular
outputs
function
capabilities
independence
in
from
can
of
between
an
the
greatly
function.
between
function.
It
function.
In
enhance
the
function
and
array.
the
cell
-110-
the
interconnection
design
is
structure.
always
overloading
of
necessary
important.
the
use
structure.
of
A
certain
between
cell.
an
It
is
the
Wahlstrom
with
the
the
4)
cell
and
used
function
or
control
so
as
Encoding
parameter
flip-flops
flip-flops
and
Wahlstrom
_3states
are
a
of
gate
contains
neither
13
be
nor
a
through
in
signals
each
cell
particular
a number
to
gates
and
minimize
possible.
flip-flops,
useful.
define
paths
and
signals
of
should
signal
delays
control
parameter
in
necessary
control
to
of
purpose.
are
used
parts
routes
done
a
should
deficiency
structure,
whenever
distinct
and
gate
cell
terms
One
of
himself
signals
Given
functions
be
more
logic.
additional
the
example
functional
either
The
the
an
independence,
for
gates
in
are
and
can
control
result
interconnection
it.
routing
the
Minnick
these
control
may
a
all
the
functions
efficient
should
control
cell
of
route
scheme
or
one
minimize
to
one
facilities.
to
attempt
pass
Only
with
cause
the
forms
and
can
and
it
and
function
parts
that
functions
cell
and
separation
to
of
of
as
disturbing
use
parts
cells[22]
without
not
conjunction
components.
the
is
these
in
control
of
is
flip-flops
designed
the
desirable
Efficient
parameter
of
often
cell
functien
scheme,
path-forming
logic.
logic
an
various
routing
cutpoint
the
cell
same
in
cell
amount
already-active
and
the
connection
[21 ].
a
both
Minnick
acknowledges
exist
paths
A too-complex
The
too-simple
between
A too-simple
available
variables.
inefficient
Balance
be
they
number
into
of
the
parameter
Notice
that
while
most
-111-
5)
Diagnosabili
diagnosable
defect
from
should
cell.
No
4.2.2
not
defect
cell
Figure
4.4
in
parts,
the
the
function
prevent
shows
(INs)
outputs
to
these
The
external
in
some
cells,
detailed
level
The
F
from
currently
that
they
main
the
a
the
and
detected
defective
defects.
model
It
consists
thus
to
to
(IBs)
are
and
of
in
array
be
basic
the
cell
inputs
from
through
buses
inputs
these
In
to
control
the
inputs
are
which
are
outputs
P are
buses.
separate
useful
C
(OBs).
Parameters
via
clearlx
2
will
(P).
as
cells.
will
of
parameters
resulting
other
of
connected
use
we
and
group
(ONs)
and
to
form
A
which
C)
available
the
possible
F).
cells
are
P,
this
or
F,
except
Of
C,
at
and
a
P
very
discussion.
idea
output
known
other
control
from
and
always
but
of
beyond
cells
chapter.
function
parameters
not
of
schema
buses
by
exact
source
is
testable
Ideally,
(abbreviated
outputs
C
it
this
determined
through
course,
be
array.
conceal
neighboring
routed
a
cell
and
by
by
the
of
determined
set
to
(abbreviated
F.
back
able
nucleus
all
function
be
remainder
are
addition,
testing
function
of
C onnections
the
should
schema.
cells
a group
of
connection
or
neighboring
Arrays
edges
should
_ high-g
consider
to
the
ty.
s
can
traditionally
here
is
of
C.
be
simply
Virtually
characterized
use
that
inputs
of
taking
the
the
cellular
all
in
to
terms
the
cell
of
F
as
and
inputs
of
arrays
C
inputs
except
to
F.
-112-
--_
INPUT
NEIGHBOR
AND BUS
CONNECTIONS
_
_
I_
I
I
I
I_
>
OUTPUT
z
CONNECTION
FUNCTION
I
I
I
I
I
C
t_TI
CELL
_
I
I
FUNCTION
I
I
P
___._>
CONTROL
BUSES
_
CONTROL
PARAMETERS
I
I
Figure
P
4.4.
A high-g
PL cell
schema
_
NEIGHBOR
AND BUS
CONNECTIONS
-113-
In
the
traditional
the
correct
thus
to the
function
the
as
variables
inputs
proper
to be
must
to
to
at
input
able
perform
the
necessary
variables
in
dense
structure
can
be used
signals
inputs
many
to
permute
only
be
routed
particularly
in
In
the
function
and
specific
examples
This
the
cell
following
function
and
its
the
of
can
to some
arrays
at a
more
applications.
cell
be
In
each
F is
general
not
so
This
enough
imply
we
cells.
input
to be
very
using
simplified.
to
F.
C
Thus
than
highly
defective
level
to
of
a
By
rather
discuss
detailed
paths
either
to
often
number
arguments
seen
general,
directions,
greatly
containing
sections,
array.
used
is
and
]-variable
significant
incoming
will
a given
in creating
array
to pass
in question
arguments).
problem
the
facility
case
that
Any
F, the
to
one.
in the
inefficiently
partly
need
specific
pezmute
employed
cell
arbitrary
routing.
or
the
(assuming
within
are
example,
point
difficulty
transit
C as
cell
of
for
from
arbitrarily
considerable
of
Suppose,
of the
cells
inputs
be routed
in
outputs
the
a certain
results
path
surrounding
of F.
is desired
3 arguments
the
form,
to
a
useful,
cells.
the connection
and
give
some
-114-
4.3
of
Connection
the
4.3.1
functions.
Neighbor
connections
connection
structure.
Neighbor
of
literature
mentioned.
These
the
are
choice
arrays.
Murphy
several
major
neighbor
arguments
neighbor
refer
here
fan-in
which
must
Clearly,
function
represents
the
inputs
and
neighbors
output
neighbor
of
to
the
cell
important
parts
the
be
simple
the
Maitra
those
described
considerations
which
various
previously
l-output
cascade[18]
to
array
later,
Brooking
and,
in
C
The
strongly
for
function
the
[23]).
bear
facilities
connection
with
2-input
(both
F.
In
lower
fan-in
for
north
a
limit
near
high-
as
well
it
and
wishes
the
function
is
number
of
on
g
PL
as
to
cell.
could
(Figure
operate
a
_.5a).
in
and
However,
a
to
cell
signals
inputs
per
signals
a
similar
of
critical
outputs
of
If
use
as
number
connections
density
south
to
arrays,
total
the
each
example,
east
the
for
affects
and
the
cell
plus
north,
to
complex
to
number
west,
the
arrays
to
the
the
array
routed
through
neighbor
to
of
this
paths
of
of
themselves.)
the
I output,
to
of
the
this
Moreover,
number
to
The
factor.
cell.
both
addition
connection
connections
1)
from
connections
and
of
(We
in
connections
Spandorfer
the
extend
2-way
following
are
examples
connections
nearest-neighbor
the
contains
neighbor
8-neighbor
buses
connections.
The
kinds
and
the
and
has
]
from
its
pass
its
if
the
manner,
-115-
1 of
its
inputs
cells
must
purpose.
both
must
have
Since
have
Figure
we
through
I more
that
input
cells
connections
Regularity
parallel,
random
which
crossovers
In
cases
in
one
to
our
first
and
I more
are
both
cell.
north
Thus
output
identical,
the
density
cell,
these
of
4)
cell
best
the
and
south
both
for
this
cells
as
must
shown
at
can
the
in
the
required
to
avoid
the
used
to
If
few
interactions
an
array
be
number
can
inputs,
the
paths
low.
to
of
programmed
then
proportionately
related
random
among
simultaneous
closely
desired
array
is
connections),
of
and
paths.
highly
The
in
with
the
often
constructed.
it.
bits
frequency
is
inputs
aKray
patterned
while
the
data
within
direction.
number
are
affects
other
functional
can
more
word)
to
of
require
data
(i.e.,
array
group
An
the
path
through
Clearly,
choice
of
well.
have
If
suited
a
are
various
qualities
I
edges.
the
constructed.
regularity
functions
crossovers,
Directional
inputs
in
few
in
as
changes
the
sparse
two
function
This
between
paths
etc.)
last
feedback
of
with
(ease
generally
processing,
necessary
functionally
paths
on
will
data
formed
influence
functions
(along
Density
cross-terms
being
direction
direction
3)
long
and
are
functions
connections.
parallel
connections
be
example,
path
of
of
various
for
less
all
least
assume
performs
cell
routed
4.5b.
which
a
at
extra
2)
to
be
distribution
or
of
signals.
2
edges
paths
only
in
a
function
is
very
array
defects
in
the
and
whose
array,
Arrays
functions
direction
dense
then
away
or
if
connections
which
have
involve
from
no
those
feedback
allowing
is
-116-
B
(a)
AI
_-
> FI
CI
B. i2
A2----_
_ F2
LI
AI
;
_
; FI
T
CI C2
Figure 4.5. Adjacent
3-input l-output cells
-117-
propagation
in several
5)
and
Parity
inverted
points
in
provide
as
the
g iven
rectangular
Figure
4.6a,
it
cells
has
causes
gate)
directly
any
(Figure
the
or
addition
in
cell
signal
an
with
internal
6)
Input-output
array
via
,
edge
externally)
will
f ol Io w.
parit
be
seen
form
to
pass
is
used,
between
every
2
neighbor
case
requires
signal
are
not
nearest-neighbor
of
any
either
2
parity
selected
connections
the
easily
they
path
simplest
of
and
points
can
direction
Signals
neighbor
handled
via
toroidal
surface.
a
if
diagonal
upon
may
be
Thus
neighbor
connections
a
every
various
can
as
true
output
the
path
parameter.
unconnected
is
that
paths
requirements.
neighbor
to
the
at
structure
between
7 dependent
I/O
available
transmitted
of
constructed
control
if
the
both
facility
(the
permits
Alternatively,
Alternatively
torus
be
an
opposite
inversion
desirable.
signals
parity.
The
to
be
noted
available.
4.6b).
upon
be
of
length
arrays,
some
inverting
should
same
each
For
must
senses
connections
be
nearest-nelghbor
a single
botlh
probably
interconnection
by
a
I
nearly
signals
The
the
will
required.
of
array.
If
connection
only
signals
flexibility
C.
in
of
senses
this
through
directions
very
useful
may
paths
buses
be
at
(see
joined
The
feature
enter
and
the
next
(on
leave
edges.
section),
the
slice
or
continuity
of
the
in
the
examples
to
-118-
I,I I4 4 " :I:I
L_I !,1 4 1 4.i-"II!
t=3
|
.r--]
"L_._.A
,
,
(a)
(b)
Figure 4.6. Parity
rectangular
and diagonal
of paths in simple
nearest-neighbor
arrays
-119-
tl. 3.2
Bus
connections.
Judicious
s tr ucture
can
flexibility
of
use
an
array.
too
neighbor
connections.
is
and
long,
in
that
is
busing
the
cells
techniques
are
used
even
if
the
or
at
a
layer
circuitry.
This
much
those
in
area
enclosed
like
_.7a).
of
The
buses,
over
the
input,
an
entire
output,
(including
the
row
the
high-g
or
or
number
will
of
buses
route
have
led
to
cells.
the
or
same
same
than
simple
similar
different
the
cell
structures
array
is
be
a
bus
memory
can
It
manufacturing
time
which
connection
passing
interior
including
unit
over
ordinary
in
on
X-Y
lines,
for
created
very
and
signals
useful
to
are
power
(Figure
the
sections
then
repeated
thought
of
as
an
both.
X-Y
scheme
PL
problem.
the
in
potential
are
dependent
on
the
number
the
smallest
arrays,
the
of
been
it
bus
in
variables
has
array),
Each
whereas,
and
the
The
manufacturing
Wahlstrom
use
array
buses
dashed
Each
this
column,
functions
a
to
particularly
traditional
in
array.
Although
to
the
interconnection
to
different
has
the
directions,
themselves.
constraint
represent
used
structure
as
met alization
be
the
regularity
of
dea i
inconvenient
outside
the
part
great
can
This
from
as
a
Buses
or
outputs
desirable
buses
contribute
distances
inputs
of
is
reaches
practice,
such
a
available
not
in
in
several
really
cells
in
only
the
most
a
single
regular
Furthermore,
(or
fan-out)
on
the
array.
For
fan-in/out
arrays
well-suited
only
pattern.
fan-in
cells
used
will
go
the
each
bus
any
but
largely
-120-
(_a} Simple
X--Y bus|ng
scheme
o.
_b) Slanted
Figure
4.7.
busLng scheme
Busing
schemes
-121-
unused.
An
in
Figure
exactly
also
of
_.7b.
Note
1 bus
may
cell
be
more
each
in
flexible
cell
direction.
created
example
Fan-in/out
nearly
perpendicular
comprise
X-Y
that
identically
mY=l).
this
slanted
number
and
over
bus
connects
The
area
the
array.
semiconductor
scheme
,
is shown
as before,
in the
dashed
to
line
Alternatively,
layers
which
are
may
the
beneath
logic.
The
be
a new
in each
be repeated
buses
the
example
set,
at
of buses,
busing
shown
has
varies
set
with
various
and
arrangement
1 set
from
has
slope
angles
appears
buses
1 to 4 over
fan-in/out
fan-in/out
of
to
as
as
the
(aX=2,
varying
vary
with
slope
8 buses.
mY=l).
from
the
of
signal
In
a special
case.
Another
Eleven
I to
desired.
(aX=1,
3.
buses
Buses
may
distribution,
this
scheme,
the
-122-
4._
Cell
nucleus
functions.
Despite
numerous
lit erature,
little
synthesizing
arbitrary
blocks.
A
few
functions
have
MAJority
gates.
proposed,
including
discussion
which
is
logic
already
a
be
been
about
functions
cited,
general
made
general
from
small
using
easier
Yau
by
the
problem
of
logic
building
NOR,
a
rough
substantial
yet
unanswered
been
Further
separation
combinatorial
make
and
have
Tang[48].
making
and
logic
NAND,
modules
and
primarily
sequential
the
logic
by
in
particular
including
form
are
existing
the
"universal"
which
primarily
results
alqorithms
Several
functions
are
known
synthesis
will
between
specific
and
use
of
those
memory
e le me nt s.
_.4.1
Combinatorial
A
cases,
central
is
the
synthesize,
are
An
"WOS"
module
3-term
NAND
is,
of
for
this
one
by
of
is
apparently
it
because
of
inputs
of
a
his
less
its
"total
does
not
than
to
size
are
3-variable
with
the
functions.
WOS
module
half
asymmetry".
change
few
wish
results
3-variable
The
a
small
_B--C+BC+AC)
permitted.
of
we
isolated
by
all
than
given
compares
given
requires
more
functions
A few
synthesizing
that
of
Patt[31]
is
for
modules
task?"
variables
sense
permutation
or
function
task
input
the
overall,
while
the
a class
module
interesting
on
in
"Given
logic
(whose
Permutation
as
following:
efficient
available.
gates
question,
what
most
superior
functions.
the
as
is
many
That
function
.-123-
produced
by
by
a
a WAND
totally
conlectured
high-g
cell
NAND,
made
building
between
used
cause
alternative
some
and
only
one
n-variable
several
and
also
shown
Two
only
f unct ions
when
and
used
formed
passed
,n-variable
they
the
possible
to be
superior
will
be
of a function
A complex
simple
cell
function
used,
with
accompanying
is
formed.
a number
signals.
same
array
may
Another
of
inputs,
Alternatively,
few
input
variables
output.
the
usefulness
other
functions,
of a given
we
define
follows:
functions
generate
all
the
synthesizing
as
as
in an
with
evaluate
relations
investigated
points
control
from
for
array.
function
to the
better
in
to be
via
is
one
complexity
certain
a function
be disabled
to
the
A very
complex
It
section.
at
cells
gate.
comparisons
in a cellular
valuable
provide
can be
Further
this
inputs
of
function
when
in
overall.
function
if
symmetry.
produced
important
[26][2_]
be very
equivalence
is an
block
of
order
WOS
been
high
to
can
property
the
has
moderately
functions
In
and
is
of which
several
a
as
always
gate
numbers
when
such
is
majority
inefficiently
overhead,
function
The
functions
may
larger
module
asymmetry
importance
function
but
has
number
obvious
cell
it
these
The
have
this
functions.
yet
a different
asymmetric
that
a primitive
to
gate,
are
said
same
to
be T-equivalent
subset
transformations
of
of
all
if
n-variable
form
T
are
a pp lied.
In
the
context
of
PL
arrays,
there
are
seTeral
-12_-
transformations
duplication
rich
of
connection
functions
of
a
the
class.
the
cell
variables
is
useful
are
consider.
via
several
using
of
variables
input
a T-equivalent
these
class
convenient
In
control
of
Permutation
possible
performed.
be made
any
to
Negation
similarly
Under
Then
a
sufficiently
and
addition,
can
generate
member
may
output
modifications
parameter
simple
and
signals
within
transformations
any
be
other
any
member
selected
for
of
use
as
nucleus.
In
functions
the
of
considerable
16
remainder
3
as
Two-variable
different
require
too
of
this
variables.
interest
I)
=
input
may
nucleus.
the
q
2
be
function
of
it
structure.
can
member
which
The
2-variable
many
for
are
the
too
when
of
will
this
following
simple.
functions.
gates
we
functions
primitives
functions
section,
More
consider
class
reasons:
There
are
complex
synthesized
hold
only
functions
from
2-variable
f u nct ions.
2)
65,5.36
Four-variable
different
3)
3-variable
Few
b)
(data/enable/clock,
c)
4)
degenerate
_-variable
common
functions
a)
functions
Sum
often
carry
There
are
2&=
enable
of
2-variable
inputs
adder
register
set/enable
2
exist,
but
certain
used:
in
Three-variable
into
complex.
functions
:in a simple
Gates
Selector
too
functions.
4-variable
are
and
are
comparator.
transfer
reset/clear,
(like
or
SPDT
:functions
can
functions,
which
paths
etc.).
switch
more
are
=
&^BvA^C).
efficiently
often
needed
-125-
regardless
of
5)
the
range
Three-input
4-nearest-neighbor
input
the
80
connection
input
and
teftmost
column
own
given
That
minimal
equivalence
is,
each
class.
of
Note
the
that
permutation,
negation,
inversion,
and
functions
some
of
constants
0 and
I as
From
in
the
2 56
we
rightmost
column
are
of
structure.
generable
sequence
by
of
of
]
Thus
a
see
or
single
that
given
Table
4.1
as
allowable
particular
all
10
in
an
an
an
of
to
variables
to
_llowing
purpose.
functions
generate
under
could
function
3
3
same
all
all
of
all
these
be
appropriate
example
in
addition
3-variable
array
alone
well.
the
The
Duplication
va ria bles
3-variable
transformations.
as
input
identity
involve
further
sufficient
fewer
functions,
one
the
together
these
gives
these
nearly
by
4.8.
is
involve
serve
cell
Figure
functions
the
this
and
the
of
of
permutation,
under
functions
would
figure,
fun ct ions
any
inputs
in
256
each
extended
duplication.
which
degenerate
this
transformations.
of
the
a
3 variables
inversion)
218
represent
generate
into
for
input
classes
columns
the
of
summarized
Succeeding
allows
have
(called
are
of
syntheses
We
variables.
inputs
easily
functions
classes.
results
equivalence
the
negation
represents
transformation.
fit
transformations
output
These
functions
enumerated
equivalence
negation,
required.
scheme.
incombination,
duplication.
its
has
permutation
resulting
allowing,
fan-in
1-output
Hellerman[13]
under
of
capable
connection
the
functions
under
this
-126-
eo
C
0
m
E
L
0
W_"
_.
140 C
Om
W-.-- _
0-_
C
,_0
_-.-- u_
O.C
C
_0
W-.-- V)
0-_
C
_0
W-.-OX_
C
_0
._ u m
E cm
::I _""
Zq-"
U
n ¢) U
E>c
_ I _
Z I,_ W...
._ m u
E>c
:0 1 :::I
Z eq q--
._
E
:_
Z
._ m U
E>c
_ I _
Z 0 q,--
m u
>c
I ::::l
,--I q....
-127- -
The
functions
Identity
AABAC
function
under
the
Input
permutation
al I those
at left
plus
AABAC can generate
given
transformations
plus
input
negation
al 1 those
at left
plus
the
following
l
plus
output
Inversion
al I those
at left
plus
plus
input
duplication
al I those
at left
plus
AABAC
AABAC
AvBvC
AAB AAC BAC
AABAC
AABAC
AvBvC
AAB A^C B^C
_^_^C
Avi_vC
_,^B _^C _^C
AABAC
AvBvC
AAB AAC BAC
AABAC
AvBvC
AvB AvC
BvC
AvBvC
AvB
BvC
_vBv_
;(vB_vC B'vC
AvBvC
AvB Ave
ArC
A
B
C
A
B
C
0
class
Table
of AAB^_
k.1.
The equivalence
under
several
transformations
BvC
1
-128-
The
The
number
each
10
function
of
3-variable
function
Totals
are
because
dual
and
not
some
the
c-units)
higher
in
are
class.
If
listed
case
ranked
two
is
Note
by
Table
4.2.
the
in
both
the
according
to
are
degenerate
the
given.
and
the
of
the
size
the
synthesize
b7
functions
primary
generate
same
size
(requires
simplicity
{1}.
generable
inversion)
of
to
the
in
functions
functions
easier
first.
detailed
(obtained
included
are
which
are
degenerate
the
Functions
one
is
dual
additive
generated
class,
and
its
functions
classes.
total
by
classes
fewer
of several
of
the
functions.
It
is
generatinq
conjectured
the
largest
transformations
of
3
transformations.
all
3-variable
in
function
without
equivalence
are
functions
he,Fe
most
or
Note
classes
efficient
more
that
in
functions..
Classes
and
of
the
tinq
and
synthesizing
given
a _bitrary
these
I contains
3,
functions
under
under
class
I,
that
genera
variables
function
dual,
proof
4 are
all
same
over
each
38
I/3
of
capable,
degenerate
fun ct :ions.
It
should
mentioned
functions
admittedly
same
because
then
limited
asymmetry
function
also
and
they
classes
as
be
do
not
sense.
the
the
happen
1,3,
be
and
of
function
selector
out
compare
All
WOS
to
pointed
the
4
too
first
(class
function
self-dual.
would
each
that
several
previously
favorably
in
this
3 functions
have
the
However,
the
WOS
4).
(class
3)
are
If
they
were
be
capable
of
not
a
less
useful
self-dual,
total
of
86
-130-
functions
an
and
array
thus
without
would
function
versatile.
Of
course,
%_o
a
previous
invert
added
cost
of
The
or
ADD
these
to
are
this
is
than
Cell
all
6,
majority
Of
course,
and
is
to
due
these
are
I,
9.
it
2,
F4
3,
It
can
and
be
in
the
only
as
possible
so
the
Figures
class
all
the
]-variable
XOR
classes
symmetry
with
that
used
some
than
under
respect
of
others
class.
answered
these
for
and
&gain,
a
specific
primarily
for
synthesis
clearly
not
benefit
of
from
primitives.
for
6 functions.
synthesize
more
ability
inputs,
primitive
be
a cell
Several
the
be
the
smallest
argued
would
gates
in
other
commonly
intended
simply
can
high
Arrays
illustrated
is
their
can
is
implies
and
to
which
XOR
as
the
have
functions.
FI
well
function
functions
or
usually
would
in
small.
more
to
_Iternatively,
classes
generate
XOR)are
arithmetic
function
7,
This
task.
of
class
seen
question
other
functions
are
valuable
a
of
is
2.
these
as
majority
more
design
one
function
the
class
negation
transformations.
array
use
input
(e.g.,
thus
of
inversion,
3-variable
given
ahead
operation
function
functions
the
this
operations.
the
be
to
examples
4.9,
4.10,
contain
of
4. 11,
F2
F3
classes
10
classes.
than
possible
I function.
contains
more
is
and
cell
4.12.
capable
of
I,
4,
2,
-131-
B
E
total
c-units
Figure
4.9.
= 12
Cell
class
function
1 = 86 functions
F1
i
A
B
C
A
A
E
B --__B
P0
17
2*6 = 12
P1
class
29 c-units
1 = 48 functions
2 = 48
3 = 24
6i6
degenerates
= 38
174 functions
Figure
4.10.
Cell
function
F2
-132-
e
_
1
18
2"3 = 6
4*6 = 24
-48 c-units
-F
P3-_
class
1 =
2 =
4 =
6 =
7 =
9=
degenerates =
48 functions
48
24
16
16
8
38
198 functions
Figure
2:
4.11.
Cell
function
F3
i
A
A
C
p
C
P3
B
B
1
A
_g
A
•
gC
A
A
B
B
C
_
C
gC
OP_
P2.
38
3*2 = 6
4*6 = 24
all
all
i
68 c-units
Figure
4.12.
Cell
function
F4
classes
256 functions
-1 33-
Although
examples,
minimalit
notice
the
capability
shown
in
The
solution
ABC),
trivial
each
r ef er en ce.
with
7
nearly
the
of
its
is
not
linear
graph
of
providing
own
control
claimed
relationship
these
all
8
for
flip-flop,
of
between
functions
minterms
any
these
cost
(Figure
4. 13).
(A-'B--C,ABC,
is
also
and
shown
---,
for
-134-
0
0
0
.
0
_
0
0
L
0
Q._
E
c
,m
OU
0
0
-135-
4. S. 2 Sequential
In
PL
addition
arrays
is
to
will
arbitrarily
meaning
functions.
synthesizing
contain
divided
attached
commonly
called
the
what
is
basically
shown
the
possibilities
hand,
arrays
not
designed
to
automata.
It
two
areas,
memory
a
intended
be
is
on
this
as
hand
we
latter
On
tlhe memory
machines
group
have
what
is
done
have
the
other
function
or
that
be
the
researchers
approach[23[39].
for
may
being
processing
Several
sequential
this
one
some
group
difference
some
array.
primarily
used
On
where
memory
This
the
elements.
ok
functions,
elements.
logic-in-memory,
within
be
memory
into
to
combinatorial
may
finite-state
we
will
focus
our
has
been
viewed
a ttention.
The
synthesis
several
contexts.
general
problem
more
recent
automatic
not,
not
of
of
make
them
a
known
of
Another
by
Sterns[12][38]
an
general
for
total
has
to
state
A
for
machines
do
which
cellular
arrays.
assignment
problem
enumeration).
been
to
construct
sequential
presented
an
algorithm
which
arbitrary
state
the
the
way.
structure
in
in
the
procedures
These
patterned
imbedding
registers
with
describes
or
discussed
abstract
machines.
iterative
to
have
a fairly
Curtis[7]
solution
approach
table
in
sequential
amenable
(except
machines
assignment
papers
possess
sequential
and
state
realization
Furthermore,
is
Hartmanis
pair
however,
would
of
yields
minimal
the
employment
machines.
a
number
of
shift
Nichols[28]
mechanization
of
shift
has
of
registers.
an
-136-
Identical
shift
register
arbitrary
state
table,
publication
shift
do
by
modules
same
m-state
as
large
memory
and
register
more)
encoding
and
which
flip-flops
m,
e.g.
a
a
for
realization,
of
as
the
fan-in
and
a
of
the
m,
ificantly
For
functions
although
part
necessitated
more
of
m
create
by
state
less
tradeoff
the
of
cell
logzm
the
for
other
next-state
case
shift
can
vary
register
usually
small
them
required.
the
powerful
On
the
m-bit
of
of
machine.
flip-flops
states.
are
of
use
Obviously,
the
more
as
much
this
completely-encoded
loqzm.
with
flexibility
over
to
an
per
but
memory,
m=1024
necessary
fan-out
sign
for
the
then,
supply.
roWfor
decoding
flip-flop
combinatorial
to
100
next-state
The
require
as
of
of
from
to
involve
practical
elements
advantage
I to
in
one
array,
amount
the
circuitry
large
independent
can
of
use
tions
and
make
recent
pattern
order
signals
memory
PL
willing
cell
relatively
higher
order
any
identical
synthesized
to
considerable
a given
something
of
are
ratio
amount
the
be
in
high-g
suit
power
we
is
the
function
with
to
can
the
encoding
m
a
regular
However,
thus
and
function
active.
not
how
realiza
are
output
require
a
(on
could
In
in
modules
provide
realize
A
shows
these
implementation
adjusted
connections,
hand,
to
to
Newborn[27].
Newborn[2]
machine
necessary
circuitry.
be
which
elements.
information
connected
connected
of
m-state
be
by
However,
any
this
large
be
Clearly,
then
must
can
of
is
(or
and
many
state
shift
Tan,
numbers
each
A
shown
machine),
logzm
can
as
task.
unnecessarily
few
Arnold,
register
this
modules
are
encoded
and
version
interconnec
tion
-137-
structure
and
a
more
efficiently
utilize
the
In
showing
state
the
next
use
transitions
simultaneous
state
the
are
states
possible.
of
flexible
cell
available
section
a high-g
cells.
we
array
dependent
and
will
outputs
function
(See
present
as
upon
in
Section
a
inputs.
to
4.3.1.)
detailed
a sequential
dependent
order
example
machine
with
Additionally,
upon
sore
than
one
-138-
4.5
An
application
As
logic
in
a
analysis
we
of
this
in
units
The
data
arithmetic
running
mechanisms
memory
in
execution
the
Figure
The
programming
control
as
of
if
an
it
machine
and
some
some
may
associated
reg.=0,
machine
contains
step
the
and
look,
status
paths,
paths,
etc.)
which
program
two
be
many
to
a
words,
all
the
counters,
small
steps
and
their
submachines
thought
coroutines.
new
control
transfer
data
perform
the
basic
instruction.
these
a subroutine.
a
are
two
elements
(like
transfer
and
and
registers,
control
individual
of
the
elements--
register
concept
all
included
The
into
machine
sensors
shows
that
logic
proceeding,
divided
data
--
interactions
were
control
presented
Before
contains
requests,
4.14
interactions.
other
I/O
programmable
of
is
logically
the
control
enable
and
be
&Iso
etc.
which
issue
may
paths.
indicators,
example
processed
like
hlgh-g
problem
given.
register
program,
the
of
appropriate.
machine
being
data
is
call
circuits,
input/output
here
use
hardware.
will
data
the
detailed
is
Processing
the
the
area
computing
machine.
f lag
A
application
we
of
consider
in
which
with
will
this
Control
parts,
example
processors.
background
4.5.1
analysis.
specific
arrays,
central
and
The
instruction
of
Each
data
as
analogous
machine
machine
is
calls
signals
present
in
to
the
the
its
-139-
CONTROL
MACHINE
II
(
register
signa|s,
bits
'
i
ena
external
and sensors,
conditions,
gating
GO signals
terms
C.
DATA
MACH INE
Outputs
Inputs
Figure 4.14. Data and control submachines
-I_0-
instruction
register.
control
Several
machine.
issues
a
The
signal
register
the
to
is
machine
and
is
transmitted
machine
acts
on
this
data
machine
is
no
clock
The
(such
if
made
irregular
and
i mplementin
g
shown
issued
executed
microprogram
a
low
per
decode
which
signals
data
control
the
fixed
control
step
Fi(_ure
to
a
_.15a.
at
the
control
store.
the
device,
The
and
input
from
is
and
the
machine
control
for
to
store
in
the
word
to
and
occur
the
in
store,
structure
order
be
accessed
control
serve
in
control
signals
can
regular
is
Each
be
The
of
machine
output
logic
more
concept
Branching
output
A method
machine.
word
highly
control
much
word
signals.
a
The
very
control
the
regular
is
promises
the
next
input
etc.
of
circuitry,
Each
of
control
on
which
state
up
structure.
is
the
read-only
logic
random
determine
the
bit.
same
m icroprogrammed
cause
depending
usually
cost
The
in
which
from
a
the
for
next
paths,
ibi lity
represents
and
in
The
made
transfer
machine
flex
functionally
bits
and
receiving
Often,
the
primarily
the
control
mining[ 36].
contains
the
transfer),
with
the
example,
sensor
on.
to
opcode
machine.
so
proceeds
almost
an d
memory
that
register
control
the
for
fact
a register
is
of
exhibits
m ic roprogra
store
a
and
adders,
out
the
regularity
the
and
machine
--registers,
machine,
The
passed
time.
data
structures
causing,
by
as
also
machine
place.
to
are
interprets
detected
response
bits
machine
information,
operation
needs
following
zero
data
take
register
delay
now
control
to
transfer
opcode
to
encode
to
keep
with
and
the
-141-
conventional logic,
i rregula r
special cTrcuits,
.regu 1ar
__
f,"
Ca_ R[croprogrammed
control
....
machine
cellular
array,
regular
j/
input
State
,
logic
flip-flops
1
(b)
Programmable
Figure
4.15.
logic
array
Control
control
machines
machine
-142-
number
of
This
bits
logic
is
in
generally
The
goal
by
using
pursued
Figure
a PL
flip-flops
be
version)
are
all
will
between
control
this
arrays
realizations
of
1)
control
of
really
computers,
than
its
memory
angle
control
and
Better
each
and
the
control
the
_ollowing
same
control
are
wery
in
any
the
PL
version
different
counterpart.
m
(number
PL
Section
encoded
state
and
available
PL
to
with
make
control
a
fair
array,
Programmable
over
we
logic
microprogrammed
output
In
number
array
size
4.3.2.)
is
fact,
store
bit
contains
12
PL
cell
contains
200
for
fewer
bits
times
varies
a
as
function
c-units
c-units
Each
signals,
of
states)
Microprogrammed
bits.
potentially
of
now
components.
of
word.
The
the
of
has
this
machine:
wasteful
gives
of
in
microprogrammed
order
store.
advantages
uti lization
as
are
microprogramming
used
whereas
computers
of
shown
structure.
In
many
(see
cellular
further
more
logic,
the
store.
issuing
varies
outputs)
bus
the
stores
capable
are
have
to
be
states
or
output
control
type
range.
as
the
sequencers
logic,
the
can
machine,
define
correspondence
in
logic
control
register
Input
read/write
assume
the
flip-flops
imbedded
a reasonable
control
microprogrammed
semiconductor
comparison
as
Shift
direct
Several
a
array
used.
(no
within
irregular.
Individual
may
store
regularizing
machine.
versions
control
quite
of
_. 15b.
sequential
the
only
medium
and
a
of
the
few
large
components
of
only,
j.
(1 flip-flop
(as
a
be
m icroproqrammed
(number
-2m
must
but
total
in
9
word
one
control
while
Thus
and
if
the
each
2 gates)
described
in
-lt_3-
the
next
will
be
section
equal
does)
and
contains
I state
bit,
the
2
methods
at
m,j,1 2 = 2m.200
j = 33 output
or
The
DEC
PDP
8/I
small
2)
Little
microprogrammed
than
small
this
type
PL
of
3)
of
execute
command
active
addition
PL
PL
in
"overhead"
control
smaller
and
thus
to
be
as
with
used
sore
machines.
terminals,
arrays
of
at
and,
etc.,
utilize
more
parallelism.
a
time.
Small
can
the
possess
flexibility
importantly,
Most
Iny
number
connected
be
in
spare
"softer"
failing
5)
a
bit
words
Less
mined
in
greater
microstores
of
is
and
theory,
of
be
microprogrammed
only
be
in
control
a
discarded.
the
general,
can,
need
tolerance
diaguosability
their
array
If
must
m icroprogra
general
than
the
failure
arrays
place.
word
degree
the
control
diagnosable
its
permits
parallelism
Greater
to
fails,
logic
outputs.
PL
array
can
only
states
can
independently.
4)
I,
28
control.
variabilit_
be
This
control
about
irregular
controllers,
Greater
one
no
requires
microprogramming
display
several
of
or
control.
economically
computers,
computer
signals.
PL
in
array
a
machine
computers
to
control
increasingly
PL
discussed
more
store
to
enhance
store
important
dependence.
contain
If
use
fails,
addition,
usually
reliability
entirely
in
larger
In
a
another
redundant
are
in
In
Chapter
failure-tolerant
counterparts.
reprogrammed
In
d iagnosability.
PL
cell
cell
the
paths
in
whole
can
whereas,
unused.
be
in
This
machines.
practice,
significant
and
most
machine
-144-
dependencies
encoding
in
of
the
must
associated
machine
being
"tuning"
array
store.
assume
a
store
fit
depends
the
machine
on
the
data
fan-out.
Microprogrammed
machines.
In
of
inputs
control
computers
due
to
the
logic
addition,
the
store
branching
structure
function
it
can
said
requires
onl_
and
machines
the
in
The
terms
therefore
equiwa
on
an
the
efficient
considerable
associated
are
and
depend
that
characteristics.
outputs
control
which
be
concept
than
partly
specialized
machine
and
is
by the
words
Overall,
data
number
This
certain
the
between
in
microprogramming
states,
compatible
store.
addressing
controlled.
of
to
signals
control
control
utilization
control
control
surrounding
mechanism
the
lent
of
PL
control
number
fan-in
much
PL
of
and
less
control
.-1_5-
4.5.2
The
control
The
functionally
the
array
cell
in
to
Control
P
connections
in
connection.
Each
and
used
1 of
is
both
the
The
outputs
the
output
this
north
4.18,
a
and
to
The
shown.
of
logic
The
and
AND
4
and
4 neighbor
The
inbus
the
true
deriwed
4.2.2.
I
among
from
are
is
passed
the
flip-flop
signal
or
outbus
3 of
outputs
and
show
nearest-neighbor
from
which
shown
to
Section
inbus
function
selects
is
1
is
outlined
in
are
selects
All
arrays
F are
giwen
and
function
the
control
There
F.
AND
signal
Detailed
C
output
which
neighbor
our
schema
selectors.
outbus
4.19.
not
of
south
and
cell
an
circuit
signal.
the
outputs
flip-flop.
through
in
Parts
neighbor
inputs
to
used
directions
as
passed
GI.
4.16.
to
section
inputs
be
Figure
relationships
cell
one
or
also
to
passes
inwerted
the
the
are
first
sense
of
of
the
both
outputs.
of
total
the
cell
is
given
number
of
c-units,
in
Figures
including
4.17,
control,
is
C section
-
Y
- 23
section
P section
-
84
90
197
The
normal
delay
delay.
The
inbus
outbus
connection
through
input
1.
c-units.
the
requires
Transition
connection
2
additional
through
function
gate
the
F
C
delays
section
is
I gate
and
takes
the
2
Z
0
Z
0
Z
0
Z
0
IO0
0
[- ...........
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en
J
-148-
ONE
Figure
, ,, :
4.18.
F section
of
cell
G1
P'.... ..:
Load
Figure
4.19. Control parameter
register
of cell
G1
-149-
gate
delays
plus
programmable
nature
condenses
all
Connection
inputs
straight
through
inputs
from
right.
other
between
inbus
IB,
F,
both
for
function
be
next
variables,
outbuses.
other
turning
west
can
only
F
or
section,
machines
are
function
the
is
lag
to
F,
the
and
cell
GI.
with
the
connections.
of
left.
straight
4.20
diagrams.
option
or
passing
Neighbor
through
from
or
any
turn
point
to
complete
connect
ions
selector
function
are
the
option
of
exiting
an
of
the
gated
excluded
AND
with
a
from
the
flowcharts
be
state
the
flip-flop
S.
cell
on
2 of
which
are
flip-flop
so
that
be
seen
function
outputting
is
(on
to
the
function.
so
same
bus)
bus.
OR
either
which
tables)
inputs
a
small
primarily
gate
will
state
that
of
are
a 2-term
the
As
equivalently,
functions
functions
40Ns,
parameter
arranged
AND
OR
wire-AND
(and
easily
primarily
similarly,
inverted
inputs
the
routing
necessitat
forms
can
OB
flexible
along
array
right
go
program
possible
have
the
sides.
input
included
The
cells
or
_ND
in
to
due
Figure
shown
various
cell
Other
to
used
south
have
The
these
an
S each
be
delays
minimized.
are
the
allows
the
been
and
without
2 opposite
flip-flops
is
structure
Each
:in the
the
of
negated.
may
north
neighbors.
and
will
of
from
Thus
necessary
which
and
(IB),
have
parameters
geometry
point
all
the
it
function
east
This
cell
time.
information
the
Neighbor
or
the
represeDtation
Notice
any
flip-flop
of
the
and
symbolic
the
and
results
to
state
number
of
formed
by
the
itself
in
OB
an
OR
the
with
-150-
-151-
4.5.3
Input/output
Input
of
buses,
and
slanted
outbuses
is
likely
to
complexity
of
the
which
is
imply
given
array
in
is
input
This
results
each,
and
Similarly,
more
inbus
outbuses
ewery
bus
more
fan-in
connected
buses
goes
in
the
fewer
from
parallel.
control,
a
neighbor
can
with
low
one
bus
of
the
any
angle
to
be
of
fan-in/out
to
in
of
due
make
the
target
to
the
array.
connections
formed
_5
cell.
fan-out
points
an
distribution
duplicated
inbuses
signals
and
a different
separated
but
the size
bus
a greater
be
are
on
with
the
which
each
a
2 sets
of
dimensions
with
through
may
output
the
(each
buses
paths
and
j are
hawe
inbuses
to
outbuses,
achieved
at
intend
fan-in/out
will
awailable
shorter
high
i and
slant
From
fan-in
Maximum
of
These
we
More
is
The
by
characteristics
which
required.
where
handled
signals.
greatest
signals
signal
in
the
number
etc.
in
machine
is
4.3.2.
the
output
maximum
i.e.,
decoding,
the
j),
maximum
i_j,
match
angle.
This
The
same
be
max(i,
cells.
just
of
a steeper
Some
opcode
made
:in Section
best
data
arrays.
G1 arrays
:for the
in
will
by
degrees.
I)
be
(;1
for
described
to
found
of
fan-in
as
be
can
timing
output
chosen
estimate
fan-in,
and
to
cells.
from
2 or
-152-
Although
times
in
easily
propagation
this
discussion,
determined.
extending
from
the
machine,
data
machine.
As
within
data
going
assume
propagates
A
The
inbus
next
rising
Clearly,
edge
of
of
clock
cycle
rate
is
to
involved
an
in
a
(i.e.,
limited
the
time
then
(by
by
the
width
between
width
less
the
edge
of
the
through
in
the
control
(SI
and
c,
while
control
c.
S2)
the
the
some
of
machine
This
rising
A_B
edge
signal
register
of _,
condition
tlhe control
function
rising
be
with
inbus
between
must
string
which
in
as
the
machine.
sets
$I
at
the
t2,
and
c.
time
(the
not
c.
detects
the
states
also
then
on
is
machine,
with
becomes
times
c
between
B(sets
f(B)
back
it
propagation
the
edge
must
of
where
limiting
"_
Similarly,
it
rising
rate
flip-flops
with
several
logic
level
clocked
begins
the
clock
data
same
state
are
clocked
true,
sensor
2
mentioned
a typical
the
the
array
sequence
At is
turn
edge
The
t3.
in
the
on
feeds
is
done,
outbus
If
and
to
B[ is
$2
register
register
to
the
the
enable.
shown.
machine
control
state
to
transfer
control]
back
been
maximum
shows
and
the
actual
_.21
flip-flop
into
the
hate
Figure
commonly
of
register
We
the
is
cells
times
of
be
the
c)
path
than
the
than
entirely
total
greatest
c)
rising
cannot
longer
a
the
of
be
of
cannot
edge
less
internal
the
shown
edge
it+t2.
cycle
of
are
c
tl,
and
be
c and
than
t2.
In
the
The
and
the
rising
than
the
the
array),
maximum
t3
tl.
rising
The
addition,
to
the
less
of
time.
t1+t2
as
total
time
t3,
clock
intervals
-154-
throughout
the
Therefore,
we
the
will
The
try
to
flip-flop-to-outbus
between
so
machine.
as
state
not
@.5.4
to introduce
In
has
given,
as
machine.
an
The
Figure
@.22.
will
Rosin
survey
machine
with
a PL
made
in the
next
Figure
flowchart
gives
code
has
been
a
Control
in
and
state
this
state
states
flowchart
need
not
The
(to about
by
for
this
the
and
paths
10 cells)
machine
improved
the
reproduced
for
by
the
as
will
two
in
6 simple
allowing
microcode
between
hypothetical
is
transfers)
this
Rosin[36]
a small
microcode
register
for
name
this
if
any
as
much
possible.
The
be mechanized
versions
will
be
is
2,
I,
differs
any
may
be
edge
conditions
are
3,
from
opcode
_ and
6,
state.
signals
machine
in
Each
box
ADD,
8 and
9,
of
from
satisfied
is
to be
thought
of c)
conventional
other
control
in a GI array.
output
rising
the
Rosin
synthesis
ann
the
Thus,
feed
the
flowchart
whose
active
possible.
on microprogramminq,
represents
along
states.
paths
section.
(at
or
in
suitable
paths
as
be limited
of
comparisons
instantaneously
all
inbus-to-fllp--flop
microcode
4.3
@.23
form
contains
the
represented
array
be longer.
machine.
Table
(simultaneity
usually
delay.
diagram
parallelism
will
short
also
block
The
control
as
article
example,
commands.
times
the
additional
-the
a recent
keep
paths
flip-flops
An example
t1+t2
any
to
then
12,
the
next
state
state
sequence
of
Notice
how
flowcharts.
A
15.
states
passing
active
the
sequencer
Several
as
issued.
can
be active
-155-
I s_ I
i
CLAC--_
AC _-_AC=0
(---- RS
Store
/_
I
SAR
i
LC
t
l
,R (AP)I
i
]
'_-_ I
AD
(I0,11,12)
to control
AC-
Block
accumulator
mo-
IRSARLCAP -
10,11,12
4.22.
control
I
SBR - storage
(__
Figure
to
l
_--ws
CLAD
I
_
diagram
buffer
register
instruction
register
storage
address
register
location counter
address part of IR
- opcode
of Rosin machine
bits of
IR
-156-
Instruction
:
LC.SAR
RS, LC+I.LC
SBR.IR, CLAD,
Fetch
branch
on IR
ADD
:
AP.SAR, AC.AD
RS
SBR.AD
AD.AC, go to IF
CLA
:
AP.SAR
RS
SBR.AC, go to IF
STA
:
AP.SAR, AC.SBR
WS, go to IF
TRA
:
AP.LC, go to IF
TRZ
:
if AC=O go to TRA else go to IF
STZ
:
AP.SAR, AC.AD
CL AC
AC.SBR
WS, AD.AC, go to IF
Table
4.3.
for
Overlapped microcode
Rosin machine
-157-
LC+SAR
I0
11
12
opcode
0
0
0
0
0
1
TRA
'"
0
0
1
1
1
1
1
0
0
]
01
0
1
0
TRZ
"
CLA
STA
ADD
LC+I..LCs2
1
1
1
STZ
SBR+I R
CLAD
_'11
•
'.-2
AC+SBR
"_
I
AC.SBR$I31
S3
--v
AC=O
s,I
I AP+SA.
s,l APN_
S;I
'-2
_I)_AC
RS
--
I At+A0
S41
$12
SBR+AD
I
Sl
,2
ol
DONE Sl
SBR.AC
41
I ws
s,,I
$
Figure 4.23. Flowchart and
instruction set for Rosin machine
-158-
simultaneously.
All
introduction
ocder
of
an
the
s igna ls.
Occasi
onall y,
defined.
However,
tlhe
function
give
directly
Experience
required.
in
Three
to
has
shown
the
them.
Figure
a
Figure
of
input
choice
by
of
to
the
the
perform
buses
any
can
speed
the
lengths
and
4.4
4.5
and
fan-in/out
states
as
many
was
assumption
he necessary.
cells
as
chosen,
are
made
to
(parameters
should
machine
be
array
without
could
results
easily
in
are
Rosin
was
about
the
as
torus.
access
shown
in
machine
here
made
prior
be
a
better
emphasized
assignments
and
the
are
busing
form
provide
of
states
with
programmed
operations
was
would
be
which
and
and
to
data
set
being
Tables
duplicated
bus
opcode
18
cells
and
This
in
states
path
are
It
done
array
additional
connections
flowchart.
set.
the
twice
of
the
the
states.
the
resulting
efficiency
on
as
are
extra
equations,
to
about
array
the
dependent
of
well
flowchart.
16
perform
of
opcode
6
in
the
size,
Edge
buses
specification
the
of
results
seen,
as
transfer,
fan-out
outbus
array
that
array
and
number
than
6 by
This
indicated
to
4.24.
4.24)
the
the
more
redundant
more
equations,
no
Thus
have
are
on
choosing
that
shown
we
corresponding
In
made
than
state
alterations,
this
array
fan-in
the
fan-in
as
control
these
occasional
reduce
of
to
of
that
as
the
from
the
knowledge
of
reprogrammed
same
to
number
of
s tates.
In
been
by
order
inserted
Xs
as
cell
at
to
random
simulate
points
parameters.
a real
in
We
this
have
array,
array.
assumed
several
These
that
faults
are
a
have
indicated
single
fault
-159-
Outbus signals
logic expression
AC.SBR
S5vS13
SBR.AD
S12
AC.AD
$4
AD.AC
S15
SBR.AC
S14
SBR.IR
S3
Inbus signals
I0
1
I
AP.SAR
$6
1
2
AP.LC
S7
LC.SAR
Sl
AC=O
GO
LC+I.LC
S2
RS
S2vS8vS10
WS
S11vS16
CL AC
S9
CLAD
,$3
DONE
S7VSllvS14vS15
Table 4.4. Inbus and outbus
signals for the Rosin machine
-160-
State
Logic
expression
States
enabled
Outbuses
enabled
Sl
GO
S2
S2
Sl
S3
S3
S2
S4
S3AIoAI
S5
S3AIoAT 1
S10, S11
AC.SBR
S6
S3AI 0
--
AP.SAR
S7
S3AI%A(T IVAC=O)
--
s8
S4AT 2
$9
S4-7
1
$4
S8,
S9
$13
SS^I 2
S14
Sll
SSAI 2
--
S8
RS, LC+I.LC
SBR.IR,
CLAD
AC.AD
AP.LC,
S12
SlO
S12
LC.SAR
S15
CL AC
RS
WS, DONE
SBR.AD
AC.SBR
sgAI 2
S14
St0
--
SBR.AC,
DONE
S15
S12VS13
"-
AD.AC,
DONE
s16
S13
--
4.5.
States
of the Rosin
S16
RS
S13
Table
S15,
DONE
machine
WS
-161-
Figure 4.24. PL array for Rosin machine
-162-
causes
In
the
the
associated
case
flip-flops
zero.
is
determined
each
fault
the
of
section
section
present.
the
of
I IB
errors
The
in
the
expected
one
several
cell.
cell
A
to
are
assumed
underlined
typical
p=.001.
proportion
to
the
(see
I OB
varying
Chapter
1 F-S
severity.
number
for
number
2).
error,
to
0
array
•
36
• e
=
be
7.1
all
permanently
of
in
faults
These
errors
of
components
Three
C errors
error,
is
-.001
197
a cell,
parameters
_ total
this
inoperable.
of
selection
of
cell
become
section
technology
error,
of
the
P control
faulty
a
randomly
of
the
by
assuming
introduced,
in
reflected
sections
selected
a
beyond
This
affected
of
section
faults.
and
of
the
was
were
in
were
3 control
9 faults
are
-163-
4.5.5
Analysis
Several
the
last
this
application.
comparisons
section.
3 6_ 197=7092
machine
of
The
c-units.
to
execute
the
*
However,
as
reverses
for
IBm
words.
were
360/65
If
given
the
example
given
represents
semiconductor
bits
words
per
in
a total
:in
of
microprogrammed
control
Table
require
4.3
would
word
bits
per
.3840
160
c-units
c-units
overhead
4000
c-units.
version
requires
out
somewhat
2000
of
2000
100
10
2,000,000
the
bit
about
Section
77
4.5.
machines.
utilizes
directly
.
in
larger
processor
transfered
with
array
c-units
pointed
only
6
12
+
PL
by
made
14 enable
bits
4 address
bits
2 condition
bits
320
the
be
microcode
20
16
Thus
6
A
about
about
can
into
were
As
a further
example,
memory
2800
used
a semiconductor
situation
would
be
logic.
this
and
of
this
store,
words
bits
per word
c-units
per bit
c-units
more
I,
a read-only
words
percent
required.
rapidly
100-bit
control
at
fhe
least
store
--16_-
._n equivalent
PL
control
5000
c-units
1,000,000
this
it
illustrate
does
into
The
present
a
version.
has
cell
when
approach
arrays.
faults
in troduced
serious
the
about
meaning
trend
smaller
more
If
per
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Another
several
have
c-units.
example
contemplated.
would
cells
• 200
Although
array
problem
same
in
building
would
be
into
the
to
technology
the
the
practical
larger
to
break
Rosin
is
machines
up
the
is
control
machine
equivalent
(p=.O01)
sense,
PL
array
microprogrammed
assumed,
about
- .001
4000
errors
would
be
errors
could
easily
Four
or
expected
more
would
microcode.
If
input/output
logic,
gate
In
Thus,
result
the
in
I
control
the
malfunction
words
be
necessary
or
more
the
entire
(a
in
of
store.
25
store
might
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in
the
Rosin
The
longest
path
in
the
microprogrammed
limited
PL
larger
practice,
by
control
arrays
propagation
arrays,
will
machine
however,
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path
lengths
generally
an
4
word.
increase
in
of
the
occurred
in
the
affected.
PL
array
is
version
versions
through
the
run
these
entire
both
say
of
operability
errors
path
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of
insure
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Each
percent
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be
larger
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The
delays.
likely
=
additional
components)
delays.
* e
be
13
is
6
would
gate
to
8
very
data
machine.
someqhat
longer.
slower.
This
is
-165-
compensated
for
microprogram
2 ways.
stores
stores
are
higher
fan-in
Read-only
in
often
may
be
somewhat
on
stores
sense
ma T
be
sacrificing
the
semiconductor
microprogrammed
array
require
individual
any
bus.
loading
since
are
they
only
parallelism
utilized.
Second,
slower
due
to
lines
in
the
used,
of
flexibility
higher
High
flip-flop
First,
lines,
used
fan-out
but
durinq
None
than
is
these
of
that
programming
be
not
PL
the
slow
of
without
arrays
lines
on
array.
a
on
PL
an
parameter
high-drive
the
or
in
required
only
and
memories.
but
required
can
buses
semiconductor
with
with
microprogram
driving
course,
stores.
possible
large
longer
possible
fan-in
not
lines
-166-
4.5.6
On
automation
It
may
programming
of
be
a
PL
than
Although
the
amount
designer
is
roughly
ordinary
less
at
with
narrow
the
in
fewer
at
width.
the
a
array
contextual
somewhat
given
in
The
themselves,
these
it
task
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topic
is
cases,
a
simplified
usually
be
in
is
search
in¥olves
and
asserted
done
the
tree
properties
is
for
logic
design
is
task
that
of
human
modules.
manipulated
two
:in the
the
easier
discrete
result
this
to
the
point
backtracking
programming
is
with
that
information
comparable
Due
point
design
Although
time.
arrays
of
programming.
this
array
version.
heuristics,
nodes
at
logic
any
PL
array
remarked
control
designers
alternatives
control
by
the
number
of
considerably
tree
which
:is
search
requires
ascending
several
the
regularity
automation
a fairly
of
of
the
straight-forward
way.
A related
theory,
it
repair
faults
sequence
is
is
I)
_
and
occurring
failure
An
is
3)
program
is
a computer
in
is
of
these
controlled
the
detected
extremely
loaded
Using
run
determines
4)
for
repairability
array
by
itself.
a
arrays.
In
PL
to
The
array
following
envisioned:
2)
parameters
possible
the
this
the
The
basic,
into
which
the
the
control
diagnoses
the
the
program
control
array{2}.
redundant
set
of
array
array.
primitive
of
PL
highly
very
location
systems
in
opcode
control
new
array
set,
piece
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by
piece
fault.
perturbs
the
original
control
-167-
array
parameters
5)
control
opcode
The
set
array
set
In
which
so
to
avoid
altered
an
the
new
array
acceptance
defect.
parameters
test
is
is
loaded
r,an using
into
the
the
complete
systems
program
verification.
arrays
perturbs
programming
of
and
for
PL
as
the
the
array.
with
array
a few
spare
program
cells,
need
not
the
be
capable
of
fully
-168-
Footnotes.
I)
represent
whose
It
vertices
10
noted
the
passing
functions
is
I
is
to
ways
useful
a very
visualize
classes
unique
analogy
that
minterm
10 function
topologically
This
in
represents
Then
vertices.
of
be
3-variable
function.
the
may
of
the
are
simply
in constructing
way
to
each
of
of
the
equivalent
to
a cube,
in
selecting
useful
expansion
groups
of
arbitrary
these
groups
functions.
2)
It
interesting
is
many
failures
check
be observed
failure
This
stores
may
due
to the
can
generally
circuits
mode
but
that
shift
which
the
often
register
PL control
occurs-of
timer.
with
a simple
use
bits
and
catch
parity
virtually
it simply
encoding
be detected
all
the
accompanying
errors
array
states.
has
an
stops.
Thus
Microprogram
large
immediately.
parity
-169-
Chapter
5
Conclusions
In
this
programmable
A
of
feasibility
versions.
more
to
More
In
this
order
kind,
systems
the
congruence.
match,
fit,
the
and
design.
use
the
We
and
arrays
technology
of
such
technology
logic
has
than
programmable
have
work
have
can
other
shown
potentially
cellular
is
of
a
to
design
of
more
the
may
provide
forms.
than
research
of
larger
context
of
said
used
here
with
its
that
maximizing
to
the
design
refer
to
environment.
several
congruence
computer
hardware
logic.
which
exists
physically
large-scale
several
some
to
be
digital
in
field.
is
that
for
this
improve
PL
useful
of
cellular
is
conventional
that
design
have
contribute
be
it
the
discussed
to
in
congruence
available
d iscussed
also
point,
relationshi_
technology
have
viewed
levels.
examples
more
meaning
this
the
to
more
attempted
in
these
ways
global
of
demonstrate
in
be
of
of
will
concept
different
researchers
consistency
inherent
One
design
and
a
the
to
attempt
vantage
property
dissertation
through
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must
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we
which
attach
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The
relationships
in
work
From
tenet
important
following
to
design.
principal
This
to
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Several
coherence
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examined
given
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terms
and
at
been
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importantly,
abstract
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arrays
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be
understanding
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PL
research
we
logic
examples
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shown
further
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cellular
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integrated
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better
In
between
which
that
circuit
programmable
utilization
particular,
a
PL
of
offers
LSI
a
-170-
new
and
solution
to
improves
the
failure
As
a
in
general,
arrays
which
may
has
too
be
in
range
congruence
very
important
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of
functions
a
is
of
dimension
of
high
We
the
began
in
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in
to
arrays
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array
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which
of
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research
relating
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other
arrays
Therefore,
may
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Via
of
be
two
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of
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two
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to
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The
perform
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to
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it
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presenting
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a
In
feasibility
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systems
to
generality
machines.
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and
of
generality
design
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required
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generality.
demonstrate
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fundamental
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without
performed;
generality
use
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and
characteristic
in
discussion
design
functions
functions
functions
ways
of
specific
of
cellular
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on
relationship
asserted
affects
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only
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related.
between
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of
number
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Another
It
felt
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perform.
as
facilitates
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presented
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discussed
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problem,
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It
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arrays.
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or
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cellular
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areas.
different
versions
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-171-
an
array
intended
to
functions.
Despite
the
array
seen
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functions,
This
while
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An
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We
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cell
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than
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demonstrates
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numerous
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implementation.
discussion
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of
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contains
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derived
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Each
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register
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This
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for
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fact
literature)
outputs
inputs
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of
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area
arrays.
tlhat cell
is
the
cell.
with
that
cell
The
forms
the
cell
connection
_
number
of
-172-
properties
fundamental
to
problems
high-g
to
were
the
efficient
applicatio,
of
PL
also
discussed
and
to
this
related
arrays
cell
schema.
Several
improve
the
realizes.
angle
in
of
One
which
order
to
such
cellular
provide
array
PL
permutation,
Under
these
of
all
10
to
synthesize
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transformations.
As
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A
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of
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arcay
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and
over
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cells
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of
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includes
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256
shown
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capable
It
than
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of
high-g
functions
Several
gate
functions
.PL arrays,
nearly
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]-variable
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majority
10
generating
suggested
these
functions
functions
often
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in
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functions.
combinational
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It
consistent
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Several
all
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usefulness
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arbitrary
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concerning
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group
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efficient
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weakest
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to
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for
applicability
functions
and
functions
used
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been
generate
are
to
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synthesis
functions
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types.
3-variable
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has
transformations,
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developed
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involves
functions.
array
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buses
This
Some
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signals.
of
techniques
congruence
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under
same
when
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proposed
XOR)
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we
1/3
were
as
shown
comparison.
have
discussed
-173-
the
problem
was
of
control
presented
as
microprogramming
array
of
shown
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for
total
number
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that
with
small
computer
by
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algorithms
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that
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The
states
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conventional
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of
LSI.
Another
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PL
often
layers
order
of
to
actually
the
to
build
type
of
added
This
up
array.
in
this
work
some
research
build
costs
been
may
be
s
more
a
is
given
algorithm
defects
=equire
a
development
the
and/or
for
have
in
technology,
than
necessary
spontaneous
proposed
the
array.
arrays.
etc.,
perturbations
circuit
knowledge
one
algorithm
paths,
also
less
problems
of
LSI
is
PL
One
arrays
In
a
PL
appropriate.
between
using
type
was
Control
of
correcting
present
control
research
array.
local
It
(small) size,
PL
obvious
control
flexibillty
logic.
with
PL
diagnosability,
programming
and
on
the
and
certain
detail
most
ways.
very
scope
connections
more
work.
unprogrammed
Although
within
interesting
the
techniques.
in
of
concentrates
making
greater
a
required
implemented
several
an
above
automatic
approached
which
include
tolerance
array
conventional
of
microp_ogranming
number
suggested
of
components
was
the
(non-iterative)
machines
current
b
failure
control
advantages
control
irregula_
all
k PL
to
Potential
improved
elimination
computers,
alternative
microprogrammed
parallelism,
and
an
approach.
over
and
:in digital
are
more
in
of
the
largely
in
this
complex
layers
these
is
than
devices,
connections,
a
-17q-
layers,
slanted
buses,
important
possibility
slow-write
fast-read
the
PL
a
set
or
set
n-variable
of
ion
obtained.
investigated
is
in
the
Also,
that
of
parameter
an
using
part
Another
How
of
theoretical
the
the
algorithms
are
connection
most
topology
The
with
most
the
functions
should
arcay
cellular
of
and
of
in
cells
This
find
these
the
object
Then
of
the
the
class
that
of
testing
interconnection
testing
testing
an
function
procedures?
array
PL
with
What
a given
yield?
imbedding
extension
of
discussed
several
combination)
into
Comparisons
conventional
would
of
_fit"
is
the
functions
and
synthesizing
one
each
what
class.
various
in
in
desirability.
the
Given
outputs,
does
weight
object
specific
investigated.
forms).
its
of
expected
combinatorial
these
to
How
consideration
efficient
(perhaps
be
to
the
of
logical
effectiveness
is
flexibility
effectiveness
n?
optimizing
to
and
effective
given
functions
extension.
inputs
most
according
primitives
does
a
3-variable
deserves
cell
are
for
of
of
logically
possibility
one
the
usefulness
primitives
functions
by
arrays.
%he
of
functions
becomes
generated
The
of
Another
classes
affect
of
transformations
primitives?
do
be
elements
transformations
of
primitive
quest
be
control
discussions
certain
all
to
should
cell.
Our
under
etc.,
_Iso
serve
this
in
of
work
Section
these
be
methods
to
further
4.q.I.
high-g
made
(as
to
3-variable
a complete
should
has
cell
between
well
as
an
other
substantiate
-175-
the
applicability
Another
array
51.
vary
How
with
optimal
does
fault-avoidance
function
for
to
problems
remains
PL.
in
to
the
other
sore
be
seen
Hopefully,
Justification
for
the
a
given
whet her
further
shift
have
arrays
as
of
is
the
defect
well.
will
science
take
has
in
array
implications
computer
dissertation
interest
this
What
would
the
register
of
range
manufacturers
this
presented.
structures?
general
commercial
was
capability
connection
these
which
concerns
connection
and/or
significant
schema
complex
It
of
cell
problem
the
Solutions
community
high-g
specific
fault-avoidance
banner
the
increasingly
densities?
for
of
this
up
the
provided
technique.
-176-
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realizatioms.
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Department of Computer Science
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In recent years, technological advances have provided the designer of computing
hardware with the ability to batch-fabricate
large numbers of logic components on a
single semiconductor
slice.
Numerous researchers have investigated the synthesis of
various kinds of digital logic by using arrays of identical cells.
This dissertation
considers cellular arrays whose individual cell functions are determined by parameter
flip-flops and logic gates in the cell, rather than by a physical customizing operation during manufacture.
Potential advantages of this technique include functional
variability after manufacture, more efficient testing, andenhanced
failure tolerance
Arrays may be classified according to their generality,
i.e., the number and
range of the tasks which they are designed to perform.
Two significantly
different
examples of low-generality
arrays are presented and analyzed.
One, a shift register
array, is shown to be more effective than some conventional
techniques for creating
shift registers in the presence of numerous manufacturing
defects.
A new cell schema is introduced which exhibits properties important in the synthesis of high-generality
functions.
Techniques are presented for improving the
match between an array design and the target class of tasks.
As an example, the
problem of central processor control logic is approached in terms of a programmable
logic array.
A small computer is implemented in detail using these techniques.
This method of synthesizing control is compared to a more conventional microprogramming approach.
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