Parameter Variations
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Variations
Variations
Wafer to Wafer
Inter-die
Intra-die
Environmental
Process
Vdd
Device
Temperature
Interconnect
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Process Variations
W
T
H=ILD
S
Ground plane
Year
Leff
Tox
Vdd
Vt
W
H
ρ
1997
32
8
10
10
25
25
22
1999
33
8
10
10
26
33
24
2002
35
10
10
10
28
30
27
2005
40
12
10
12
30
34
32
2006
47
16
10
14
33
36
33
% variation from mean value
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Source: IBM, ISSCC’00
Sources of Process Variations
q
Film thickness variations: Tox is critical but is relatively well
controlled. Vertical variations caused by Chemical-Mechanical
Planarization (CMP); Inter-layer distances (dielectric
thickness)
q
Horizontal: Poly line-width & Leff variation comes from:
- Mask, exposure and etch variations (photolithography)
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Statistical Description: Lumped Statistics
L = L0 + ∆L
σL
∆L = N ( µ = 0,σ 2 L )
L0=µL is the sample mean of L, and σ2L is estimated as the
sample variance. The combined set of underlying deterministic
and random contributions are lumped into a combined
“random” statistical description.
µ=0
It is important to remember the basis for the distribution being
described, and to apply the distribution only to similar
samples. For devices on one wafer, the distribution (mean and
variance) for L can be different from devices within a single
die.
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Separation of inter-die and intra-die variations
Sources of parametric variation are separated into:
interdie and intradie variation.
Since the variation within the die - due to layout pattern
dependencies – may be larger than variations across
wafer, thus matching of devices is different on one chip vs.
on one wafer.
P = P0 + ∆Pinterdie + ∆Pintradie + ∆Pe
P0 = nominal design value
∆Pintradie = intradie variation (within a given chip)
∆Pinterdie = interdie variation (from one chip to another)
∆Pε = remaining “random” or unexplained variation
Variation in ILD thickness across wafer – across die
P indicates a structural or electrical parameters such as
W, tox, device parameters, Vth, channel mobility, coupling
capacitances, line resistances.
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Intradie Variation
It is the deviation occurring spatially within any one die. In contrast to interdie variation, intradie
variation contributes to the loss of matched behavior between structures on the same chip.
Two important sources for intradie variations are: (1) wafer level trends and (2) die pattern
dependencies.
(1)
(2)
Wafer scale variation can result in small trends that are reflected across the spatial range of
the chip. For example, some deposition processes suffer from a gentle “bowl” or concentric
ring pattern in thickness from the center of the wafer outwards. These can cause systematic
trends across the die.
Die-pattern dependencies can create variations that have become increasingly problematic in
IC fabrication. Two interconnect lines that are designed identically in different regions of the
die may result in lines of different width, due to photolithographic interactions, plasma etch
micro-loading, ..etc. Distortion in lens and other elements of a lithographic system are also
known to create systematic variations across the die.
Within any randomly selected die, wafer level variation can be approximated as a random bias
function of the coordinates of the die within the wafer. Due to the small die area w.r.t. wafer, it
is reasonable to assume that the wafer level variation can be modeled within the die as a
linear function of position:
Pintradie ( x , y ) = W (ω , x, y ) = ω0 + ω x x + ω y y
where ω denotes the coefficients ω 0, ω x and ω y are random variables describing the plane
(example: slanted plane)
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Supply voltage (V)
Supply Voltage Variation
Reliability & power è Vmax
Vmin è frequency
Time (msec)
• Activity changes
• Current delivery RI and L(di/dt) drops, wire
planning
• Within-die variation
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S. Borkar,
Borkar, “Parameter Variations and Impact on Circuits and Microarchitecture
Microarchitecture,”
,” DAC, pp. 338338-342, 2003
Vdd Profile
IBM Chip
0.13µm CMOS Tech.
160K Macros
8mm X 8mm
Vdd=1.2V
Power = 48W, 20% leakage
Hot Spots
Variations in Vdd = 3% to 15%
Hot spots = High power density regions
H. SuEE141
et al., “Full Chip Leakage Estimation Considering Power Supply
Su pply and Leakage Variations,”
ISLPED, pp. 7878-83, 2003
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Temperature Variation
• Higher temperature results in
slower transistors, higher
interconnect resistance and
exponentially higher
subthreshold leakage
Cache
70ºC
Temp
( oC)
Core
•
•
•
•
Activity & ambient change
Within-die variation
Floorplan
power distributions
120ºC
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S. Borkar,
Borkar, “Parameter Variations and Impact on Circuits and Microarchitecture
Microarchitecture,”
,” DAC, pp. 338338-342, 2003
Thermal Profile
IBM Chip
0.13µm CMOS Tech.
CPU Core of µProcessor
2.5mm X 4.7mm
Vdd=1.0V
Power = 5.6W, 20% leakage
Hot Spots
Variations in temperature = 0.8oC to 30.3oC
Hot spots = High power density regions
H. SuEE141
et al., “Full Chip Leakage Estimation Considering Power Supply
Su pply and Leakage Variations,”
ISLPED, pp. 7878-83, 2003
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Motivation
Increasing uncertainty in Timing
– Technology-generated uncertainty
– Process variations are increasing with every new
technology generation
– Coupling noise impact on timing
– Power supply variations and its impact on timing
– Inaccuracies in the delay calculator
Statistical timing analysis regarded as a key area in the
industry and in technology roadmap (ITRS)
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Normalized Frequency
Frequency & Subthreshold Leakage
1.4
1.3
1.2
1.1
30%
1.0
20X
0.9
0
5
10
15
Normalized Leakage (Isb)
Low Freq
Low Isb
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Source: Intel
0.18 micron
~1000 samples
High Freq
Medium Isb
High Freq
High Isb
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Vt Distribution
# of Chips
120
0.18 micron
~1000 samples
100
80
~30mV
60
40
20
0
-39.71 -25.27 -10.83
3.61
18.05
32.49
∆Vt(mv)
High Freq
High Isb
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Source: Intel
High Freq
Medium Isb
Low Freq
Low Isb
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Leakage with Vdd and Temp. Variations
Leakage considering environmental variations
• Accurate leakage model of actual Vdd and temperature profile
Hot Spots
Large leakage variations regions correspond to the hot spots
in the Vdd and Temp. profiles
H. SuEE141
et al., “Full Chip Leakage Estimation Considering Power Supply
Su pply and Leakage Variations,”
ISLPED, pp. 7878-83, 2003
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Temperature Dependence
q
q
q
Gate Leakage is unaffected by temperature
Subthreshold Leakage has an super linear relationship to Temperature
- At room temperatures, gate leakage is dominant for future processes
- At higher temperatures (where chips normally operate), subthreshold
leakage dominates
- This situation may change in future with technology scaling (Igate scales
faster)
For a 50nm device with 1.5nm Tox
S. Mukhopadhyay
et al., “Gate Leakage reduction for scaled devices using transistor
transistor stacking,”
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IEEE Trans. VLSI Systems, pp. 716716-730, Aug. 2003.
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Leakage with Process Variations
Monte-Carlo Analysis
NMOS
- Tox and Length have greatest effect
- The mean of length variations is not equal to nominal
- Larger mean and variance when all parameters are varying
PMOS
- Much larger dependence on length
Parameter
varied
NMOS
None
42.4
Nch
Tox
Ldrawn
All above
42.5
42.9
44.1
45.9
Parameter
varied
PMOS
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Mean Leakage Standard
(pA)
Deviation
1.8
9.0
9.6
15.7
Mean Leakage Standard
(pA)
Deviation
None
26.4
Nch
Tox
Ldrawn
All above
26.5
27.0
32.0
33.6
1.0
6.2
22.0
27.8
SD/Mean
4.2%
21.0%
21.8%
34.2%
SD/Mean
3.8%
23.0%
68.8%
82.7%
A. Srivastava et al., “Modeling
and Analysis of Leakage Power
Considering WithinWithin -Die Process
Variations,” ISLPED, pp. 6464-67,
2002
R. Rao et al., “Statistical
Estimation of Leakage Current
Considering InterInter- and IntraIntra-Die
Process Variation,” ISLPED, pp.
84--89, 2003
84
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Impact on Circuits and
Micro-architectures
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Path Delay
Probability
Delay Paths
Delay
Path delay variability due to variations in Vdd, Vt, and Temp
impacts individual circuit performance and power
Objective: full chip performance, power, and yield
Multivariable optimization of individual circuit—Vdd, Vt, size
Optimize each circuit for full chip objectives
by guard-banding
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Delay Paths: Problem of Correlations
gate delay pdfs
Arrival time pdf
Arrival time pdf
B
I1
A
D
C
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Clock Skew
q
Performance of high-speed
synchronous digital systems is
reduced significantly by clock
skew, even though the H-tree clock
distribution network is used.
q
When circuits run at giga-Hz, clock
skew becomes a significant part of
the clock period.
q
Random and wafer level variation
impact
Interconnect sensitivity analysis
Statistical Interconnect Impact
q
q
Skew
B
Leff Variations:
• Impact of PolyPoly -Silicon mask, lithography and etch at the chip level
• Each buffer (total of 65) has a unique value of Leff
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Interconnect Sensitivity Analysis
q
Take derivative of delay with respect to variable of
interest
-
Vt
Channel length
Gate oxide thickness
ILD thickness
Wire thickness
IR drop
Temperature gradients
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Control of Parameter Variations
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2000
1.5
1.2V
110° C
1750
1
Fmax (MHz)
Normalized operating frequency
Body Biasing Techniques
Forward Body Bias: Vt Modulation
450mV
0.5
1500
Body bias chip
with 450 mV FBB
1250
1000
NBB chip
& body bias
750
chip with
ZBB
500
0
250
0
200
400
600
Forward body bias (mV)
0.9
1.1
1.3
1.5
1.7
Vdd (V)
Intel’s 6.6M transistors communications router chip
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S. Narendra
On -Chip Body Bias in 150nm CMOS,” ISSCC
EE141 et al., “1.1V 1GHz Communications Router with Onpp.270--271, 2002
pp.270
Body Biasing Techniques
Reverse Body Bias: Leakage Reduction
100
1E--05
1E
110C
0.5V RBB
Higher Vt
Lower Vt
1
1
10
100 1000
Target Ioff (nA/mm)
Lworst
worst--case
1E--07
1E
1E--08
1E
Shorter L
0.01 0.1
Ileakge (A)
Intrinsic
Leakage 10
Reduction
Factor (X)
1E--06
1E
150nm, 27oC
1E--09
1E
0
Lnominal
0.5
1
1.5
Reverse V BS (V)
RBB
RBB reduces
reduces subthreshold
subthreshold leakage
leakage
Less
Less effective
effective with:
with: shorter
shorter L,
L, lower
lower V
Vtt,, &
& scaling
scaling
A. Keshavarzi
et al., “Effectiveness of Reverse Body Bias for Leakage Control in Scaled Dual Vt
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CMOS ICs,” ISLPED, pp.207pp.207-210, 2001
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Number of dies
Body Biasing Techniques
Adaptive Body Bias
too
leaky
too
slow
FBB
f
NBB
Accepted die
100%
60%
ABB
ABB
target
Frequency
RBB
f
target
within die ABB
50% of dies with NBB fell, but are
recovered using ABB
97% highest bin
For given Freq and Power density
100% yield
• 100% yield with ABB
• 97% highest freq bin with ABB for
20%
within die variability, compared to
0%
Higher Frequency
à
30% for ABB
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J. Tschanz
Die -to
to--Die and WithinWithin -Die Parameter
EE141 et al., “Adaptive Body Bias for Reducing Impacts of DieVariations on Microprocessor Frequency and Leakage,” ISSCC, pp.422
pp.4 22--423, 2002
Supply Voltage Control
Number of dies
100%
Fixed Vdd
74%
60%
52%
37%
20%
Adaptive Vdd
15%
6% 10%
0%
Bin1
Bin2
Bin3
Higher Frequency à
Bin improvement by adaptive Vdd
20% of dies are pushed from Bin1 to Bin2 +
recovered dies that fell below Bin 1
S. Borkar
Microarchitectures,”
,” DAC, pp.
EE141et al., “Parameter Variations and Impact on Circuits and Microarchitectures
338--342, 2003.
338
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Supply Voltage Control
Vdd Variation Reduction
With Die Caps
Without Die Caps
On die decoupling capacitors reduce ? Vdd
• Cost area, and gate oxide leakage concerns
T. Rahal
Rahal-Arabi et al., “Design and Validation of the Pentium III and Pentium 4 Processors Power
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Delivery,” VLSI Symp
Symp.. Circuits, pp. 220220-223, 2002
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When temperature exceeds
the threshold
1. Lower frequency
(activity)
2. Lower Vdd
Temperature
Temperature Control
This leads to a power consumption drop
followed by a drop in onon- die temperature
Tmax: frequency & power
Throttle
Time (µsec)
S. Borkar
Microarchitectures,”
,” DAC, pp.
EE141et al., “Parameter Variations and Impact on Circuits and Microarchitectures
338--342, 2003.
338
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