A 4-Bits Trimmed CMOS Bandgap Reference with an
Improved Matching Modeling Design
Juan Pablo Martinez Brito, Sergio Bampi
Hamilton Klimach
PGMICRO – Graduate Program on Microelectronics
Federal University of Rio Grande do Sul, UFRGS
Porto Alegre, Brazil
juanbrito@ieee.org, bampi@inf.ufrgs.br
Electrical Engineering Department
Federal University of Rio Grande do Sul, UFRGS
Porto Alegre, Brazil
hamilton.klimach@ufrgs.br
Abstract—Component tolerances and mismatches due to process
variations severely degrade the performance of bandgap
reference (BGR) circuits. In this paper, we describe the design of
a BGR considering the Pelgrom’s mismatch model. The main
purpose of our methodology is to convey the design to reach a
good trade-off between area and mismatch. Implemented in
standard 0.35µm CMOS technology, our circuit also includes a
straightforward 4-bits trimming circuit to achieve more process
variations independence. Its Monte Carlo temperature
coefficient average is 40-ppm/ºC and the reference output
voltage average is 1.230V. The area of the BGR is 400x350µm2
due to our design matching requirements.
Keywords: CMOS Bandgap References, Process Variations,
Trimming Circuit, MOSFET Mismatch Modeling.
I.
INTRODUCTION
The well-known bandgap reference (BGR) circuit first
proposed by [1] is the most used architecture for voltage
references. It is commonly designed to be insensitive to
variations on temperature, supply voltage and process
parameters. Much work has been done to improve
performance concerning temperature [2-5] and supply voltage
[6] variations. However, the development of high-performance
CMOS BGR circuits has been hindered by several limiting
factors attributable to process variations [7]. Even though the
stress in their design is mostly on temperature compensation,
process variations have the largest impact on the absolute
value of the reference voltage [8]. Commonly the various
sources of errors are Bipolar and/or MOS transistors, however
in many applications matching accuracy of resistors and/or
capacitors are also critical [9]. Hence, quantifying and
qualifying all these errors is a crucial step to predict trim range
and therefore to increase yield [7]. In view of that, in this work
we focused our design in order to afford the maximum
matching among circuit components. Even though is a
common task to set up a BGR circuit in many applications,
handling statistical design aspects is not often a standardized
step in the design flow. On that account, we develop further
the theory described in [10] and link that as a design variable
This work is supported by the National Science Foundation.
to reach the best size of each BGR circuit component.
Furthermore, to achieve more process independence it also
includes a straightforward 4-bits trimming circuit for adjusting
the zero-drift coefficient point in a wide range of
temperatures. In section II we describe the circuit architecture.
The design towards matching theory is developed in section
III. Section IV describes the extra-circuits like trim circuit. In
section V, some simulations and measurement results are
analyzed. The circuit was fabricated in AMS 0.35µm CMOS
technology. Finally, in section VI is presented the conclusion.
II.
CIRCUIT DESCRIPTION
For clarity and convenience, the analysis is performed
within the context of the bandgap’s basic building block. The
schematic is shown in Fig. 1
VDD
Q4
Q3
Q2
Q1
Q5
VREF
R1
5k
R2
5k
Q9
Q6
Q7
Q8
Figure 1. Basic architecture of the CMOS Bandgap Reference.
The current source proportional to absolute temperature
(IPTAT) is produced by differences between the emitter-base
voltage in the BJT transistors Q6 and the pair Q7/Q8 over R1.
 (W L )5 ⋅ k

I PTAT = I R1 = 
⋅ ln (N ) ⋅ T
⋅
W
L
q
R
(
)
1
3


(1)
However, considering the current mirror formed by Q3/Q5
and regarding the current through R2 the reference output
voltage must therefore be
 (W L )5 ⋅ k

VREF = R2 ⋅ I PTAT5 + VEB 9 = R2 ⋅ 
⋅ ln ( N ) ⋅ T + VEB 9 (2)
(
)
W
L
q
⋅
R
1
3


Deriving the equation as a function of temperature and
setting a zero-drift temperature condition, then
 (W L )5 ⋅ k
 ∂V
∂VREF
= 0 = R2 
⋅ ln ( N ) + EB 09
∂T
∂T
 (W L )3 q ⋅ R1

∂VEB 09
(W L )5 ≅ − ∂T
= 30.5
⇒ K REF =
(W L )3 k ln (N )V O C
q
 ∆I DS
 I DS
σ 2 

 ∆β
 = σ 2 
 β

2

4 ⋅ AVT

1  2

 =
⋅ Aβ +
2
(VGS − VT ) 
 W ⋅ L 

1
 ≈
W ⋅L

B. MOS Transistors
Threshold voltage (∆VT) and Current factor (∆β)
(β=COX.µ.W/L) differences are the dominant sources of
mismatching between MOS transistors. These random
differences have a normal distribution with zero mean and
their standard deviation depends on device area W.L and
device spacing distance [10]. For our purpose only area effects
are taken into consideration. Thus, the standard deviation of
∆VT and ∆β defined by two closely spaced identical transistors
are
(8)
 2 ⋅ AVT 

⋅ 
 (VGS − VT ) 
(9)
Consequently, the expression (9) infers about the minimal
transistor dimensions related to a minimum transistor current
difference error. It is dependent on the technology and on the
bias point. Hence, it can be rewritten as,
W ⋅L ≈
(4)
where KR=11%-µm for polysilicon in the AMS 0.35µm
CMOS technology [13]. Supposing σR ≤ 0.1% [7] as a start
point, it will lead to a device area of 12100 µm2. We choose
R=5KΩ to keep the polysilicon (50Ω/□) resistors not too
large, then their size goes to W=1000µm and L=10µm.
(7)
However, if we define a corner gate-overdrive voltage as:
(VGS – VT)m=2•AVT/Aβ, [12] and considering that in most
practical circuits (VGS – VT) is much smaller than (VGS – VT)m,
we may conclude that the effect of VT mismatch is dominant
over β mismatch. As a result, the equation (8) written as a
function of standard deviation can be approximated by,
 ∆I DS
 I DS
The following Pelgrom model [10] describes the standard
deviation between two rectangular devices dependent on the
area
2
  gm 
2
 +  I  ⋅ σ (∆VT )
  DS 
Therefore, for a transistor biased in strong inversion and in
saturation, the gm/IDS can be approximated by 2/(VGS – VT).
After substitution of (5) and (6) in (7) we may obtain,
σ 
A. Resistors
(6)
where AVT and Aβ are process-dependent constants. The
model valid for all regions of operation that describes the
variance for the relative current difference of two identical
transistors biased with the same VGS is defined by [11],
 ∆I DS
 I DS
In this section we would like to standardize our design
taking into account mismatching models.
KR
 ∆R 
=
W ⋅L
 R 
(5) , σ  ∆β  = Aβ
 β 
W ⋅L


W ⋅L
σ 2 
DESIGN TOWARDS MATCHING
σR
AVT
(3)
where k is the Boltzmann’s constant, q is the charge of an
electron, ∂VEB09/∂T= –1,826mV/ºC, N=2 to reduce the number
of components, and considering R1=R2 to all temperature
range. In this architecture KREF is the size ratio between Q5 and
Q3, or the current mirror gain. Equation (3) finds the ratio to
produce the stable reference voltage (VREF).
III.
σ (∆VT ) =
2 ⋅ AVT
 ∆I
σ  DS
 I DS
(10)

 ⋅ (VGS − VT )

Observing the curves of the experimental data provided by the
foundry AMS [13], the parameter AVT was estimated as
AVTPmos= 1.575%.µm.V and AVTNmos =1.42%.µm.V. Thus,
drawing square transistors and targeting an error less than
0.1% for each transistor current difference, then the
dimensions of each NMOS and PMOS transistor are:
2,84%.µm.V
= 77.2µm
0,1% ⋅ 0,368V
3,15%.µm.V
≅
= 68.5µm
0,1% ⋅ 0,460V
W NMOS = L NMOS ≅
WPMOS = L PMOS
(11)
For convenience the final transistors sizes were
WNMOS=LNMOS=80µm and WPMOS=LPMOS=70µm. Table I
presents the final size of the components.
TABLE I.
FINAL COMPONENTS DIMENSIONS
Component
Value
Q1, Q2
Q3, Q4
Q6…Q9
Q5, Q10…Q35
Q36
Q37
Q38
Q39, Q40
R1
R2
W=80µm, L=80µm
W=70µm, L=70µm
32.6µm2 (Vertical BJT)
W=20µm, L=20µm
W=10µm, L=20µm
W=5µm, L=20µm
W=1µm, L=80µm
W=10µm, L=1µm
W=10µm, L=1000µm-5KΩ
W=10µm, L=1000µm-5KΩ
IV.
V.
SIMULATIONS AND MEASUREMENT RESULTS
A test chip with analog circuits and test vehicles in
AMS0.35µm CMOS technology was developed. It is
composed by analog blocks like : OTAs, comparators, Gm-C
filters, Trapezoidal and T-Shape transistors and a Bandgap
Reference. Fig. 3 shows the 4.55mm2 chip microphotograph.
The BGR size is 400x350µm2.
EXTRA-CIRCUITS
A. Trimming Array Circuit
Transistors and resistors were calculated to reach our
matching specification of 0.1%. Since other sources of errors
also exist [8], for convenience we will increase the target
mismatch value to ∆VREF=±0.5%. We assume that the BGR
in the worst case may expect a variation of ∆VREF=±5%.
Respectively, it is defined as a least significant bit voltage
VLSB=0.5%• VREF and as a full-scale voltage VFS=5%•VREF.
Based on [14] the number of trim bits is determined by the
following expression:

V
ln FS + 1
V

 LSB
# Bits ≥
ln(2)
(12)
Since ideally VREF=1.2V then VLSB=0.5%•1.2=6mV and
VFS=5%•1.2=60mV. Consequently, #Bits ≥ 3.5 thus the trim
circuit of 4 bits. This feature was implemented through 4
MOS transistors having their gate (G) and source (S) terminals
connected in parallel to Q5, and the drain (D) terminal
connected to four additional output pads. The transistor sizes
were binary weighted in 2x steps (2W5, W5, W5/2 and W5/4).
Thus, the current through R2 can be adjusted in up to 16
levels, proportionally to the current that flows through R1 by
connecting or not these 4 Pads to the VREF node. The
schematic including a simplified view of the trim circuit and a
start-up circuit not discussed in this paper are shown in Fig. 2.
Figure 3. Analog test chip microphotograph.
A. Temperature Variation
The curves in Fig. 4 present the simulated output voltage
VREF as a function of the temperature for all the 16
combinations of the trim circuit.
Figure 4. all possible combinations of the trim circuit
Figure 2. Final schematic of the Bandgap reference
Fig. 5 shows the variation of the zero-drift point for
each of the 16 bandgap curves. The range of temperature is
from -75ºC to 75ºC. For instance, we are able to set up an
application specific bandgap circuit according to its working
temperature.
VI.
CONCLUSION
A bandgap reference was designed, fabricated and tested
in AMS 0.35µm standard CMOS technology. It was
strengthened for best matching among their components and
contains a trim circuit for final drift adjustment. A theoretical
approximation was done using a first order mismatch model.
Simulation and experimental results present good agreement,
meaning that our design strategy was adequate. A weak point
to consider is that we have measured a single chip sample. To
complete validate our design methodology we would need a
greater sample number. Therefore, the trimming and start-up
circuits match with our expectations.
ACKNOWLEDGMENT
Figure 5. Vo versus trimming range
Finally, in order to ensure the values found by our design
methodology in Fig. 6 is shown the Monte Carlo analyses. We
have used Monte Carlo Resistor and MOS/Bipolar Transistor
models for 1000 simulation rounds. We have set up the
analyses only for one trim configuration (trim=1001), because
the value of its zero-drift point is basically at room
temperature.
The authors would like to thank the CNPq and CAPES
agencies for the PGMICRO scholarship and support.
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Figure 6. Histogram of Monte Carlo simulation
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[9]
TABLE II.
SUMMARY OF MEASURED AND SIMULATED RESULTS
VREF (T=27ºC) trim=0000
TC (trim=0000)
Supply Dependence
IDD(T=27ºC)
Start-up time
TABLE III.
Simulated
1.1890V
40ppm/ºC
1%/ºC
350µA
2us
Measured
1.1732V
47ppm/ºC
1%/ºC
420µA
6.35us
SUMMARY OF MEASURED AND SIMULATED RESULTS FOR
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MonteCarlo mean
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VLSB
Specified
1.2V
60mV (5%)
60mV
6mV
Simulated
1,230V
92.40mV (7.53%)
64mV
3.5mV
Measured
61mV
4.3mV
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