Comparison of Bulk and SOI CMOS Technologies in a DSP
Processor Circuit Implementation
Piia Simonen, Aarne Heinonen, Mika Kuulusa and Jari Nurmi
Digital and Computer Systems Laboratory, Tampere University of Technology
P.O. Box 553, FIN-33101 Tampere, Finland
E-mail: piia.simonen@tut.fi
Tel. +358 3 365 4354, Fax. +358 3 365 3095
Abstract
Silicon-on-insulator (SOI) CMOS technologies are
very attractive options for implementing high-speed
digital integrated circuits for low-power applications.
This paper presents the layout migration of a DSP
processor chip from a 0.6 µm bulk CMOS to a 0.5 µm
SOI CMOS technology. The layout migration and
verification are described and the two CMOS designs are
compared using two main criteria: circuit speed and
average power consumption. For nominal supply
voltages, the simulations suggest that the SOI circuit can
operate at a speed of 98 MHz which is 51 % higher than
that of the original (65 MHz). The average power
consumption is 35 % lower in the SOI circuit by using
3.3 V and 35 MHz for both SOI and bulk CMOS designs.
1. Introduction
Today most of electronic circuits are realized using a
bulk CMOS technology which is a very mature
technology with low manufacturing costs, high
performance and good low-power capabilities. However,
both die size and power consumption of bulk CMOS
circuits will become increasingly difficult to reduce in the
future. This has given an opportunity for some emerging
semiconductor technologies. Among the most promising
ones for ultra low-power circuit implementation are
silicon-on-insulator (SOI) CMOS processes [1,2,3].
The ability to use a low supply voltage and to
simultaneously reduce parasitic capacitances are of high
importance in designing fast low-power digital
circuits [4]. Instead of a bulk silicon substrate, SOI
CMOS employs an insulator below a thin layer of silicon
which eliminates most of the parasitic capacitances found
in bulk CMOS processes. This allows SOI CMOS
circuits to operate with a reduced supply voltage thus
further reducing system power consumption and
improving speed. In addition, SOI technologies enable
the design of denser and more reliable circuits. Increased
reliability is mainly due to the absence of the latch-up
effect. Currently, the main drawback with SOI CMOS
technologies is their high manufacturing costs which can
be prohibitive for products where low system cost is of
primary concern.
This paper presents migration of a DSP processor
design from a bulk CMOS to SOI CMOS technology. In
the paper, the basic structures of bulk and SOI CMOS
devices are presented and the main differences between
the technologies are specified. The DSP processor chip
under migration is shortly described. Then the layout
migration, various verifications, and simulations are
studied in detail. The main results are summarized in the
conclusions.
2.
Bulk and SOI CMOS Technologies
Instead of using silicon as the substrate, as in bulk
CMOS transistors, an insulating substrate can be used to
improve device characteristics and circuit performance
[5]. SOI CMOS circuits consist of single-device islands
which are dielectrically isolated from each other and also
from the underlying substrate. Since there are virtually no
isolation constraints for individual devices, transistor and
interconnect densities can be very high [2,6].
The dominant capacitance in both bulk and SOI
CMOS circuits is gate capacitance. In bulk CMOS
devices every junction produces undesirable parasitic
capacitance as well. These junction capacitances do exist
in SOI also, but they are reduced by a factor ranging from
4 to 7 [7,8]. In Fig. 1, structures and parasitic
capacitances of bulk and SOI CMOS devices are
illustrated. The gate capacitances are not drawn in the
figures because they are approximately the same in both
technologies.
3.
DSP Processor Chip
The test circuit was a prototype of a DSP processor
chip developed by VLSI Solution. The processor was
implemented for a 0.6 µm bulk CMOS technology and its
design database was used as the reference design
throughout the migration task. Fig. 2 shows a transistorlevel layout of the DSP processor chip. The chip consists
of several functional blocks: VS-DSP1 processor
core [9], 512x32-bit program SRAM, two 512x16-bit
(a)
+
n
+
+
p
+
p
+
n
n
PLL
P-substrate
contact
+
p
PP
SP3
NMOS
Silicon gate
Gate oxide
N-well contact Metal
Silicon dioxide
RS232
PMOS
XRAM
YRAM
N-well
SP2
(b)
PMOS
p+
NMOS
Silicon gate
Silicon dioxide Gate oxide
n-
p+
n+
p-
VS-DSP1
PROCESSOR
EXT
PRAM
SP1
Metal
ROM
p-
Silicon substrate
n+
SiO2
Silicon substrate
Figure 1: Cross-sections of (a) bulk CMOS and
(b) SOI CMOS devices.
data SRAMs, boot ROM, three serial ports, 8-bit parallel
port, phase-locked loop (PLL), RS232 port for
connection to a personal computer and external bus
interface. The processor core, SRAM blocks, and boot
ROM block are realized using full-custom module
generators while other blocks are straightforward
standard-cell designs.
4. Layout Migration
The layout migration task begun with a design
database of the DSP processor chip. The transistor-level
layout was in L-language which precisely describes the
structure of the chip. The original layout is depicted in
Fig. 2. In the migration, the objective was to handle large
blocks at a time, to automate required modifications, and
to verify the migrated layout with extensive simulations.
The target technology was Peregrine Semiconductor
Ultra Thin Silicon (UTSi) 0.5 µm SOI process in which
the wafers are formed by depositing ultra thin silicon on
an insulating synthetic sapphire wafer.
Fig. 3 illustrates a 3-input NAND gate implemented in
bulk and SOI CMOS technologies. Even with these
simple six transistor cells the area advantage in SOI
circuit is clear. This is mainly due to the absence of wells
and substrate contacts and the possibility to align contacts
and vias vertically.
In the UTSi design rules, there was one limiting
constraint: the minimum spacing between a transistor
gate and a drain/source contact was 0.1 µm larger than in
the bulk CMOS technology. Placing the transistors
manually side by side in long rows would have required a
lot of time-consuming modifications during the
Figure 2: Layout and main structural blocks of
the DSP processor.
migration. In order to avoid this, all the coordinates of the
SOI circuit were scaled by a factor of 1.1 which, in turn,
increased the chip area from 23 to 27 mm2 (measured
without pads). The scaling and other modifications to the
design database were performed with Perl language
scripts. The scripts updated layer and transistor names
and removed all substrates and contacts related to them.
The inputs in a SOI CMOS chip are slightly more
difficult to protect than in bulk CMOS because of the
lack of substrate diodes [10,11]. Therefore, the new pads
were constructed using the pads provided in the UTSi
technology and some logic from the original pads. The
drawback of this approach is that these structures had a
major contribution to the total chip area.
5.
Verification and Simulation Results
5.1 Design Rule and Equivalence Checks
For the migrated DSP processor chip, the final design
rule checks (DRC) were performed using Cadence Diva.
Most rule errors were caused by the differences in
maximum via and contact matrix sizes between the
technologies. The next verification step was layout
versus schematic (LVS) check with Calibre. The SPICE
netlists extracted from the layouts of the original and the
migrated chip were compared to ensure correct wirings
and connections. In addition, it was possible to compare
transistor sizes at the same time. Due to difference in gate
capacitance, the capacitors in the design had been scaled
down to retain the equal capacitance values. These
200
Bulk CMOS 5 V
Bulk CMOS 3.3 V
SOI 3.3 V
SOI 2.5 V
SOI 1.8 V
Power / mW
150
100
50
0
20
30
40
50
Frequency / MHz
60
70
Figure 4: System power consumption of bulk
CMOS and SOI CMOS circuits as a function of
operating frequency. Note that the maximum
frequency of the SOI design with 3.3 V (98 MHz)
is not shown.
Figure 3: A 3-input NAND gate implemented in
both bulk CMOS and SOI CMOS technology
(grid 1 µm). There are no wells nor substrate
contacts in the SOI circuit and contacts and vias
are aligned vertically.
capacitors then caused several errors, so the strict
transistor size checks had to be skipped in order to make
the migrated design pass the LVS check.
The LVS verification tool allows very accurate
comparisons and thus produced lots of error messages
that were practically useless for our purposes. Mostly
these messages were due to the reorganization of the
supply wirings after removing wells and substrate
contacts from the SOI design.
5.2 Functionality and Power Analysis
In addition to the design rules and electrical
correspondence, the correct functionality of the SOI
CMOS circuit was verified. Both circuits were simulated
using PowerMill and the test vectors generated for testing
the original bulk CMOS design. Wiring capacitances
were not taken into account, but they are likely to be
coarsely the same in both designs. The tests for the DSP
processor chip covered executing various program
kernels up to 10000 clock cycles. Moreover, the
functionality of the processor core was verified
separately by several smaller test programs. Only
differences between the two circuits were found in signal
rise/fall times, as expected.
The UTSi SOI CMOS technology offers three types of
transistors: intrinsic, regular threshold, and low threshold
voltage. The SOI circuit was first implemented with the
low voltage transistors that have a threshold voltage of
±0.35 V. Interestingly, the initial power estimations
revealed huge leakage currents in the dense SRAM
blocks, even though the memories operated correctly
[11]. For this reason, the transistor type was changed to
the regular transistors with a threshold voltage of ±0.8 V.
With the low voltage transistors maybe even a supply
voltage less than 1.2 V could have been used. The lowest
supply voltage the SOI CMOS circuit operated correctly
with the regular transistors was 1.8 V, but then also the
circuit speed degraded significantly. The simulations
imply that 2.5 V is still adequate for correct operation
with operating frequency up to 65 MHz. As the nominal
supply voltage of the UTSi SOI technology is 3.3 V the
result was still very satisfying.
Both the SOI CMOS and the bulk CMOS circuits
were simulated with the same test vectors and program
code at the nominal temperature. According to all the test
cases, the currents in the SOI circuit are approximately
one third of those in the original bulk CMOS design
when simulated with the nominal supply voltages (3.3
and 5 V) and 50 MHz. The values given in textual report
of the simulation are 13.9 and 34.7 mA for the SOI and
bulk CMOS designs, respectively. Thus the calculated
values for the average power consumption are 45.9 and
174 mW. Therefore, comparing these two designs with
the nominal supply voltages gives a 74 % reduction in
system power consumption. When using a 3.3 V supply
voltage and a 35 MHz operating frequency for both
circuits, the reduction is approximately 35 %.
Fig. 4 shows the simulation results of both circuits
with different supply voltages and operating frequencies.
As mentioned earlier, 1.8 V proved to be the lowest
supply voltage for the SOI CMOS circuit to retain its
correct functionality. The corresponding value for the
bulk CMOS circuit was 3.3 V.
The maximum operating speed of the physical bulk
CMOS chip is 50 MHz. According to the Powermill
simulations, however, it was measured to be as high as
65 MHz. Also the SOI circuit was simulated with higher
frequencies to find the maximum operating frequency.
The results imply that the SOI CMOS circuit can operate
with a clock frequency of 98 MHz. Using a supply
voltage and an operating frequency of 3.3 V and 98 MHz
for SOI, and 5 V and 65 MHz for the bulk CMOS circuit,
the system power consumption is reduced 65 %.
6. Conclusions
SOI CMOS technologies are developed for improving
performance, reliability and power consumption of
integrated circuits. This paper described a layout
migration of a DSP processor chip from a 0.6 µm bulk
CMOS technology to a 0.5 µm SOI CMOS technology.
The simulations focused on verifying the correct
functionality of the migrated design and then analyzing
the impact on the system power consumption and circuit
performance. The results imply that the SOI CMOS
design consumes significantly less power than the bulk
CMOS circuit and it also can operate at 98 MHz as
opposed to 65 MHz of the original. The power
consumption is reduced by 35 - 74 %, depending on the
supply voltage and the operating frequency. To
summarize, the improvements that can be achieved with
SOI technologies in terms of performance and power
consumption are quite remarkable. The simulation results
of the test circuit demonstrated that a SOI CMOS
technology clearly is a viable alternative for realizing
low-power, high-speed digital integrated circuits.
7. Acknowledgement
This research was supported by VLSI Solution, Nokia
Mobile Phones, Vaisala and National Technology
Agency.
8.
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