page 1
Weak inversion
CCCD Workshop 2003, Lund, Oct. 2-3
WEAK INVERSION IN
ANALOG AND DIGITAL CIRCUITS
Eric A.Vittoz
CSEM, Centre Suisse d'Electronique et de Microtechnique SA
Jaquet-Droz 1, CH 2007 Neuchâtel, Switzerland
eric.vittoz@csem.ch
• Behaviour and model of MOS transistors in weak inversion [1,2,3].
• Examples of analog circuits.
• Exploratory analysis of weak inversion logic [4,5].
CSEM, E. Vittoz, 2003
page 2
Weak inversion
MOS TRANSISTOR : DEFINITIONS
n-channel
VD
B
symbols:
D
VG
G
ID
VS S
n+
n+
p local substrate
B
VS
VD
S
p-channel
D ID
VG
G
n-channel
W,L
Cox
width, length of the channel
S
gate capacitance per unit area
VS
B
UT = kT/q ( = 26 mV at 300°K)
V = local non-equilibrium voltage in channel : channel voltage
(quasi-Fermi potential of electrons)
• at source end of channel: V = VS
• at drain end of channel: V = VD
local mobile inversion charge in channel (electrons)
Qi
VT0
gate threshold voltage for V=0.
CSEM, E. Vittoz, 2003
VG
D ID
VD
page 3
Weak inversion
DRAIN CURRENT
VD
ID = β ∫
Qi
dV
C
ox
VS
• Given by:
with
β = µCox W
L
(µ=mobility)
- Qi /Cox
V G const.
VG-VT0
strong inversion, slope factor n =1.2 to 1.6
-n
pe
slo
ID
β
0
-Qi
VP -V
exponential
weak inversion: C = 2nUT exp
UT
ox
V
VS
VD
VG - VT0
Pinch-off voltage VP ≅
n
• Weak inversion already possible for VS=0 if VG<VT0 ("subthreshold")
CSEM, E. Vittoz, 2003
page 4
Weak inversion
DRAIN CURRENT IN WEAK INVERSION
(vertical axis magnified)
-Qi /Cox
-Qi /Cox
VG-VT0>0
-n
slope
-n
slope
ID/β
0
VS
VP>0
VD
V
ID/β
0
VP<0
VG-VT0<0
CSEM, E. Vittoz, 2003
VS
VD
V
page 5
Weak inversion
FORWARD AND REVERSE CURRENTS
-Qiβ/Cox
-Qiβ/Cox
Drain current ID
=
forward
current IF
ID
VS VD
-Qiβ/Cox
reverse
current IR
IF
V
VS
V
IR
VD
V
ID(VG,VS,VD) = F(VG,VS) - F(VG,VD) = IF - IR
• Drain current is the superposition of independent and symmetrical
effects of source and drain voltages.
• basic property of long-channel transistors, independent of current [6].
• Transistor saturated if IR«IF, then ID=IF.
CSEM, E. Vittoz, 2003
page 6
Weak inversion
DRAIN CURRENTEXPRESSION IN WEAK INVERSION
VP-V
• -Qi/Cox = 2nUT e UT « 2nUT
thus:
VP -VS,D
IF,R = IS e UT
2
• Definition: specific current of the transistor:
IS = 2nβUT
(10 to 300 nA for W=L)
• Introducing VP ≅ (VG-VT0)/n and ID =IF - IR, this yields:
VG-VT0
V
V
- S
- D
ID = IS e nUT (e UT - e UT )
IF
IR
CSEM, E. Vittoz, 2003
for IF and IR « IS
page 7
Weak inversion
FORWARD CHARACTERISTICS IN WEAK INVERSION
• output
VG,VS = const.
ID /IF
1
0
5% saturation
VD-VS
UT
VT0
where ID0=IS e- nUT
)
• transfer from gate
VS, VD const.
ID
log
ID0
• transfer from source
VG, VD const.
ID
log
ID0
/n
1
VG
e
p
slo
U
T
1
VD
VS
U
( e T - e UT
sl
op
e
ID = ID0
VG
e nUT
0 1 2 3 4 5 6
VD-VS
ID ~ 1-e - U
T
minimum VDSsat
VG
ID ~ e nUT
exponential, slope 1/n
CSEM, E. Vittoz, 2003
VS
UT
VS
ID~ e UT
exponential, slope 1
page 8
Weak inversion
CONTINUOUS MODELS WEAK-STRONG INVERSION
a. From charge analysis [7,8]:
VP -VS,D
=
UT
IF,R
1+4 I
S
IF,R
1+4 I
S
-1 +ln
2
-1
cannot be inverted to express IF,R(VP,VS,D)
VP -VS,D
IF,R
2
[9]
b. Interpolation formula:
=
ln
(1
+
e
)
2U
IS
T
Both converge asymptotically towards:
VP -VS,D
IF,R
IS = e U T
for VP -VS,D «UT (weak inversion)
IF,R
VP -VS,D 2
IS =  2UT 
for VP -VS,D »UT (strong inversion)
• Only 3 parameters: VT0, n (inside VP) and IS (or β) to model the current
from weak to strong inversion.
CSEM, E. Vittoz, 2003
page 9
Weak inversion
CONTINUOUS MODELS WEAK-STRONG INVERSION
IF,R
IS
b
strong
current
102
a
VP =(VG-VT0)/n
1
10-2
with:
ID = IF - IR
weak
10-4
-20
0
20
40
VP -VS,D
60
UT
voltage
• Definition: Inversion coefficient: IC = the larger of IF/IS and IR/IS
weak inversion: IC « 1
moderate inversion: IC ≅ 1
 VDSsat  2
strong inversion: IC =  2U  » 1
T
CSEM, E. Vittoz, 2003
page 10
Weak inversion
TRANCONDUCTANCE FROM WEAK TO STRONG INVERSION
• Transonductance gm from gate in saturation
weak inversion asymptote: gm=ID/(nUT)
model a
gm
nUT
ID
1.0
strong inv.asymptote: gm= 2βID/n
0.8
model b
0.6
0.4
0.2
weak
moderate strong inv.
IC=ID/IS
0
10
0.01
0.1
1
100
• gm/ID decreases with increasing inversion coefficient IC.
• gm/ID is maximum in weak inversion.
CSEM, E. Vittoz, 2003
page 11
Weak inversion
SUMMARY OF FEATURES OF WEAK INVERSION
• Large-signal DC model:
+ exponential :
⇒
+ min. VDSsat
+ min. gate voltage
+ min. gate capacitance
+ max. gm/ID :
+ gm(ID) linear
⇒
+ gm independent of β
–
µUT
– Low speed: fT≅
2πL2
VG-VT0
ID = IS e nUT
VD
VS
( e - UT - e - UT
)
+ translinear circuits and log domain filters
+ max. Ion/Ioff for given voltage swing
– intermodulation in RF front ends
+ max. intrinsic voltage gain
+ min. input noise density for given ID
+ max. bandwidth for given kT/C and ID
+ min. input offset voltage
– max. output noise current for given ID
– max. current mismatch :
∆ID ∆VT0
dominated by VT -mismatch:
=
ID nUT
CSEM, E. Vittoz, 2003
page 12
Weak inversion
EVOLUTION OF IC WITH SCALED-DOWN PROCESSES
• Scaling-down of process:
• dimension scaling by factor k
• all voltages decreased by k, except U T:
- analog circuits: VDSsat must be decreased by k, thus
VDSsat 2
IC = 
2U 
decreased by k2
T
- digital circuits: VB decreased by k, thus
VB -VT0 2

2
ICon =
decreased
by
k
2nUT 
• Weak inversion approached for constant temperature T.
µVDSsat
• Transition frequency: fT =
increased by k
2
2πL
- weak inversion with L=100nm : fT >4 GHz
CSEM, E. Vittoz, 2003
page 13
Weak inversion
LOW-VOLTAGE CASCODE IN WEAK INVERSION
[2]
VDSsat = 4 to 6UT per transistor
I
VDS2 T2
VD2
I
T3
T4
All transistors in weak inversion with:
β4
β2
= P and
=M
β3
β5
T5
T1 V
DS1 VR
substrate
• Model in weak inversion yields: VDS1 = UT ln [ P (1+ 2M)]
for P = M = 8 : VDS1=5UT,
thus VD2 = 10UT sufficient to saturate T1 and T2
CSEM, E. Vittoz, 2003
page 14
Weak inversion
EXTRACTION OF UT AND CURRENT REFERENCE [1]
V-
m
sink
T5
3 -T
4
I1
P(stable)
T
T4≡T3
I2
T2≡KT1
mirror T1-T2
or
T3
irr
T6
source
I2
slope
K
V+
T1
R
VR
• For T1 and T2 in weak inversion:
Q (unstable)
VR = RI2 =UT lnK
• Self-starting if leakage of T2 larger than that of T1.
CSEM, E. Vittoz, 2003
I1
page 15
Weak inversion
CURRENT GENERATION WITHOUT RESISTOR
• Resistor replaced by transistor T8 in conduction [10]:
• T6 =T3 =T4 =T7 and T5 = T1
T6
T3
I
• T8 and T9 in strong inversion with
β8 =Aβ9 (A»1 to have T8 in conduction) I
• T2 and T1 in weak inversion with
β2 = Kβ1
yields:
V+
T4
I
T7
I
T2
T5
T1 V R
V-
T9
T8
2
I = 2nβ8UT.Aln2K = IS8.Aln2K
• Reference current I proportional to specific current IS8
• Useful to bias transistors at inversion coef.IC independently of process.
• If mobility ~ T -2, then compensation by UT2 : I ~ IS independent of T
CSEM, E. Vittoz, 2003
page 16
Weak inversion
MOS TRANSISTOR OPERATED AS A PSEUDO-RESISTOR
[11,12,13,6]
Consequence of basic property ID = F(VS) - F(VD):
• Networks of transistors with same gate voltage are
• linear with respect to currents
• thus equiv. for currents to a resistive prototype, with Gi=1/Ri~ISi
• ground in res. prototype correspond to saturated transistors.
• example of application: current-mode linear attenuator (e.g. R-2R).
• In weak inversion:
• linearity of currents even for different gate voltages
with
VGi
Gi = 1/Ri ~ ISi exp
nUT
CSEM, E. Vittoz, 2003
page 17
Weak inversion
simple example of pseudo-R network in weak inversion:
CALCULATION OF HARMONIC MEAN
IN
ground 0
GN
IN
GN
Gk
Ik
I1
G1
Gk
GN*
Gk*
G
I
0*
0*
I
[14,13]
Ik
0*
G1*
I1
0*
GN*
Gk*
G1*
VVresistive prototype
pseudo-resistive version
(0*=pseudo-ground)
1
• Series combination of Gi : G =
harmonic mean
Σ1/Gi
Ihm
1
• Same voltage across G and Gi, thus I =
=
Σ1/Ii N
G1
• Can be used as a fuzzy AND gate.
CSEM, E. Vittoz, 2003
page 18
Weak inversion
TRANSLINEAR CIRCUITS
With bipolar transistors:
With MOS transistors in weak inversion:
Ii
+
[15]
+
∑(VGi - VSi) = ∑(VGi - VSi)
+
VBEi
+
with:
+
Ii
VGi
n -VSi = UT ln ID0i
+
+ and - directions of BEi
(any sequence)
∑VBEi
=
∑VBEi
+
Ii
with: VBEi= UT ln I
[16,17]
VGi
Ii -1
Ii
VSi
common substrate
• If + and - are alternated then: pairs of equal
VGi both sides of equation:
VGi ⇒ VGi /n for each pair,
and then
si
∏Ii
+
∏Ii
∏Isi
=
+
∏Isi
• Otherwise: separate wells connected to
=λ
sources to impose VSi = 0
• Precision degraded by VT0 mismatch
CSEM, E. Vittoz, 2003
page 19
Weak inversion
BASIC CONSIDERATIONS FOR WEAK INVERSION LOGIC
• Dynamic power consumption: Pdyn = f C ∆V VB
• Weak inversion model can be rewritten as
supply voltage
logic swing
VGS 
VDS 
ID = I0 e nUT  1 - e- nU 
T
• exponential in VGS, with maximum gm/ID, thus:
- minimum swing ∆V for given Ion/off, hence
- minimum Pdyn for given Ioff
VT0+(n-1)VS
- with: I0 = IS e
nU
T
adjustable by VS.
• Assumptions on process:
1. Threshold VT0 close to 0 (VS cannot be too negative).
2. Triple well (true twin well): separate local p and n substrates
- adjustment of I0 by VS for n- and p-channel.
CSEM, E. Vittoz, 2003
[5]
page 20
Weak inversion
STABLE STATES OF CMOS FLIP-FLOP
V+
• Simplifying assumptions: nn=np=n, I0n=I0p=I0
inverter
• Normalized voltages vk=Vk /UT
Ip
4
2
vB
Vi
ab
le
n=1.6
st
6
swing
high and low logic states
8
vH (high)
2
4
In
C
Vo
V-
le
b
a
st
a
t
me
• bistable for VB > 1.91UT
stable vL (low)
0
VB
6
8
normalized supply voltage vB
CSEM, E. Vittoz, 2003
• 95% swing for VB = 4UT
page 21
Weak inversion
STATIC CURRENT AT LOGIC STATES
• Since VL=VB-VH >0, static current Istat at each state is larger than I0
1.2
Istat
I0
n = 1.6
1.1
1.0
0.9
0.8
1
4
6
2
8
normalized supply voltage vB
• Istat <4% above I0 for vB ≥ 4 :
• Static power :
the difference can be neglected thus:
Pstat ≅ I0VB
CSEM, E. Vittoz, 2003
page 22
Weak inversion
STANDARD TRANSITIONS IN HOMOGENEOUS SYSTEM
2Td
• Chain of inverters
Vo2
VH
Vo8
Vo6
Vo4
VL
vH
4
3
vo7
vo5
n = 1.6
vB = 4
2Td/T0
vo2
1
0
vo3
vo1
von=vin+1
2
0
vo4
vo6
vo8
vL
1
3
2
normalized time t /T0
• Characteristic time : T0=CUT/I0
• Transitions become standard after a few stages
• Normalized delay time Td/T0 only depends on VB and n.
CSEM, E. Vittoz, 2003
page 23
Weak inversion
DELAY TIME FOR STANDARD TRANSITIONS
1
Td
T0
n = 1.6
• Approximation:
0.1
0.01
3
CVB
CVB
≅
Td ≅
Ion
I0eVB/nUT
or
5
6
8
4
7
9 10
normalized supply voltage vB
11
CVB -V /nU
e B
T
Td
(for calcul. of Pstat)
I0 ≅
• Td decreases approximately exponentially with increasing VB.
CSEM, E. Vittoz, 2003
page 24
Weak inversion
PROPORTION OF SHORT-CIRCUIT CHARGE
FOR STANDARD TRANSITIONS
10-2
n = 1.6
Qsc
QC
0
3
7
5
6
9
4
8
normalized supply voltage vB
10
• Short-circuit charge Qsc < 1.4% capacitor charge QC : negligible, thus:
• dynamic power
Pdyn ≅ fQCVB ≅ fCVB2
• with static power
Pstat = IstatVB ≅ I0VB
CSEM, E. Vittoz, 2003
page 25
Weak inversion
POWER-DELAY PRODUCT
• Definition: duty factor α = 2f Td ≤ 1
• proportion of time during which the gate is in transition.
CUT2 2
• Then, total power P = Pdyn + Pstat ⇒ P =
vB(α/2 + e-vB/n)
Td
normalized
power-delay product
PTd
CUT2
10
α=1
8
0.5
0.2
n =1.6
0.1
6
4
2
0
2
4
6
8
10
normalized supply voltage vB
0.05
0.03
0.01
0.003
12
• Pdyn dominates for large α ⇒ min. VB for min. PTd
• Pstat dominates for small α ⇒ increase VB to increase Ion/Ioff
CSEM, E. Vittoz, 2003
page 26
Weak inversion
POWER/FREQUENCY RATIO
• By re-using α =2f Td :
P/f = C(nUT)2 (vB/n)2(1+
normalized total power
P/f
1000
C(nUT)2
Pdyn for VB=25nUT ≅1V
100
e-3
10-2
1
10-3
Pdyn
10-4
parameter α
Pstat
10 1
1
α -v /n
e B )
2
e-3
10-2
10-4
10-3
6
8
4
14
10
12
normalized supply/slope factor vB/n
• VBopt and Pmin increase for decreasing α
• At Pmin : Pdyn»Pstat
• Increasing I0 does not allow to reduce VB significantly for Td const.
• For α > 5%, power reduction by >20 compared to Pdyn at 1V.
2
CSEM, E. Vittoz, 2003
page 27
Weak inversion
MAXIMUM SPEED
• Since Td ≅
CVB
Ion
and Ionmax ≅ ICon IS (inv. coeff* spec. current), thus:
Tdmin ≅
• Limit of weak inversion: ICon ≅1, thus
VB C
ICon IS
process
Tdmin(weak) ≅ VB C
IS
• Higher speed can only be obtained by entering moderate or strong inv.
CSEM, E. Vittoz, 2003
page 28
Weak inversion
EFFECT OF ENTERING MODERATE AND STRONG INVERSION
• More voltage swing needed
105
to obtain Ion/Ioff
• from continuous current model:
103
40
VGS swing
∆VGS
nUT
(using continuous model of ID)
60
param.
Ion/Ioff
20
10
0
10-1 1 101 102 103
"on" inv. coeff. ICon
• Degeneration of logic states:
• reduction of logic swing
• large increase of static current Istat
• loss of bistability
• more supply voltage needed.
CSEM, E. Vittoz, 2003
4
vH
3
logic
swing
2
vL
1
0
vB=4
n=1.6
0
1
2
3
Istat
IS
ICon
4
page 29
Weak inversion
NUMERICAL RESULTS
• Simple inverter replaced by 3-input NAND-gate:
• approx. equivalent to inverter with
L = 3-time that of n-ch transistor
C = 6-time that of min. inverter
(includes Cinterconnect=C/2).
parameter
C VB
process A process B unit
min. channel length
Lmin
equiv. spec. current
IS
equiv. load capac.
C
specific energy
C(nUT)2
P/f for α=1 VB=4UT
(P/f)min for α=0.01 and VBopt=6nUT
Pdyn/f at VB=1V
fmax1 for α=1 and VB=4UT
fmax2 for α=0.01 and VB=VBopt
Pmin at fmax2
CSEM, E. Vittoz, 2003
500
200
20
28
228
1.46
20
50
0.22
32.5
180
400
4
4.2
44
0.22
4
500
2.56
56.3
nm
nA
fF
aJ
aJ
fJ
fJ
MHz
MHz
nW
page 30
Weak inversion
PRACTICAL CONSIDERATIONS AND LIMITATIONS
• Low-voltage power source
• should be proportional to UT (PTAT)
• need for power-efficient adapter from higher supply voltage.
• Asymmetry
• p/n asymmetry may result in speed reduction.
• Mismatch
• dominated by threshold mismatch δVT
• may result in speed reduction proportional to δVT /VB.
• Short channel effects: should not drastically degrade the results.
• Gate leakage current : should be alleviated by very low VB.
• Adjustment of I0 orTd to required value
• control by VS with charge pump in loop [18]; n>1 needed (no SOI!)
• corresponds to threshold adjustment unavoidable at very low VB.
• System architectures and applications.
CSEM, E. Vittoz, 2003
page 31
Weak inversion
SYSTEM ARCHITECTURE AND APPLICATIONS
• Duty factor α must be maximized to reach minimum P/f,
(where f is the average transition frequency), thus
• avoid idling gates (contrary to traditional CMOS culture)
• new architectures needed:
- maximally active gates of minimum speed (max. delay time Td)
- particular problem with RAMs (short Td but sparse activity)
- how? new constraints should result in novel solutions.
• partition the system in blocks of comparable α and Td
- optimum VB and I0 for each block (separate I0 control).
• Maximum frequency much lower than for strong inversion:
• best applicable when no high local speed is required
• m-parallelize: mTd but same power if same α (m units with P/m)
- digital image processing ?
CSEM, E. Vittoz, 2003
page 32
Weak inversion
CONCLUSION
• Weak inversion permits very low supply voltage VB
2
• approached with scaled-down VB: IC ~ VB
• limit for scaled-down VB.
• Analog: • VB>10UT = 250 mV
• provides maximum gm/ID
• bipolar-like behaviour can be exploited in new schemes.
• Digital: • VB> 4UT = 100mV
• transistor not a switch but a current modulator (Ion/Ioff)
• new architectural approaches for max. duty factor α.
• ultimum (asymptotic) limit for low power*delay.
• Low speed, but keeps increasing with 1/L2 in scaled down processes.
CSEM, E. Vittoz, 2003
page 33
Weak inversion
REFERENCES
[1]
E.Vittoz and J.Fellrath, "CMOS analog integrated circuits based on weak inversion operation", IEEE J.Solid-State Circuits, vol.SC-12, pp.224-231, June 1977.
[2]
E.Vittoz, "Micropower techniques", in Design of VLSI Circuits for Telecommunications and Signal Processing, J.E.Franca and Y.P.Tsividis Editors, Prentice
Hall, 1991
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applications", Analog Integrated Circuits and Signal Processing, Vol.8, pp.83-114, 1995.
[4]
R.M Swanson and J.D.Meindl,"Ion-implanted complementary MOS transistors in low-voltage circuits", IEEE J.Solid-State Circuits, vol.SC-7, pp.146-153, April
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[5]
E. Vittoz, "Weak inversion for ultimate low-power logic", to be published in Low-Power Electronic Design, ed. C. Piguet, CRC Press LLC (2003?), Chapter 16.
[6]
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[7]
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MIT Press, Cambridge MA, 1987.
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June 1983.
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, pp.163-173.
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McGraw-Hill, 1994.
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University Press, USA, 1996.
[18] V. von Kaenel et al. "Automatic adjustment of threshold and supply voltage for minimum power consumption in CMOS digital circuits'', Proc. IEEE Symposium
on Low Power Electronics, San Diego, 1994, pp.78-79.
CSEM, E. Vittoz, 2003