Realizing Boolean logic
„
„
„
Algebraic expressions to gates
Mapping between different gates
Discrete logic gate components (used in lab 1)
Winter 2010
1
CSE370 - III - Realizing Boolean Logic
A simple example: 1-bit binary adder
Cout Cin
„
„
Inputs: A, B, Carry-in
Outputs: Sum, Carry-out
Carry out
A
B
A
B
A
B
A
B
A
B
S
S
S
S
S
A
A
0
0
0
0
1
1
1
1
Winter 2010
B
0
0
1
1
0
0
1
1
Cin Cout S
0
0
0
1
0
1
0
0
1
1
1
0
0
0
1
1
1
0
0
1
0
1
1
1
B
Cin
S
Cout
S = A’ B’ Cin + A’ B Cin’ + A B’ Cin’ + A B Cin
Cout = A’ B Cin + A B’ Cin + A B Cin’ + A B Cin
CSE370 - III - Realizing Boolean Logic
2
Apply the theorems to simplify expressions
„
The theorems of Boolean algebra can simplify expressions
‰
e.g.,
g , full adder’s carry-out
y
function
Cout
Winter 2010
=
=
=
=
=
=
=
=
=
=
=
=
A’ B Cin + A B’ Cin + A B Cin’ + A B Cin
A’ B Cin + A B’ Cin + A B Cin’ + A B Cin + A B Cin
A’ B Cin + A B Cin + A B’ Cin + A B Cin’ + A B Cin
(A’ + A) B Cin + A B’ Cin + A B Cin’ + A B Cin
(1) B Cin + A B’ Cin + A B Cin’ + A B Cin
B Cin + A B’ Cin + A B Cin’ + A B Cin + A B Cin
B Cin + A B’ Cin + A B Cin + A B Cin’ + A B Cin
B Cin + A (B’ + B) Cin + A B Cin’ + A B Cin
B Cin + A (1) Cin + A B Cin’ + A B Cin
B Cin + A Cin + A B (Cin’ + Cin)
B Cin + A Cin + A B (1)
adding extra terms
B Cin + A Cin + A B
creates new factoring
opportunities
CSE370 - III - Realizing Boolean Logic
3
A simple example: 1-bit binary adder
Cout Cin
„
„
Inputs: A, B, Carry-in
Outputs: Sum, Carry-out
Carry out
A
B
A
B
A
B
A
B
A
B
S
S
S
S
S
A
A
0
0
0
0
1
1
1
1
Winter 2010
B
0
0
1
1
0
0
1
1
Cin Cout S
0
0
0
1
0
1
0
0
1
1
1
0
0
0
1
1
1
0
0
1
0
1
1
1
B
Cin
S
Cout
Cout = B Cin + A Cin + A B
S = A’ B’ Cin + A’ B Cin’ + A B’ Cin’ + A B Cin
= A’ (B’ Cin + B Cin’ ) + A (B’ Cin’ + B Cin )
= A’ Z + A Z’
= A xor Z = A xor (B xor Cin)
CSE370 - III - Realizing Boolean Logic
4
From Boolean expressions to logic gates
„
NOT X’
X
„
AND X • Y
„
OR
X+Y
Winter 2010
XY
~X
X
X/
X∧Y
X
Y
X∨Y
X
Y
X
0
1
Y
CSE370 - III - Realizing Boolean Logic
Y
1
0
Z
X
0
0
1
1
Y
0
1
0
1
Z
0
0
0
1
Z
X
0
0
1
1
Y
0
1
0
1
Z
0
1
1
1
5
From Boolean expressions to logic gates (cont’d)
„
NAND
X
Y
„
NOR
X
Y
„
„
XOR
X⊕Y
XNOR
X=Y
Winter 2010
X
Y
X
Y
Z
X
0
0
1
1
Y
0
1
0
1
Z
1
1
1
0
Z
X
0
0
1
1
Y
0
1
0
1
Z
1
0
0
0
Z
X
0
0
1
1
Y
0
1
0
1
Z
0
1
1
0
X xor Y = X Y’ + X’ Y
X or Y but not both
("inequality", "difference")
Z
X
0
0
1
1
Y
0
1
0
1
Z
1
0
0
1
X xnor Y = X Y + X’ Y’
X and Y are the same
("equality", "coincidence")
CSE370 - III - Realizing Boolean Logic
6
Full adder: Carry-out
Before Boolean minimization
Cout = A'BCin + AB'Cin
+ ABCin'
C + ABCin
C
After Boolean minimization
Cout = BCin + ACin + AB
notA
B
Cin
A
B
A
notB
Cin
Cout
A
B
notCin
A
Cin
Cout
B
Cin
A
B
Cin
Winter 2010
7
CSE370 - III - Realizing Boolean Logic
Full adder: Sum
Before Boolean minimization
Sum = A'B'Cin + A'BCin'
+ AB'Cin' + ABCin
After Boolean minimization
Sum = (A⊕B) ⊕ Cin
notA
notB
Cin
notA
B
notCin
Sum
A
notB
notCin
A
B
Cin
Sum
A
B
Cin
Winter 2010
CSE370 - III - Realizing Boolean Logic
8
Preview: A 2-bit ripple-carry adder
A
B
A1
B1
A2
B2
1-Bit Adder
A
B
0
A
Cin
Cin
Cin Cout
Cin Cout
Sum1
Sum2
Cout
B
Cin
Cout
A
B
Sum
Cin
Sum
Winter 2010
9
CSE370 - III - Realizing Boolean Logic
Mapping truth tables to logic gates
„
A
0
0
0
0
1
1
1
1
Given a truth table:
1.
2
2.
3.
4.
Write the Boolean expression
Mi i i th
Minimize
the B
Boolean
l
expression
i
Draw as gates
Map to available gates
1
2
B
0
0
1
1
0
0
1
1
C
0
1
0
1
0
1
0
1
F
0
0
1
1
0
1
0
1
F = A’BC’+A’BC+AB’C+ABC
= A’B(C’+C)+AC(B’+B)
= A’B+AC
3
notA
B
4
F
A
C
Winter 2010
notA
B
F
A
C
CSE370 - III - Realizing Boolean Logic
10
Conversion between gate types
Example: map AND/OR network to NOR-only network
„
A
B
Z
C
D
A
\A
NOR
\B
B
NOR
Z
C
D
NOR
\C
NOR
\D
Z
NOR
conserve
"bubbles"
conserve
"bubbles"
Winter 2010
11
CSE370 - III - Realizing Boolean Logic
Conversion between gate types (cont’d)
„
Example: verify equivalence of two forms
\A
A
\B
B
NOR
Z
C
NOR
\C
D
\D
Z
NOR
Z = { [ (A’ + B’)’ + (C’ + D’)’ ]’ }’
Winter 2010
={
(A’ + B’) • (C’ + D’)
=
(A’ + B’)’ + (C’ + D’)’
=
(A • B) + (C • D)
CSE370 - III - Realizing Boolean Logic
}’
12
Activity: convert to NAND gates
A
B
C
F
D
A
A
B
C
B
C
F
D
F
D
A
B
C
F
D
Winter 2010
CSE370 - III - Realizing Boolean Logic
13
Example: tally circuit (outputs # of 1s in inputs)
X1
X2
X3
T2
T1
0
0
0
0
0
0
0
1
0
1
0
1
0
0
1
0
1
1
1
0
1
0
0
0
1
1
0
1
1
0
1
1
0
1
0
1
1
1
1
1
T1 = X1’ X2’ X3 + X1’ X2 X3’
+ X1 X2’ X3’ + X1 X2 X3
= (X1’ X2’ + X1 X2) X3
+ (X1’ X2 + X1 X2’) X3’
= (X1 xor X2)’ X3
+ (X1 xor X2) X3’
= (X1 xor X2) xor X3
T2 = X1’ X2 X3 + X1 X2’ X3
+ X1 X2 X3’ + X1 X2 X3
= X1’ (X2 X3) + X1 (X2 + X3)
Winter 2010
CSE370 - III - Realizing Boolean Logic
14
From Boolean expressions to logic gates
„
More than one way to map expressions to gates
‰
e.g., Z = A’ • B’ • (C + D) = (A’ • (B’ • (C + D)))
use of 3-input gate
Winter 2010
CSE370 - III - Realizing Boolean Logic
15
Waveform view of logic functions
„
Just a sideways truth table
‰
‰
but note how edges
g don’t line up
p exactly
y
it takes time for a gate to switch its output!
time
change in Y takes time to "propagate" through gates
Winter 2010
CSE370 - III - Realizing Boolean Logic
16
Choosing different realizations of a function
A
0
0
0
0
1
1
1
1
B
0
0
1
1
0
0
1
1
C
0
1
0
1
0
1
0
1
Z
0
1
0
1
0
1
1
0
two-level realization
(we don’t count NOT gates)
multi-level realization
(gates with fewer inputs)
XOR gate (easier to draw
but costlier to build)
Winter 2010
CSE370 - III - Realizing Boolean Logic
17
Are all realizations equivalent?
„
Under the same input stimuli, the three alternative
p
have almost the same waveform behavior
implementations
‰
‰
‰
„
delays are different
glitches (hazards) may arise – these could be bad, it depends
variations due to differences in number of gate levels and structure
The three implementations are functionally equivalent
Winter 2010
CSE370 - III - Realizing Boolean Logic
18
Which realization is best?
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Reduce number of inputs
‰
literal: input
p variable ((complemented
p
or not))
„
„
‰
fewer literals means less transistors
„
‰
gates are smaller and thus also faster
fan ins (# of gate inputs) are limited in some technologies
fan-ins
„
„
smaller circuits
fewer inputs implies faster gates
„
‰
can approximate cost of logic gate as 2 transistors per literal
why not count inverters?
the programmable logic we’ll be using later in the quarter
Reduce number of gates
‰
fewer gates (and the packages they come in) means smaller circuits
„
directly influences manufacturing costs
Winter 2010
CSE370 - III - Realizing Boolean Logic
19
Which realization is best? (cont’d)
„
Reduce number of levels of gates
‰
‰
fewer level of g
gates implies
p
reduced signal
g
p
propagation
p g
delays
y
minimum delay configuration typically requires more gates
„
wider, less deep circuits
„
Hazards/glitches
„
How do we explore tradeoffs between increased circuit delay
and size?
‰
‰
‰
‰
one without hazards may be preferable/necessary
automated tools to generate different solutions
logic minimization: reduce number of gates and complexity
logic optimization: reduction while trading off against delay
Winter 2010
CSE370 - III - Realizing Boolean Logic
20
Random logic gates
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„
Transistors quickly integrated into logic gates (1960s)
Catalog of common gates (1970s)
‰
‰
‰
Texas Instruments Logic Data Book – the yellow “bible”
all common packages listed and characterized (delays, power)
typical packages:
„
„
„
in 14-pin IC: 6-inverters, 4 NAND gates, 4 XOR gates
Today, very few of these parts are still in use
However, parts libraries exist for chip design
g
‰
‰
‰
designers reuse already characterized logic gates on chips
same reasons as before
difference is that the parts don’t exist in physical inventory –
created as needed
Autumn 2006
CSE370 - V - Implementation Technologies
21
Some logic gate components
Winter 2010
Quad 2-input NANDs – ‘00
Quad 2-input NORs – ‘02
6 inverters (NOTs) – ‘04
3 3-input NANDs – ‘10
CSE370 - III - Realizing Boolean Logic
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