Logic Circuits II
ECE 2411
Thursday 4:45pm-7:20pm
Lecture 7
Lecture 7
• Topics:
– Chapter 6
Registers
• A register is a group of flip flops
– All share a common clock
– Each flip flop is capable of storing one bit of
information
• Thus, a n-bit register consists of n flip flops and is
capable of storing n bits of binary information
• A register may also contain combinational logic
that perform specific data-processing tasks
Four Bit Register
module four_bit_reg(I,A,Clock, Clear_b);
input [3:0] I;
input
Clock;
input
Clear_b;
output [3:0] A;
reg [3:0] A;
always @(posedge Clock, negedge Clear_b) begin
if(!Clear_b)
A <= 4'h0;
else
A <= I;
End
endmodule // four_bit_reg
Four Bit Register
module four_bit_reg(I,A,Clock, Clear_b);
reg Clk = 0;
reg Clr_b = 1;
reg [3:0] I = 4'h0;
Forgot to declare A bus!
Simulation still runs (with warning)
// Free running clock
always
#50 Clk = !Clk;
// Instantiate four_bit_reg
four_bit_reg four_bit_reg(.Clock(Clk), .Clear_b(Clr_b), .I(I), .A(A));
input [3:0] I;
input
Clock;
input
Clear_b;
output [3:0] A;
reg [3:0]
`timescale 1ns/10ps
module four_bit_reg_tb();
// Test Stimulus
initial begin
#10 Clr_b = 0;
repeat(2) @(posedge Clk);
Clr_b = 1;
repeat(2) @(posedge Clk);
I = 4'h1;
A;
repeat(2) @(posedge Clk);
I = 4'h2;
always @(posedge Clock, negedge Clear_b) begin
if(!Clear_b)
A <= 4'h0;
else
A <= I;
End
endmodule // four_bit_reg
repeat(2) @(posedge Clk);
I = 4'h4;
repeat(2) @(posedge Clk);
I = 4'hF;
#10 Clr_b = 0;
repeat(2) @(posedge Clk);
Clr_b = 1;
repeat(2) @(posedge Clk);
$stop;
end
endmodule
Note: “A” still shown at Testbench level but single wire, not bus
Four Bit Register
module four_bit_reg(I,A,Clock, Clear_b);
input [3:0] I;
input
Clock;
input
Clear_b;
output [3:0] A;
reg [3:0]
A;
always @(posedge Clock, negedge Clear_b) begin
if(!Clear_b)
A <= 4'h0;
else
A <= I;
End
endmodule // four_bit_reg
`timescale 1ns/10ps
module four_bit_reg_tb();
reg Clk = 0;
reg Clr_b = 1;
reg [3:0] I = 4'h0;
wire [3:0] A;
Fixed!
// Free running clock
always
#50 Clk = !Clk;
// Instantiate four_bit_reg
four_bit_reg four_bit_reg(.Clock(Clk), .Clear_b(Clr_b), .I(I), .A(A));
// Test Stimulus
initial begin
#10 Clr_b = 0;
repeat(2) @(posedge Clk);
Clr_b = 1;
repeat(2) @(posedge Clk);
I = 4'h1;
repeat(2) @(posedge Clk);
I = 4'h2;
repeat(2) @(posedge Clk);
I = 4'h4;
repeat(2) @(posedge Clk);
I = 4'hF;
#10 Clr_b = 0;
repeat(2) @(posedge Clk);
Clr_b = 1;
repeat(2) @(posedge Clk);
$stop;
end
endmodule
Register with Parallel Load
module four_bit_reg_para(I,A, Load, Clock, Clear_b);
input [3:0] I;
input
Clock;
input
Clear_b;
input
Load;
output [3:0] A;
reg [3:0] A;
wire [3:0] D;
// Load Combiantional Logic
assign D[3:0] = ((A[3:0] & {4{!Load}})|(I[3:0] & {4{Load}}));
always @(posedge Clock, negedge Clear_b) begin
if(!Clear_b)
A <= 4'h0;
else
A <= D;
end
endmodule
Register with Parallel Load
module four_bit_reg_para_no_comb(I,A, Load, Clock, Clear_b);
input [3:0] I;
input
Clock;
input
Clear_b;
input
Load;
output [3:0] A;
reg [3:0] A;
always @(posedge Clock, negedge Clear_b) begin
if(!Clear_b)
A <= 4'h0;
else
if(Load)
A <= I;
else
A <= A;
end
endmodule
Register with Parallel Load
Shift Register
module four_bit_shift_reg(input CLK, SI, output SO);
reg [3:0] SO_reg;
assign SO = SO_reg[3];
always @(posedge CLK)
SO_reg <= {SO_reg[2:0], SI};
endmodule // four_bit_shift_reg
Serial Shift Register with Shift Control
Serial Shift Register with Shift Control
module four_bit_shift_reg_cntrl(input CLK, SI, SC, output SO);
reg [3:0] SO_reg = 4'h0;
assign SO = SO_reg[3];
always @(posedge CLK)
if(SC)
SO_reg <= {SO_reg[2:0], SI};
else
SO_reg <= SO_reg;
endmodule
Serial Adder
Binary Ripple Counter
Don’t use these as the FFs don’t have a common clock
module ripple_counter(Count, A);
input Count;
output reg [3:0] A = 4'h0;
always @(negedge Count)
A[0] <= !A[0];
always @(negedge A[0])
A[1] <= !A[1];
always @(negedge A[1])
A[2] <= !A[2];
always @(negedge A[2])
A[3] <= !A[3];
endmodule
Bad: New clock domains
D FF Binary Counter
module binary_counter(Clk, CntEn, Q);
input Clk, CntEn;
output reg [3:0] Q = 4'h0;
always @(posedge Clk)
if(CntEn)
Q <= Q +1;
else
Q <= Q;
endmodule // binary_counter
`timescale 1ns/10ps
module binary_counter_tb();
reg Clk = 0;
reg CntEn = 0;
wire [3:0] Q;
always
#50 Clk = ~Clk;
binary_counter binary_counter(.Clk(Clk), .CntEn(CntEn),
.Q(Q));
initial begin
repeat(10) @(posedge Clk);
CntEn = 1;
repeat(20) @(posedge Clk);
CntEn = 0;
repeat(5) @(posedge Clk);
$stop;
end
endmodule // binary_counter_tb
Up/Down Binary Counter
module up_dwn_binary_counter(Clk, CntEn, upDwn, Q);
input Clk, CntEn, upDwn;
output reg [3:0] Q = 4'h0;
always @(posedge Clk)
if(CntEn)
if(upDwn)
Q <= Q + 1;
else
Q <= Q - 1;
else
Q <= Q;
endmodule
Lab 2 – Due 10/16/2014
•
Code (Verilog) and simulate a 8 bit up/down binary counter that doesn’t roll
over, i.e. counts up to 8’hff and stops, counts down to 8’h00 and stops, and
has 8 bit user parallel input for initial value.
–
–
Inputs:
• Clock,
• upDwn (0 = count down, 1 = count up)
• Count Enable (0 = stop counting, 1 = count)
• Load (one clock wide pulse to load initial value
• Initial Value (User defined initial value)
• Asynchronous reset (resets counter to 8’h00)
Output:
• 8 bit count value
• Deliverables:
– Verilog code for counter and test bench
– Waves showing operation
Example of a 4 bit counter
stopping
at min and max values
Lab 3 – Due 10/16/2014
•
Code (Verilog) and simulate the four bit Johnson Counter shown in figure
6.18a. Add feature outlined on page 283 that fixes the issue of the counter
going into undesired states.
–
–
Inputs:
• Clock,
• Asynchronous reset (resets counter to 4’h0)
Output:
• Sequence number as indicated by AND gate outputs given in column 3 of fig. 6.18b
• Deliverables:
– Verilog code for counter and test bench
– Waves showing operation
– Verify that the fix on page 283 does indeed work by either
• Parallel load of registers with bad states
• Verilog force/release statements in your test bench
– Disable the page 283 fix and show that the counter “goes off in the weeds”.