P.1
Analog and Mixed-Signal Circuits
Testing and Design for Testability
張順志 (Soon-Jyh Chang)
Department of Electrical Engineering
National Cheng Kung University
Email: soon@mail.ncku.edu.tw
Outline
NCKU/EE
„
Overview of VLSI testing
„
Mixed-Signal Circuits Testing
„
Mixed-Signal Circuits Design-for-Testability
„
Summary
P.2
S.J.Chang
P.3
What is Testing?
NCKU/EE
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S.J.Chang
VLSI realization process
Customer’s need (specifications)
1. Design House
2. Foundry
3. Foundry or Testing House
4. Packaging House
5. Testing House
IC Design
Wafer Manufacturing
Wafer Testing
Packaging
Final Testing
Shipping
„
Testing: The process of determining whether a system is
functioning correctly or defective.
P.4
Why Testing?
NCKU/EE
„
S.J.Chang
The IC fabrication process is not perfect!
„
Catastrophic defects
Underetched Via
„
Blocked Etch
Imperfect photographic printing & doping process
Focused ion beam (FIB)
micrograph of metal traces
on an IC
Why Study Testing?
P.5
(1/2)
NCKU/EE
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S.J.Chang
Economics!
„
„
Reduce test cost (enhance profit)
„ 1 second of test time equals 3 to 5 cents.
„ 5 second test program @ 4 cents per second times one
million devices per quarter costs USD 800,000 per year.
“Rule of Ten”:
Defects detected during
Wafer
Packaged chip
Board
System
Field
Cost
0.01 – 0.1
0.1 – 1
1 – 10
10 – 100
100 – 1000
Why Study Testing?
P.6
(2/2)
NCKU/EE
„
S.J.Chang
Economics!
„
Shorten time-to-market (time-to-volume)
„ Profits depends on having product available at the right time.
„ Testing provides the means of maximizing product yields in
the shortest possible time.
100%
Revenue
Yield
Testing
0%
Time
Principle of Testing
NCKU/EE
P.7
S.J.Chang
Input Patterns
---11
---00
----...
-------10
Stored
Correct
Response
Output Response
Digital
Circuit
10--00------...
----01---
Comparator
Test Result
„
The quality of the tested circuit will depend upon the
thoroughness of the test vector
„
Exhaustive testing for a 3-input AND gate takes 8 test
patterns
Why Testing is Difficult?
NCKU/EE
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S.J.Chang
Consider a 32-bit adder
„
„
„
„
P.8
65 inputs, 33 outputs:
265 = 36,893,488,147,419,103,232 patterns
Using 10 GHz ATE, would take ≈ 116.98 years
Problems to think
„
„
„
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A 32 bit adder (combinational)
A 64 bit counter (sequential)
A 1Gb memory
A 108-transistor CPU
„
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Combinational + sequential + memory
A mixed-signal processor
„
Combinational + sequential + memory + analog
So, Testing Cost Will Soon Be A Big Problem
NCKU/EE
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P.9
S.J.Chang
Testing cost vs. manufacturing cost
Source: ITRS Roadmap, 2002
Outline
NCKU/EE
„
Overview of VLSI testing
„
Mixed-Signal Circuits Testing
„
Mixed-Signal Circuits Design-for-Testability
„
Summary
P.10
S.J.Chang
P.11
Analog/Mixed-Signal ICs
NCKU/EE
S.J.Chang
Transistors/Chip
106
System-on-chip
105
Mixed
signal ASIC
104
103
102
Dedicated
interface
components
MSI off-the-shelf
components
101
Low
Medium
High
Modems
LAN Transceivers
Consumer audio
Video interfaces
Codecs
Servo
…
Volume
P.12
Trend: Mixed-Signal System-on-Chip
NCKU/EE
S.J.Chang
Digital I/Os
Ref
Analog
Inputs
Amp
ADC
Power
Management
DSP
Clock & Timers
„
Ref
DAC
Amp
Analog
Outputs
Interface
Mixed-signal ICs surpassed the global microprocessor
market last year (2005) [SIA]
„
The worldwide mixed-signal IC market is expected to reach
$42.7 billion by 2007, representing a large 24% increase over
the $34.4 billion mixed-signal IC market in 2004
P.13
Features of Mixed-Signal ICs Development
NCKU/EE
S.J.Chang
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Analog circuit contains fewer devices, whereas the digital
part contains millions of devices
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High expenses both time and money on designing and
testing of analog subcircuits
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Absence of tools for analog and mixed-signal test development
Testing in Digital Domain
NCKU/EE
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P.14
S.J.Chang
Fact: Most of complicate digital ICs can be test in few
seconds today.
„
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Structural based tests
„ Test faults rather than function
There are fruitful research results to alleviate the difficulties
„ Fault simulation
„ Automatic test pattern generation (ATPG),
„ Design for Testability (DfT),
„ Built-In Self-Test (BIST),
„ …
Analog Circuits Testing Difficulties
NCKU/EE
P.15
S.J.Chang
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Continuous time and amplitude signal
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Analog circuits are nonlinear in nature
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Complicated cause-effect relationship
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Absence of suitable fault model
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Mainly functional (specifications) based test.
Product Costs for a Mixed-Signal ICs
NCKU/EE
P.16
S.J.Chang
[ITC’2002]
„
For complex MS ICs, testing is becoming one of the major
cost factors in the over-all IC product costs.
„
With the introduction of DfT techniques digital test costs
came down.
„
Analog test costs will dominate the product costs.
P.17
A Beirf Summary of Mixed-Signal ICs Testing
NCKU/EE
S.J.Chang
Expensive test equipment
„ Long test time
„ Long test developing time
„
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Test Costs ↑↑↑
To reduce test cost, the recently strategies are
„
„
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Reduce test items
Employ low cost tester
Computer aided test development
Various Circuit Types and Specifications
P.18
(1/2)
NCKU/EE
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S.J.Chang
Analog and mixed-signal circuit types
„
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Amplifier, comparator, filter, signal/reference generator,
sensor/meter, transceiver (driver, transmitter, receiver, …),
converter (ADC, DAC, VFC, …), …
Analog and mixed-signal circuit specifications
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DC specifications: gain, offset, drift, INL, DNL, …
AC specifications: unit-gain frequency, bandwidth, CMRR, …
Transient specifications: rise/fall/settling time, glitch, jitter, …
Others: operation range, I/O impendence, noise figure, power
dissipation, temperature sensitivity, …
Various Circuit Types and Specifications
NCKU/EE
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P.19
(2/2)
S.J.Chang
Example: ADxxxx datasheet
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Analog front end for cable: 2x8bits ADCs, 1x10bits ADC,
1x12bits ADC, 1x12bits DAC (224 MHz, BW=65MHz)
Datasheet gives 140 analog parameters
Reduce Test Items
NCKU/EE
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P.20
S.J.Chang
Characteristic observation inference test design approach
[TCAD, 1999]
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Structural fault based specification reduction methodology
[JETTA, 2002]
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Alternate test methodology [TCAD, 2002]
Specifications of initial N devices are
measured using conventional test set-up
Measurement data is taken for same set
of N devices on alternate test set-up
Model/Mapping Functions are built from measurements
to specifications using statistical analysis
Subsequent devices are measured on the alternate test
set-up and models are used to estimate the specifications
Test by Low Cost Tester
NCKU/EE
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One of the promising approaches to reduce test cost.
„
In order to move to a low cost tester,
P.21
S.J.Chang
Design for Testability (DfT) and/or Built-In Self-Test (BIST)
techniques, and their corresponding control mechanism
are necessary.
Outline
NCKU/EE
„
Overview of VLSI testing
„
Mixed-Signal Circuits Testing
„
Mixed-Signal Circuits Design-for-Testability
„
Summary
P.22
S.J.Chang
Design for Testability (DfT)
Built-In Self-Test (BIST)
NCKU/EE
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Many DfT techniques largely reduce the test cost for
digital circuits.
„
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Scan design, memory BIST, …
Today, many CAD tools support DfT features.
Recently, many researchers toward to alleviate the
difficulties of analog testing by using DfT techniques.
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Isolation (bypassing)
Loop around
SW-OPAMP
Oscillation test strategy
P.23
S.J.Chang
Isolation (Bypassing)
NCKU/EE
P.24
S.J.Chang
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Normal
„
Test functional block 1
„
Test functional block 2
Analog
function
Analog
function
sel1
sel2
„
Most used currently
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Switch (multiplexer) should be designed carefully
P.25
Loop Around
NCKU/EE
S.J.Chang
voice
Modulator
RF
sel2
voice
Demodulator
Downconverter
RF
sel1
„
Example
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CODEC, RF/IF Test
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Switch (multiplexer) should be designed carefully
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Fault masking
SW-OPAMP
P.26
(1/2)
NCKU/EE
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S.J.Chang
Switched-Opamp
„
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C= 1: regular opamp
C= 0: power-off opamp
VDD
M5
C
M10
M7
M8
V-
M1
M2
V+
Cc
Vo
M6
5uA
M3
M4
VSS
M9
C
SW-OPAMP
P.27
(2/2)
NCKU/EE
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S.J.Chang
Test strategy
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C=1: normal operation test
C=0: reconfiguration test
Example
R5
C1 C2 C3 =111
C1 C2 C3 =100
C1 C2 C3 =000
R2
C1
R1
C2
R3
R4
HPO
C1
R7
R6
LPO
BPO
C2
C3
Oscillation Test Strategy
P.28
(1/2)
NCKU/EE
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Partitioning CUT into functional building blocks
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Converting each building block to an oscillator
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Defects cause deviations in oscillation frequency
S.J.Chang
Oscillation Test Strategy
P.29
(2/2)
NCKU/EE
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S.J.Chang
Example
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Continuous-time
state-variable filter
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Excellent for hard and large deviation faults
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Challenges
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No universal rules to transfer DUT into oscillator
No trivial relationship between the oscillation frequency and the
specification under test
P.30
Practice
NCKU/EE
S.J.Chang
„
Analog circuit designers design perfect circuits.
„
No one dare to change it.
vs
Sourced from:
Prof. CC Su
So, What Should We Do …
NCKU/EE
„
S.J.Chang
Incorporate DfT features at a early design stage
„ Analog design engineer(s) + test engineer(s)
„
„
P.31
Analog design engineer(s) who know(s) the knowledge
of DfT issues
Develop easy-to-use test platform (including tools)
Outline
NCKU/EE
„
Overview of VLSI testing
„
Mixed-Signal Circuits Testing
„
Mixed-Signal Circuits Design-for-Testability
„
Summary
P.32
S.J.Chang
Summary
NCKU/EE
S.J.Chang
„
AMS testing requires specialized approaches and
experienced engineers because of the large varieties of
signals, functions and circuits.
„
Mystification
Testing is an expensive process that drives up the cost of ICs
without adding any new value to the final product.
„ Testing cannot change the quality of the individual ICs; It can
only measure quality if it already exists.
⇒ Testing is not necessary!
„
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P.33
Demystification
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Guarantee IC quality and reliability
Enhance IC yield
„ Infrastructure IP: design-for-yield
Thank You
NCKU/EE
P.34
S.J.Chang
Thank You for Your Patience!