Resonant Transition Topologies for Push-Pull and
Half-Bridge DC-DC Converters
A Thesis
Submitted for the Degree of
Master of Science
in the Faculty of Engineering
by
B. SWAMINATHAN
Department of Electrical Engineering
Indian Institute of Science
Bangalore - 560 012, INDIA
MAY 2004
Acknowledgements
I thank Prof. V. Ramanarayanan and Prof. V. T. Ranganathan, for accepting me as a
student in the Power electronics group. This is a lifetime opportunity for me. Both professors
have been an inspiration for me and will continue to be so in future.
I thank my guide Prof. V. Ramanarayanan for providing me a research topic, which
has practical relevance. I wish to acknowledge the guidance and the research facilities made
by him. I feel highly fortunate to have worked under him.
I consider myself fortunate to have studied in Indian Institute of Science. This place
provided me an opportunity to learn a lot more than power electronics. I also gratefully
acknowledge the Government of India for the financial assistance provided to me.
I am grateful to Dr. G. Narayanan, for his timely advice and motivation during my
stay.
I thank my parents for their exhaustive financial support and constant encouragement
throughout my academic career. It is because of their well wishes and encouragement I was
able to cross several hurdles, which I faced throughout my academic career.
I thank Mr. B. G. Satyanarayana, Mrs. Renuka Khembavi and Mrs. Sandhya of BEL
for providing the various components for my project.
I thank Mrs. Silvi Jose of stores for providing me the hardware accessories for my
project. I like to thank Mr. Channegowda and his colleagues of office for their support during
my stay.
I like to thank Dr. N. Viswanathan for his useful advice during my stay. I also like to
thank Dr. A. R. Beig for the help that he rendered during my research work. I like to thank
Milind for his help while building my hardware setup. Finally I thank my friends Vishal,
Amit, Shashidhar, Hariharan, Rajaganesh, Ashok kumar, Banerjee, Surajit Das, Kamalesh,
Venugopal, Lakshmi, Srinath.
i
Abstract
Switched mode power supplies (SMPS) are being extensively used in most power
conversion processes. The analysis, design and modeling processes of hard-switched
converters are mature, where the switching frequency was limited to a few 10’s of kHz. The
present direction of evolution in SMPS is towards higher efficiency and higher power
density. These twin objectives demand high switching frequency and low overall losses. Soft
switching results in practically zero switching losses and extends the switching frequency to
100’s of kHz and beyond.
This thesis presents novel variants of push-pull and half-bridge DC-DC converters
with soft switching properties. The proposed topology uses two additional switches and two
diodes. The additional switches introduce freewheeling intervals in the circuit and enable
loss-less switching. Switch stress, control and small signal model are similar to hard-switched
PWM converter. Synchronous rectifiers are used in the ZVS push-pull converter to achieve
high efficiency. It is interesting to see that the drives for the synchronous rectifier device are
practically the same as the additional switches.
The contributions made in this thesis are
1) Idealized analysis and design methodology for the proposed converters.
2) Validation of the design through circuit simulation as well as prototypes - a 300kHz,
200W push-pull converter and a 300kHz, 640W half-bridge converter.
3) Closed loop control design for desired bandwidth and accuracy. Verification of loop
gain through network analyzer instrumental for the same. The loop gain bandwidth
achieved is about 30kHz for the push-pull converter and 20kHz for half-bridge
converter.
An appendix has been devoted to explain the use of network analyzer.
Characterization of coil, transformer and capacitor are explained in detail. Measurement
techniques for measuring the small signal parameters of power supply are also explained in
the appendix.
ii
Contents
Acknowledgements
i
Abstract
ii
Contents
iii
CHAPTER 1 Introduction
1
CHAPTER 2 Soft Switching Topologies: An Overview
2.1 Introduction
4
2.2 Hard Switching
4
2.3 Soft Switching
6
2.4 Soft Switching Topologies
7
2.4.1 Resonant Converters
7
2.4.2 Resonant Transition Converters
10
2.4.3 Active Clamp Converters
12
2.4.4 ZVS Push-Pull converter
13
2.5 Issues Associated in Achieving ZVS in Controlled Push-Pull and HalfBridge Converter
14
2.6 Conclusion
16
CHAPTER 3 Analysis and Design of ZVS Push-Pull Converter
3.1 Introduction
17
3.2 Proposed Circuit and Operation
17
3.3 Designing for ZVS
30
3.3.1 Parameters Affecting ZVS
30
3.3.2 Design Procedure
34
3.3.3 ZVS limit
36
3.4 Design and Development of a 300kHz / 200W Push-Pull converter
3.4.1 Design Procedure
3.5 Simulation and Experimental Results
36
37
42
3.5.1 Simulation Results
42
3.5.2 Experimental Results
44
3.6 Dynamic analysis of ZVS Push-Pull Converter
iii
52
3.6.1 Design of Closed Loop Control
53
3.7 Line and Load regulation
56
3.8 Losses in ZVS Push-Pull Converter
57
3.9 Conclusion
59
CHAPTER 4 Analysis and Design of ZVS Push-Pull Converter
4.1 Introduction
60
4.2 Proposed Circuit and Operation
60
4.3 Designing for ZVS
74
4.3.1 Parameters affecting ZVS
74
4.3.2 Design Procedure
74
4.3.3 Specifications of a 300kHZ /640W Half-Bridge Converter
75
4.4 Simulation and Experimental Results
76
4.4.1 Simulation Results
76
4.4.2 Experimental Results
76
4.5 Dynamic Analysis of ZVS Half-Bridge converter
84
4.6 Losses in the ZVS Half-Bridge Converter
84
4.7 Conclusion
86
CHAPTER 5 Conclusion
87
References
89
Appendix
91
iv
CHAPTER 1
INTRODUCTION
Switched mode power supplies (SMPS) are being extensively used in most power
conversion processes [1]. They are efficient and compact. The analysis, modeling and design
processes have all matured in the past 3 decades. Most of these developments centered
around hard-switching converters, where the switching frequency was limited to a few 10’s
of kHz [2]. The present direction of evolution in SMPS is towards higher efficiency and
higher power density. This twin objective demands higher switching frequency and low
overall losses. Soft switching results in practically zero switching losses and extends the
switching frequency to 100’s of kHz and beyond [3]. The soft switching converters belong to
several families namely resonant load [4], [11], resonant switch [5], [9], [12] resonant
transition [7], [13] and more recently active clamped circuit topologies [6], [10]. The resonant
load converters depend on the characteristics of the load to achieve soft switching. The
resonant switch converters have additional elements in the switch enabling loss-less
switching. Resonant transition converters employ the parasitics of the circuit to achieve lossless switching. Fig. 1.1 shows the classification of the SMPS.
SMPS
Hard Switching
Re sonant Load
Soft Switching
Re sonant switch
Re sonant Transition
ActiveClamp
Fig. 1.1 Classification of SMPS
This thesis presents novel variants of push-pull and half-bridge converters with soft
switching properties.
1
Push-pull converter and half-bridge converter are popular power converters at
medium power levels. Push-pull and half-bridge converters are characterized by circuit
intervals when both power transfer switches are off. Such circuits exhibit hard switching and
not readily adaptable to soft switching. The proposed topology uses two additional switches
and two diodes. The additional switches introduce freewheeling intervals in the circuit and
thus enable loss-less switching. The new circuit features,
•
Loss-less switching transition for all the switches employed.
•
Switch stress similar to hard switched PWM converter.
•
Control and small signal behavior similar to hard switched PWM converter.
This thesis presents the new topology suitable for push-pull and half-bridge
converters. The operation and idealized analysis are presented. The non-idealities and their
effect on the operation are highlighted. The design methodology to achieve ZVS operation in
the range of interest is given. Prototype converters are fabricated and evaluated thus
validating the design methodology. This thesis is organized as follows.
Chapter 2 of this thesis gives an introduction to high frequency switching. Further it
gives an overview of the existing soft switching families. Some of the soft switching
topologies for push-pull converter are reviewed. Advantages and disadvantages of each
topology are discussed.
Chapter 3 discusses the complete steady state analysis of the proposed push-pull
converter. Operation of the converter is analyzed interval by interval. Design methodology
and parameters affecting the ZVS are discussed. Simulation results and experimental
verifications are presented in this chapter. Dynamic characteristics are explored through
approximate analysis. These are verified on the prototypes.
Chapter 4 gives the complete analysis for the proposed half-bridge converter.
Operation, design methodology, simulation and experimental results are presented. Dynamic
characteristics are presented in this chapter.
Chapter 5 concludes the thesis.
Contributions of this thesis are,
1) Improvised push-pull and half-bridge converters suitable for soft switching.
2) Idealized analytical model helpful in the design of such converters.
3) Validation of the design through a 200W push-pull converter switching at 300kHz
and a 640W half-bridge converter switching at 300kHz for critical performance
figures.
2
4) Closed loop control design for desired bandwidth and accuracy. Verification of loop
gain through network analyzer. The loop gain bandwidth achieved is about 30kHz for
the push-pull converter and 20kHz for half-bridge converter.
The use of network analyzer, and the measurement of dynamic performance
are all presented in the appendix.
3
CHAPTER 2
Soft Switching Topologies: An Overview
2.1 Introduction
This chapter gives an introduction to the problems associated with hard switching.
Advantages of soft switching techniques over the hard switching are discussed. Some of the
soft switching topologies that are available in the literature are also reviewed.
Section 2.2 discusses the problems associated with hard switching. Section 2.3 lists
the advantages of the soft switching techniques. Soft switching families like resonant load
converters, resonant switch converters, resonant transition and active clamp converters are
reviewed in section 2.4. Finally the issues associated in achieving ZVS in push-pull converter
and half-bridge converter are presented in section 2.5.
2.2 Hard Switching
In conventional PWM SMPS, the switches turn-on full current from full voltage.
Similarly the turn-off is to full voltage from full current. Such switching is classified as hard
switching. The losses during hard switching are considerable. Further, on account of the
parasitic capacitances and inductances of the switching circuit, the turn-off voltage and turnon current are more than full [2]. Fig. 2.1 shows diode clamped inductive load. Fig. 2.2 shows
its switching waveforms and switching trajectory. Switching loss for the switching waveform
in fig. 2.2 is given by,
1
 1

Switching loss =  × Vg × Il × tr × f s  +  × Vg × Il × t f × f s 
2
 2

Vg = Source Voltage; Il = Load Current
f s = Switching Frequency; tr = Rise time; t f = Fall time
D
Vg
Sw
Il
V ds I sw
Fig. 2.1 Circuit diagram of clamped inductive circuit
4
(2.1)
Turn Off
Vds = Vg
Turn On
Turn Off
I sw = Il
V
ds
I
, I sw
t
tr
tf
sw
Turn On
Vds
Fig. 2.2 Switching waveforms and switching Trajectory
From the equation 2.1 it is seen that switching losses are proportional to the switching
frequency. Fig. 2.3 shows the typical switching trajectory when parasitics effects are present.
Turn Off
I sw
Turn On
V
ds
Fig. 2.3 Effects of parasitics on switching trajectory
In order to protect the devices from the switching stresses of high off-state voltages
and high on-state currents, snubber circuits are used. Snubber circuits are of two types - turnoff snubber and turn-on snubber.
Turn-off snubber uses resistor, capacitor and diode. During turn-off, the capacitor C
effectively comes across the device and limits the rate of rise of voltage. Thus overvoltages
during the turn-off process are snubbed. The device turn-off loss is also reduced. When
properly sized, the snubber may also marginally reduce the overall losses. Fig. 2.4-a shows
the diode clamped inductive load with turn-off snubber.
Turn-on snubber is the dual of turn-off snubber. It uses inductor, resistor and diode.
During turn-on, the inductor limits the rate of rise of current. Thus overcurrents during the
turn-on process are snubbed. The device turn-on loss is also reduced. When properly sized,
the snubber may also marginally reduce the overall losses. Fig. 2.4-b shows the diode
5
clamped inductive load with turn-on snubber. Switching trajectory with snubber circuits is
shown in fig. 2.5.
L
Vg
D
I sw
Il
Vds
Vg
R
Ds
Ds
D
I sw
Ic
C
R
Il
Vds
(b) Turn on snubber
( a ) Turn off snubber
Fig. 2.4 Circuit diagram of clamped inductive circuit with turn-off snubber and turn-on snubber
I sw
Turn off
Turn on
V ds
Fig. 2.5 Turn-on and turn-off switching trajectory with snubber circuits
2.3 Soft Switching
Although snubber circuits reduce the loss during one switching transition, during the
other switching transition the energy stored in snubber L or C will be dissipated in the
snubber resistor. Hence snubber circuits will contribute to additional losses. Further snubber
circuits are not so useful if the switching frequency is above 200kHz, because the energy
associated with the switching transition is more [19]. Hence soft switching techniques are
used to achieve loss-less switching in order to obtain good efficiency at high switching
frequency.
In ZVS, the device voltage is zero just before the turn-on, thus totally eliminating the
turn-on losses. In ZCS, the device current is zero just before the turn-off, thus totally
eliminating the turn-off losses.
6
The following are the features of soft switching,
1) Soft switching converters can be switched at high frequency.
2) High frequency switching reduces the converter size.
3) Switching process is not abrupt. So it emits less EMI.
4) The energy stored in the parasitics can be recovered fully.
Fig. 2.6 shows the soft switching trajectory.
I sw
I sw
ZV turn on
ZC turn off
Assisted turn off
Vds
Assisted turn on
Vds
(b) ZCS trajectory
(a) ZVS trajectory
Fig. 2. 6 Soft switching trajectory
2.4 Soft Switching Topologies
The following section reviews some of the existing soft switching families. Some of
the soft switching techniques available for push-pull converter in the literature is also
reviewed. Advantages and disadvantages of the existing topologies are discussed.
2.4.1 Resonant Converters
1. Resonant Load Converters
Resonant load converters employ resonant circuits for power conversion. Historically
they are the first soft switching converters proposed. They exhibit ZVS/ZCS property. ZVS

is achieved if the switching frequency is greater than resonant frequency ωr  ωr = 1

L r Cr


.


ZCS is achieved if the switching frequency is lesser than the resonant frequency ωr . Output
voltage control in such converters is achieved through the control of switching frequency.
7
Resonant load converters are classified into series loaded resonant converter and
parallel loaded resonant converter. Fig. 2.7 shows the series loaded resonant converter. Fig.
2.8 shows the parallel loaded resonant converter.
C1
S1
Lr
Cr
Vg
Co
S2
RL
C2
Fig. 2.7 Series loaded resonant converter
Lo
S1
C1
Vg
Lr
Co
Cr
S2
RL
C2
Fig. 2.8 Parallel loaded resonant converter
Detailed analysis of resonant converters are given in the references [4] and [8]. A
constant frequency switching phase modulated series resonant converter is given in reference
[11].
Fig. 2.9 shows the typical switch voltage and switch current waveforms for series
resonant converter under ZVS condition. During the turn-on, the device current is negative.
This indicates that during the turn-on, the switch achieves ZVS.
8
Body diode conducting
Voltage across switch
Device current is negative
Switch current
Fig. 2.9 Typical switch voltage and switch current waveforms
2. Resonant Switch Converters
Resonant switch converters or quasi-resonant converters achieve ZVS or ZCS by
using resonant switches. Resonant switches consist of switch and resonant elements ( L r and
Cr ). They are classified based on switch current (half wave or full wave), type of resonant
switches (M - type or L – type) and soft switching techniques (ZVS or ZCS). Fig. 2.10 shows
the full wave quasi-resonant buck converter. Reference [5] and [9] gives the analysis of
quasi-resonant converters. Unified model of all quasi-resonant converters are given in
reference [5].
S1
Lo
Lr
Vg
Cr
Df
Co
RL
Fig. 2.10 Quasi-resonant ZCS full wave buck converter
9
Body diode conducting
Voltage across switch
Device current is negative
Switch current
Fig. 2.11 ZCS waveforms of quasi-resonant full wave buck converter
Fig. 2.11 shows the typical switch voltage and switch current waveforms. The device
current crosses zero and becomes negative during turn-off process. This indicates that during
turn-off transition the switch achieves ZCS.
Disadvantages of Resonant Converters
1) The currents/voltages are sinusoidal. So the peak value is much higher than
the equivalent square wave PWM converters, for processing the same amount
of power.
2) The conduction loss increases considerably because of the increase in peak
currents.
3) Resonant load and quasi-resonant converters have variable frequency
operation. The magnetics has to be designed for lowest operating frequency.
4) Resonant converters operate in wide range of switching frequency. So
designing of EMI filter is difficult.
5) Control of resonant converters is more complex than the hard-switched PWM
converters.
2.4.2 Resonant Transition Converters
Resonant transition converters are more recent family of soft switching converters.
The following are the features of the resonant transition converters,
10
1) Soft switching of all devices is possible.
2) Switching frequency is constant.
3) Control is by PWM.
4) Peak voltage/current stress of the devices is limited to throw voltage and pole
current.
5) Parasitic inductance and capacitance in the circuit may be used as the resonant
elements.
L
S1
S2
o
Llk
Co
Vg
S1
RL
S2
Fig. 2.12 Full-bridge phase modulated resonant transition converter
S1
S1
S2
S2
t
Fig. 2.13 Phase Modulated Resonant Transition Converter Control Signals
11
Full-bridge phase modulated resonant transition converter is the most popular
converter of this family. Fig. 2.12 shows the circuit diagram of phase modulated full-bridge
resonant transition converter. Its corresponding idealized control pulses are shown in fig.
2.13. In this family, ZVS is dependent on load current. Reference [7] and [13] shows the
complete analysis of phase modulated resonant transition converter. Fig. 2.14 shows the
typical primary voltage and current waveforms of phase modulated resonant transition
converter.
Voltage across the
transformer
Current through the
transformer
Fig. 2.14 Typical primary voltage and current waveforms of full-bridge resonant transition
phase modulated converter
2.4.3 Active clamp converters
Active clamp converters are recently introduced family of ZVS converters. This
topology adds an active clamp network to the hard-switched converter. This active clamp
network is responsible for achieving ZVS. It consists of an auxiliary switch and resonant
elements ( L r and Cr ). Active clamp converters are used with both isolated and non-isolated
topologies.
Reference [6] and [10] gives the analysis of active clamp converters. The
following are the features of active clamp converters,
1) Switching frequency is constant.
2) Control is by PWM.
3) Soft switching is possible in all the switches used.
12
4) Switch stress is minimum due to clamping action.
5) Conduction loss and dynamic characteristics are nearly same as the hardswitched PWM converters.
2.4.4 ZVS Push-Pull Converter
A ZVS push-pull converter has been proposed in the reference [14]. Fig. 2.15 shows
the circuit diagram and the control signals are shown in the fig. 2.16. Synchronous rectifiers
S3 and S4 freewheels the magnetizing current during t 0 to t1 , which is shown in fig. 2.16.
This energy is used to discharge the switch output capacitance just before the time of turn-on.
For achieving ZVS synchronous rectifier should always be used. Reference [14] gives the
steady state analysis and dynamic analysis of the ZVS push-pull converter.
Lo
S4
Co
Vg
S1
S3
S2
Fig. 2.15 ZVS push-pull converter with synchronous rectifiers
S1
S2
S3
S4
t
0
t1
0.5Ts
t
Ts
Fig. 2.16 Control signals for ZVS push-pull converter
13
RL
Switch current is negative
Fig. 2.17 Typical switch current waveforms of ZVS push-pull converter
Typical switch current waveforms are shown in fig. 2.17. During turn-on, the switch
current is negative. This indicates that the device is achieving ZVS during turn-on.
2.5 Issues associated in achieving ZVS in controlled Push-Pull and Half-bridge
converter
Fig. 2.18 shows the push-pull converter. The transformer leakage inductance is
lumped in the secondary circuit and it is represented as Llk . Fig. 2.19 shows the essential
waveforms.
Llk
Dp
L
CL
VDC
S1
Llk
S2
Fig. 2.18 Push-Pull Converter
14
Dn
R
The duty cycle of the converter is fixed near 50% with a small dead time Td . When
S1 is on, the secondary diode D n takes the load current. When S1 is switched off, the
leakage inductance of the transformer forces the current in the primary circuit in such a way
that it flows through the body diode of switch S2 . If S2 is turned on when body diode is
conducting it achieves ZVS. Thus ZVS can be achieved if the duty cycle is fixed very near to
50%. Regulation cannot be achieved if the duty cycle is fixed. This condition is applicable to
half-bridge converter also. Hence controlled push-pull and half-bridge converters cannot
readily achieve ZVS.
S1
S2
I S1
I S2
I DP
&
I DN
Td
Fig. 2.19 ZVS Waveforms for Push-Pull Converter ( D ≈ 50% )
The proposed circuit to be introduced uses two additional switches and two
diodes. The additional switches introduce freewheeling intervals in the circuit and thus enable
loss-less switching. In classical push-pull and half-bridge converters, the transformer primary
is left open during two sub-intervals in a period. On account of this feature, the turn-on of the
switch in these converters is always hard. The new circuit topology converts these open
circuit intervals into freewheeling intervals with such a modification, all trapped energy in the
core is conserved to achieve ZVS during all the transitions.
15
2.6 Conclusion
There are numerous soft switching converters that are mentioned in the literature.
Some of these soft switching converters are switching above 1MHz and are in commercial
use. Analysis and design methodology of soft switching converters are complex than the hard
switched PWM converters. Such soft switching converters have the attractive operational
features like compactness, efficiency and low EMI. Hence soft switching converters have
taken up an appreciable share of the SMPS market.
In the following chapters the ZVS push-pull converter and half-bridge converter are
introduced. Operation, design methodology and results are presented in the subsequent
chapters.
16
CHAPTER 3
Analysis and Design of ZVS Push-Pull Converter
3.1 Introduction
This chapter introduces the ZVS push-pull converter. Operation of the circuit is
explained. Design procedure is presented. Simulation and experimental results are presented
to validate the design procedure. Further this chapter discusses small signal behavior of the
proposed circuit.
Section 3.2 introduces the ZVS push-pull converter. The idealized operation of the
proposed circuit is presented. Design procedure and parameters affecting ZVS are explained
in the section 3.3. Section 3.4 gives a sample design of 200W, 300kHz ZVS push-pull
converter. Simulation and experimental results are presented in section 3.5. Estimated and
experimental dynamic characteristics are presented in section 3.6. Regulation and loss
distribution are presented in section 3.7 and 3.8 respectively.
3.2 Proposed Circuit and Operation
Fig. 3.1 shows the proposed ZVS push-pull converter. This circuit is obtained from
the hard-switched push-pull converter by connecting two switches (S3 & S4 ) and two
diodes (D3 & D4 ) as in fig. 3.1. The leakage inductance of the transformer is lumped on the
secondary side and represented as Llk in fig. 3.1. C1 and C2 are the snubber capacitors.
Dp
Llk
VDC
I p1
D4
S1
C1 Vc1
I Dn
V p 2 P2
Llk
S4
S3
I p2
S2
D1
C2 V
c2
D2
Fig. 3.1 ZVS push-pull circuit
17
Vo
I Dp
V p1 P1
D3
L
Dn
Co
R
Fig. 3.2 indicates the gate pulses Vg1 , Vg2 , Vg3 and Vg4 for the switches S1 , S2 ,
S3 and S4 respectively. S3 and S4 have a duty ratio of nearly 50% (with a small dead
time). The dead time (Td ) is also shown in fig. 3.2.
V
Td
g1
Vg3
Vg
2
Vg
4
DTs
DTs
Fig. 3.2 Control pulses
Idealized operation of the circuit is explained by a set of 6 intervals. Fig. 3.3 shows
the idealized waveforms of primary switch current, snubber capacitor current and secondary
diode currents.
I s1
I s3
Is2
I Dp & I Dn
I c1
Ic2
t0
t1
t
2
t3 t4
Fig. 3.3 Idealized waveforms
18
t5
The following are the assumptions made during the idealized analysis:
1. Switching devices are ideal.
2. Diodes are ideal.
3. Device output capacitance is neglected. Only the effect of snubber capacitor is
considered.
4. Primary leakage inductance effects are neglected.
The notations Vp1 , Vp2 , Ip1 , Ip2 , Vc1 and Vc2 used in the analysis throughout this
chapter are referred to fig. 3.1. The following are the symbols used in the analysis,
Im = Magnetizing current
n = Turns ratio
(IDn ∼ IDp )
n
IDn , IDp = Secondary rectifier current
Irefl = Reflected load current =
Interval T1 (t 0 < t < t1 )
In interval T1 , S1 and S3 are on. When S1 is conducting, diode D3 is reverse biased
in the primary circuit. In the secondary circuit diode D n is forward biased. This interval is
known as power transfer interval. During this interval power is transferred from primary to
secondary. The following equations are valid for this interval. Fig. 3.4 shows the conduction
path and fig. 3.5 shows the equivalent circuit for interval T1 .
Primary Circuit:
I p1 = I m + I refl
I refl =
(3.1)
( I Dn − I Dp )
n
(3.2)
Vc 2 = 2VDC
(3.3)
= −VDC
(3.4)
V
p1
Secondary Circuit:
I Dn = I L ; I Dp = 0
(3.5)
VDC
dI
− Vo = ( L + Llk ) L
n
dt
(3.6)
19
IL
Dp
Vo
L
I p1
Co
VDC
D3
S3
S1
C1
I Dn
D4
R
Dn
S4
S2
C2
D1
D2
Fig. 3.4 Conduction path in interval T1
L + Llk
VDC
Im
Lm
VDC
n
IL
n
Co
Vo
R
Fig. 3.5 Equivalent Circuit for interval T1
Interval T2 (t1 < t < t 2 )
Interval T2 begins when S1 is turned off. The snubber capacitor C1 assists the turn-
off process of S1 . As the turn-off process is capacitor assisted, the turn-off process is low loss
switching transition. The magnetizing current and reflected current charge C1 from 0 to
VDC and discharge C2 from 2 VDC to VDC . Although S3 is on, D3 is still reverse biased
because the voltage VC1 has not reached to VDC .
In the secondary circuit D n takes the load current. This interval is known as resonant
transition-I interval. Fig. 3.6 shows the conduction path in interval T2 . The following
equations are valid for this interval. Fig. 3.6 shows the conduction path and fig. 3.7 shows the
equivalent circuit for interval T2 .
20
Primary circuit:
I p1 = I p 2 = I p
(3.7)
I p = I m + I refl ; Irefl =
Ip
C
=
d (Vc1 + Vc 2 )
dt
I Dn − I Dp
n
(3.8)
; C1 = C2 = C
(3.9)
The initial conditions for this interval are,
Vc1 (t1 ) = 0;Vc 2 (t1 ) = 2VDC
(3.10)
This interval ends when Vc1 reaches VDC and current commutates to S3 , D3 .
Vc1 (t2 ) = VDC ;Vc 2 (t2 ) = VDC
(3.11)
Secondary circuit:
V ( t ) − VDC
Secondary voltage,Vsec ( t ) = c 2
n
Vsec ( t ) − Vo = ( L + Llk )
( 3.12 )
dI L
dt
( 3.13)
Dp
IL
Vo
L
I p1
VDC
S3
S1
D3
C1
D1
D4
Co
I Dn
Dn
S4
S2
C2
D2
Fig. 3.6 Conduction path in interval T2
21
R
L + Llk
Lm
IL
n
C1 = C
Vo
Co
Vsec (t )
R
C2 = C
Fig. 3.7 Equivalent circuit for interval T2
Interval T3 (t 2 < t < t 3 )
Interval T3 begins when C1 charged to VDC . As C1 charged to VDC , D3 is
forward biased. The magnetizing current and reflected current Ip1 freewheel through S3 and
D3 . This interval is known as freewheeling interval. The leakage inductance Llk ensures
that only D n takes the load current. Fig. 3.8 shows the conduction path and fig. 3.9 shows the
equivalent circuit for interval T3 .
Dp
IL
Vo
L
I p1
Co
VDC
D3
S3
S1
D4
I Dn
Dn
S4
S2
C1
R
C2
D1
D2
Fig. 3.8 Conduction path in interval T3
L + Llk
Lm
IL
n
Fig. 3.9 Equivalent circuit for interval T3
22
Co
Vo
R
Primary circuit:
V p1 = 0
(3.14)
Vc1 = Vc 2 = VDC
(3.15)
Secondary circuit:
−Vo = ( L + Llk )
dI L
dt
(3.16)
Interval T4 (t 3 < t < t 4 )
At the start (t = t 3 ) of this interval T4 , S3 is switched off. The magnetizing current
and reflected current charge C1 from VDC to 2VDC and discharge C2 from VDC to 0.
This interval is known as resonant transition – II interval. From the equivalent circuit (fig.
3.11) it is clear that reflected current and magnetizing current discharges C2 . So magnetizing
inductance and leakage inductance has to be designed to discharge C2 . In the secondary
circuit the load current starts shifting from D n to D p . Fig. 3.10 shows the conduction path
and fig. 3.11 shows the equivalent circuit for interval T4 .
I Dp
Dp
S3
S1
D3
C1
D1
D4
Vo
L
Ip
VDC
IL
Co
I Dn
S4
S2
Dn
C2
D2
Fig. 3.10 Conduction path in interval T4
23
R
L
Lm
IL
n
C1 = C
Llk
Vsec (t )
C2 = C
I Dp
Llk
R
Co
I Dn
Fig. 3.11 Equivalent circuit for interval T4
The equations valid for this interval are,
Primary circuit:
I p1 = I p 2 = I p
Ip
C
=
(3.17)
d (Vc1 + Vc 2 )
(3.18)
dt
V p1 = Vc1 (t ) − VDC
(3.19)
V p 2 = VDC − Vc 2 (t )
(3.20)
The initial conditions for this interval are,
Vc 2 (t3 ) = VDC ;Vc1 (t3 ) = VDC
(3.21)
This interval ends when Vc1 reaches 2VDC and Vc2 discharges fully.
Vc 2 (t 4 ) = 0;Vc1 (t4 ) = 2V DC
Secondary circuit:
Vsec ( t ) =
Vc1( t ) − VDC
n
Vsec ( t ) = Llk
( 3.23)
dI Dp
−Vsec ( t ) = Llk
−Vo = L
(3.22)
( 3.24 )
dt
dI Dn
dt
( 3.25)
dI L
dt
( 3.26 )
24
Interval T5 (t 4 < t < t 5 )
Interval T5 begins when C2 is discharged fully. As C2 is discharged, the
magnetizing current and reflected load current forward biases D2 . The magnetizing current
and reflected load current (Ip2 ) flow through D 2 . When current is flowing through D 2 , S2
and S4 are turned on. Thus zero voltage switching of device S2 is achieved. This interval is
known as ZVS interval. When S2 is on D 4 is reverse biased in the primary circuit.
When the primary current direction changes its direction, S2 takes the current from
D 2 . At the end of this interval D n blocks fully and D p takes the full load current. The time
of interval T5 is decided by the leakage inductance. The following are the equations
determining this interval. Fig. 3.12 shows the conduction path and fig. 3.13 shows the
equivalent circuit for interval T5 .
Primary circuit:
I p 2 = I m + I refl
I refl =
(3.27)
( I Dp − I Dn )
(3.28)
n
V p 2 = VDC
(3.29)
Secondary circuit:
dI Dp
VDC
= Llk
n
dt
(3.30)
V
dI
− DC = Llk Dn
n
dt
(3.31)
−Vo = L
dI L
dt
(3.32)
25
I Dp
Dp
IL
Vo
L
Co
VDC
S3
S1
D3
D4
I p2
S2
C1
Dn
I Dn
S4
R
C2
D1
D2
Fig. 3.12 Conduction path in interval T5
Vo
L
Lm
VDC
IL
n
Llk
VDC
n
I Dp
Llk
Co
R
I Dn
Fig. 3.13 Equivalent circuit in interval T5
Interval T6 (t > t 5 )
This interval is known as power transfer interval. During this interval S2 and S4 are
on in the primary circuit. D4 is reverse biased in the primary circuit. Dp is forward biased
in the secondary circuit. Fig. 3.14 shows the conduction path and 3.15 shows the equivalent
circuit in interval T6 . This interval is followed by similar sets of intervals as before to
achieve ZVS for S1 .
Interval T6 is the complimentary interval of T1 . Each cycle consists of 10 intervals.
These are given in table 3.1. Table 3.2 gives the currents and voltages in the secondary
circuit.
26
Primary circuit:
I p 2 = I m + I refl
I refl =
(3.33)
( I Dp − I Dn )
n
(3.34)
Vc1 = 2VDC
(3.35)
V p 2 = VDC
(3.36)
Secondary circuit:
VDC
dI
− Vo = ( L + Llk ) L
n
dt
( 3.37 )
I Dp
Dp
IL
L
Co
I p2
VDC
D3
S3
S1
D4
C1
R
Dn
S4
S2
C2
D2
D1
Fig. 3.14 Conduction path for interval T6
L + Llk
VDC
Lm
IL
n
VDC
n
Fig. 3.15 Equivalent circuit in interval T6
27
Co
Vo
R
Interval Conducting
Vc1
Vc2
Vp1
Vp2
Interval
devices
Intervals for S1
T1
S1
0
2VDC
-VDC
-VDC
Power transfer
T2
C1 , C2
Vc1 (t)
Vc2 (t)
Vc1 (t)-VDC
VDC -Vc2 (t)
Resonant transition-I
T3
S3 , D3
VDC
VDC
0
0
Freewheeling
T4
C1, C2
Vc1 (t)
Vc2 (t)
Vc1 (t)-VDC
VDC -Vc2 (t)
Resonant transition –II
T5
D 2 , S2
2VDC
0
VDC
VDC
ZVS interval
Complimentary intervals for S 2
T6
S2
2VDC
0
VDC
VDC
Power transfer′
T7
C1, C2
Vc1 (t)
Vc2 (t)
Vc1 (t)-VDC
VDC -Vc2 (t)
Resonant transition-I′
T8
S4 , D 4
0
0
Freewheeling′
T9
C1, C2
Vc1 (t)-VDC
VDC -Vc2 (t)
Resonant transition –
VDC
Vc1 (t)
VDC
Vc2 (t)
II′
T10
D1 , S1
0
2VDC
-VDC
-VDC
ZVS interval′
-VDC
Power transfer
Intervals for S1 (Next Cycle)
T1
S1
0
2VDC
-VDC
Table 3.1 Tabular columns showing the voltages in the primary circuit
(′ - Represents the intervals for the switch S2 )
28
Interval Conducting
I Dp
I Dn
devices
Vsec
Slope of the Inductor (L)
(Secondary
current
voltage)
Intervals for S1
T1
Dn
0
IL
VDC
n

1 

 ( Vsec - Vo )
 L + Llk 
T2
Dn
0
IL
VDC - Vc1 (t)
n

1 

 ( Vsec - Vo )
 L + Llk 
T3
Dn
0
IL
0

1 

 ( Vsec - Vo )
 L + Llk 
T4
Dp , Dn
IL - IDn (t)
IDn (t)
Vc1 (t) - VDC
n
V
− o
L
T5
Dp , Dn
IL - IDn (t)
IDn (t)
VDC
n
V
− o
L
Complimentary intervals for S 2
T6
Dp
IL
0
VDC
n

1 

 ( Vsec - Vo )
 L + Llk 
T7
Dp
IL
0
VDC - Vc2 (t)
n

1 

 ( Vsec - Vo )
 L + Llk 
T8
Dp
IL
0
0
T9
Dp , Dn
IL - IDn (t)
IDn (t)
Vc2 (t) - VDC
n

1 

 ( Vsec - Vo )
 L + Llk 
V
− o
L
T10
Dp , Dn
IL - IDn (t)
IDn (t)
VDC
n
V
− o
L
Intervals for S1 (Next cycle)
T1
Dn
0
VDC
n
IL

1 

 ( Vsec - Vo )
 L + Llk 
Table 3.2 Tabular column showing voltages and currents in the secondary
29
3.3 Designing for ZVS
3.3.1 Parameters affecting ZVS
There are various parameters affecting ZVS. They are magnetizing current, leakage
inductance of the secondary, leakage inductance of the primary, time delay, load current and
device output capacitance. The choice of the various parameters is a trade-off between
switching loss and conduction loss. The following section explains about the various
parameters affecting ZVS.
1. Magnetizing current
Magnetizing current aids ZVS. Fig. 3.16 shows the magnetizing current and voltage
across on half of the primary winding. It is seen that magnetizing current is in the direction to
discharge the device output and snubber capacitance. Hence higher the value of magnetizing
current is good from the ZVS point of view. But increase in magnetizing current increases the
conduction loss and peak current.
Fig. 3.16 Voltage across one half of the primary winding and magnetizing current
2. Leakage inductance of the secondary side
Leakage inductance of the secondary side aids ZVS. Leakage inductance limits rate of
reversal of reflected current in the primary circuit. Higher value of leakage inductance means
more energy is available to discharge the device output capacitance and snubber capacitance.
30
But increase in leakage inductance decreases the effective duty ratio. Hence utilization of the
installed components is less. Further leakage inductance resonates with junction capacitance
of diode and causes severe ringing. Fig. 3.17 and fig. 3.18 shows the secondary voltage,
current through diode and rectified voltage. From the fig. 3.17 and fig. 3.18 it is clear that the
effective duty cycle reduces with the increase in leakage inductance.
Duty cycle lost
Secondary
voltage
Rectified
voltage
Current
through
diode
Fig. 3.17 simulation waveforms with secondary leakage inductance = 1.2µH
Duty cycle lost
Secondary
voltage
Rectified
voltage
Current
through
diode
Fig. 3.18 simulation waveforms with secondary leakage inductance = 4µH
31
3. Snubber capacitor and device output capacitor
Snubber capacitance and device output capacitance together called as effective
capacitance. Increasing the value of effective capacitance reduces the turn-off switching loss.
Further it will reduce any voltage spike that is caused during turn-off transition. But higher
value of effective capacitance demands more energy to be stored in magnetizing inductance
and leakage inductance.
4. Time delay
Fig. 3.19 shows the voltage across the S2 , current through S2 and current through
the effective capacitance C2 during ZVS instant. The operation of the circuit during ZVS is
explained through 3 sub-intervals. The sub-intervals are mentioned in the fig. 3.19 as τ1, τ2
and τ3.
Vc 2
I s1 + I c1
τ1
τ2
τ3
Fig. 3.19 Idealized waveforms during ZVS
Interval T4 (Resonant transition – II interval) is same as the sub-interval τ1. During this
sub-interval - τ1 the capacitance C2 discharge from VDC to 0. If the switch is turned on
during this sub-interval - τ1 results in hard switching. The time of discharge of the capacitor
depends only on the reactive elements (leakage inductance and effective capacitance).
32
During sub-interval τ2 the body diode of the switch conducts. As body diode of the
switch is conducting during this sub-interval - τ2, If the switch is turned during sub-interval
τ2 ZVS can be achieved. The time of sub-interval τ2 depends on the reflected current. Higher
load current increases the sub-interval τ2. This is shown in fig. 3. 20 through simulation
results.
If the switch is not turned on during sub-interval τ2, the effective capacitance charges
again. So the switching will be hard.
So, time delay of the circuit should be above τ1 and below (τ1 + τ2).
Fig. 3.20 switch current during ZVS transition
(For different value of load resistance, R1>R2>R3)
5. Leakage inductance of the primary
Fig. 3.21 shows the various leakage inductances in the push-pull transformer. Primary
leakage inductances are represented as Llk,p1 and Llk.p2 in fig. 3.21. Secondary leakage
inductances are represented as Llk,s in fig. 3.21. During transition of intervals from T2 to
T3 and T4 to T5 , the magnetizing current and reflected current shifts its path from full
primary winding to one half of the primary winding. So the energy trapped in any of the
primary leakage inductance causes ringing in the waveforms. Snubber circuits have to be
33
used to reduce the ringing. It is advantageous to have very low value of primary leakage
inductance.
Llk , p1
Llk , s
Llk , p 2
Llk , s
Fig. 3.21 Leakage inductances of the push-pull transformer
3.3.2 Design Procedure
There are two important parameters which decides the ZVS, they are
1. Energy available in leakage (secondary leakage inductance) and magnetizing
should be sufficient to discharge the device output capacitance and snubber
capacitance.
2. Sufficient time delay should be available to discharge the device output
capacitance.
Fig. 3.22 shows the equivalent circuit in the primary side during the interval T4 .
Im
Lm
C1 = C
IL
n
⇒
C1 = C
Lm & Llk *
 IL

 n + Im 


C2 = C
C2 = C
Fig. 3.22 Equivalent circuit in the primary side during interval T4
The following equations are used to design the leakage inductance, magnetizing
inductance and time delay.
34
−L
dI 2
− ∫ idt = 0
dt C
(3.38)
L 
L = Lm || L*lk ; L*lk =  lk 
 2
 2n 
On solving,
I (t ) = i (0) cos
(3.39)
2
t
LC
VC 2 = VDC − i (0)
(3.40)
L
2
t
sin
LC
2C
(3.41)
Equation 3.41 gives the condition to achieve ZVS. The condition is,
VDC ≤ i (0)
L
; i (0) = I m + I refl
2C
(3.42)
From 3.40 minimum time required discharge the effective capacitance can be
determined.
ϖ=
2
;
LC
( 3.43)
T = π 2 LC is the total time period .
∴the time taken to disch arg e the snubber capaci tan ceTd =
∴ Minimum time delay =
π
2 2
T
4
LC
( 3.44 )
( 3.45)
The following are the steps to be followed while designing the reactive elements
(leakage inductance and snubber capacitor) for ZVS push-pull converter.
Step: 1:
Based on switching frequency and device characteristics select the time delay and
effective capacitance (output capacitance and snubber capacitance).
35
Step: 2:
Calculate the L from the equation 3.45. Calculated value of L is approximately equal
to L*lk because magnetizing inductance L m is much higher than the leakage inductance.
Step: 3:
If the equation 3.42 is not satisfied with the value of the leakage inductance then
magnetizing current has to be increased to satisfy the equation 3.42.
3.3.3 ZVS limit
From the above design procedure (Equation 3.42) it is understood that ZVS is
dependent on load current and magnetizing current. At lightly loaded condition it is difficult
to achieve ZVS because the energy stored in the leakage inductance and magnetizing
inductance may not be sufficient to discharge the effective capacitance prior to the turn-on of
the switch. When the load current is high, the reflected current in the primary is more. So it
is easy to achieve ZVS at higher load currents.
So for a wider ZVS range more energy has to be stored in leakage and magnetizing
inductance. Wider ZVS range suffers from the disadvantage of higher conduction loss. Hence
selecting the ZVS range is a trade off between conduction loss and switching loss.
3.4 Design and development of a 300kHz / 200W Push-Pull converter
This section presents the specifications and block diagram of the power supply.
Design aspects of the power supply are discussed. Step by step design procedure is explained.
Fig. 3.23 shows the block diagram of the prototype developed.
Input voltage
40-48V
Output voltage
20V
Output power
200W
Switching frequency
300kHz
Closed loop bandwidth
30kHz
Table 3.3 Specification of the power supply
36
Push − Pull
Transformer
Input Filter
Synchronous
Proposed Push − Pull
VDC
Load
Re ctifiers
Circuit
Driver Circuit
Output Filter
Control /
PWM Generator
Voltage sensor
Fig. 3.23 Block diagram of the ZVS push-pull converter
3.4.1 Design Procedure
This section gives a sample design of 200W, 300kHz ZVS push-pull
converter.
Step: 1
Output voltage Vo = (20 + 1) = 21V, considering 1V diode drop.
Input voltage = 48V
Effective duty cycle = 32%
As mentioned earlier leakage inductance is added to achieve ZVS. This leakage
inductance reduces the effective duty cycle. It is assumed that there is 3% loss in duty cycle.
So the total duty cycle is 35%.
For push-pull converter the output voltage expression is given by,
V
Vo = DC 2D
n
On solving the above expression the number of turns is given by, n ≈ 1.5.
Step: 2
Based on the switching frequency and device characteristics, time delay is selected as
TD = 50ns.
37
Step: 3
Design of reactive elements (Leakage inductance and snubber capacitor):
Assume, C = 1n (including the device output capacitance and snubber capacitance)
TD = 50ns
From equation 3.45,
π
TD =
LC
2 2
On solving the above equation, effective inductance L = 2µH.
L
*
*
Effective inductance, L = L lk || L m ; where Llk = lk
2n 2
It is assumed that Lm is much higher than L*lk . So the effective inductance is
approximately equal to L*lk .
L
On solving, L*lk = lk
2n 2
Secondary leakage inductance (Llk ) = 1.7µH.
Step: 4
ZVS limit is selected to be 6A. Hence the reflected current in the primary under this
condition is given by,
Irefl =
=
Load current
, n = no.of turns
n
6
= 4A
1.5
Step: 5
For achieving ZVS, the following inequality must be satisfied.
38
VDC ≤ ( Im + Irefl )
L
2C
VDC = 48V; Irefl = 4A; L = 2µH
On subsitituting the above values in the inequality
48 ≤ (Im + 4)31.662
The above exp res si on is valid even when magnetizing current Im = 0A
Hence leakage inductance alone is sufficient to discharge the device output
capacitance and snubber capacitance. As leakage inductance alone is sufficient to achieve
ZVS. Additional magnetizing inductance is not added to achieve ZVS.
Step: 6
The transformer core uses high frequency ferrite material N87. The core is operated at
a flux density (< 0.1 T) to have low core losses. In order to reduce skin effect losses, the
conductors are made of foil shape.
Details of the transformer:
Ferrite material used - N87
Size of the core used - ETD 44/22/15
Copper foil details - 105µm (Thickness), 28mm(width)
Primary Turns - 3T, 2 strand.
Secondary Turns - 2T, 2 strand.
Step: 7
In order to have lower core losses of the leakage inductance, high frequency core
material is used. N87 is selected as the core material. To reduce the skin effect losses, foil
shaped conductors are used.
Leakage inductance ( Llk ) required to achieve ZVS = 1.7µH.
The transformer has a secondary leakage inductance of 0.8µH. So the additional
leakage inductance required is 0.9µH.
39
Details of the leakage inductance:
Ferrite material used - N87.
Size of the core - EFD25
Foil details - 105µm (thickness), 20mm (width)
Turns - 2T, 2 strand.
Step: 8
Design of filter inductor
The output filter inductor takes DC current and the ripple component is very less. It is
not required to use high frequency ferrite material for the filter inductor. N67 is used as the
core material. It is assumed that the peak-to-peak ripple current is 10% of the full load current
(10A).


T
n2
− Vo  × D × s
 VDC ×
n1
2

L=
10% × IL
On substituting the values L value is found to be 7µH.
Step: 9
Design of output filter:
The output filter capacitor uses metallized polyester type. ESR of the capacitor is
6mΩ. As ESR of the capacitor is very low, it is assumed that output voltage ripple is because
of inductor ripple current only.
δIL × Ts
C × 16
Peak-to-peak ripple is assumed to 0.1% and the capacitor value is 6.6µf.
δVo =
Step: 10
Design of synchronous rectifiers:
Synchronous rectifiers are used for rectification instead of diodes. The synchronous
rectifiers have low conduction losses when compared to the switching grade diodes. Losses
of the synchronous rectifier depend on the R ds (on) of the Mosfet. Additional control logic is
used to drive the synchronous rectifiers. Fig. 3.24 shows the push-pull converter with
synchronous rectifiers. Fig. 3.25 shows the control pulses for the synchronous rectifiers. To
40
avoid cross conduction of synchronous rectifiers time delay is provided in the gate pulses of
the synchronous rectifiers, which is shown in fig. 3.25. Reference [22] explains the procedure
to design synchronous rectifiers.
Llk
Lo
S5
Co
S3
S4
Llk
D1
VDC
S1
RL
D2
S6
S2
Fig. 3.24 Proposed ZVS push-pull converter with synchronous rectifiers
V
Td
Td
g1
0.5Ts
Vg 6
Vg
2
Vg 5
DTs
DTs
Fig. 3.25 Control pulses for synchronous rectifiers
Step: 11
Control logic
The circuit uses UC3825 as the PWM controller. It can produce switching pulses up
to 1MHz. The controller can be used in voltage mode control as well as current mode control.
In the present application it is used as voltage mode controller. Some of the features of the
control IC are soft start, under voltage lock out, pulse-by-pulse current limiting and feed
forward control. The mono-stable multi-vibrator is used for generating the control pulses for
the switches (additional switches S3 and S4 ) and synchronous rectifiers.
41
3.5 Simulation and Experimental results
3.5.1 Simulation results
The converter designed above is simulated using Saber, a circuit-simulating tool. The
simulation is used to fine-tune the design procedure. The following are non-idealities of the
circuit elements used for the simulation,
1. Magnetizing inductance of the transformer – 35µH (Magnetizing inductance of each
half of the primary winding).
2. ESR of the output filter capacitor (6mΩ).
3. R ds (on) of the Mosfets.
4. Secondary leakage inductance of the transformer (0.8µH).
The primary leakage inductance is not used for the simulation. Primary leakage
inductance as discussed earlier it produces ringing in the primary waveforms. It doesn’t have
any significant effect in ZVS.
Simulation results and experimental results are presented for the following operating
point:
Input voltage, VDC = 48V
Output voltage, Vo = 20V
Output power, Po = 200W
Fig. 3.26 shows the control pulse for S1 ( Vg1 ), voltage across the switch S1 ( Vc1 ),
current through S1 ( Is1 ) and current through S3 ( Is3 ). Fig. 3.27 shows the control pulse for
S2 ( Vg2 ), voltage across S2 ( Vc2 ) and current through switches S2 ( Is3 ) and current
through S4 (Is4 ) .
ZVS can be achieved, if the switch is turned on when the voltage across the switch is
zero. If the body diode of the switch is conducting the voltage across the switch will be zero.
From the fig. 3.26 and fig. 3.27 it is seen that just before the time of turn-on the switch
current is negative. This indicates that the body diode is conducting. So the switches S1 and
S2 are achieving ZVS during turn-on.
Fig. 3.28 shows the current through diodes D p and D n . During the ZVS transitions,
the load current commutates from one diode to another, which is shown in fig. 3.28.
42
Body diode conducting
Vg1
Vc1
I s1 + I s3
ZVS transition
Fig. 3.26 ZVS waveforms for S1
Body diode conducting
Vg 2
Vc 2
I s2 + I s4
ZVS transition
Fig. 3.27 ZVS waveforms for S2
43
ZVS transition
Fig. 3.28 Secondary diode currents
3.5.2 Experimental Results
Fig. 3.29 shows the control pulses for the push-pull switches S1 and S2 . The primary
duty cycle of each pulse is kept at 34%. The switching frequency is 300kHz.
Fig. 3.29 Control pulses for S1 and S2
(Ch-1 – Control pulse for S1 & Ch-2 control pulse for S2 )
44
Fig. 3.30 shows the control pulses for the switches S1 and S3 . Duty cycle of the
switch S1 is 34% and the duty cycle of the switch S3 is near to 50%, with dead time. As
discussed earlier switch S3 provides a freewheeling path in the primary when S1 is off.
Fig. 3.30 Control pulses for S1 and S3
(Ch-1 – Control pulse for S1 & Ch-4 control pulse for S3 )
Fig. 3.31 shows the control pulses for S2 and S4 . Duty cycle of the switch S2 is
34% and the duty cycle of the switch S4 is near to 50%, with dead time. As discussed earlier
switch S4 provides a freewheeling path in the primary when S2 is off.
45
Fig. 3.31 Control pulses for S2 and S4
(Ch-2 – Control pulse for S2 & Ch-3 control pulse for S4 )
Fig. 3.32 shows the control pulses for S1 and synchronous rectifier S6 . A dead time
is provided in the pulse for synchronous rectifier, which is shown in fig. 3.32. Body diode of
the synchronous rectifier conducts during this dead time. The dead time is provided to avoid
cross conduction of the synchronous rectifier.
Fig. 3.33 shows the control pulses for S2 and synchronous rectifier S5 .
46
Dead time
Fig. 3.32 Control pulses for S1 and S6
(Ch-1 – Control pulse for S1 & Ch-3 control pulse for S6 )
Dead time
Fig. 3.33 Control pulses for S2 and S5
(Ch-2 – Control pulse for S2 & Ch-4 control pulse for S5 )
47
Fig. 3.34 shows the voltage across S1 and control pulse for S1 . The leakage
inductance between the two primary windings is responsible for the ringing in the Vc1
(voltage across switch S1 ) waveform, which is shown in fig. 3.34.
Fig. 3.34 Voltage across S1 and Control pulse for S1
(Ch-1 – Vc1 & Ch-2 control pulse for S1 )
Fig. 3.35 shows the voltage across S1 and control pulse for S1 during turn-on. From
fig. 3.35 it is clear that the voltage across the device falls just before applying the control
pulses. This indicates ZVS of the switch S1 during turn-on.
48
Fig. 3.35 Voltage across S1 and control pulses for S1
(Ch-1 – Vc1 & Ch-2 control pulse for S1 )
Fig. 3.36 shows the voltage across S2 and control pulse for S2 . The leakage
inductance between the two primary windings is responsible for the ringing in the Vc2
(voltage across switch S2 ) waveform, which is shown in fig. 3.34.
Fig. 3.37 shows the voltage across S2 and control pulse for S2 during turn-on. From
fig. 3.37 it is clear that the voltage across the device falls just before applying the control
pulses. This indicates ZVS of the switch S2 during turn-on.
49
Fig. 3.36 Control pulses for S2 and voltage across S2
(Ch-1 – Vc2 & Ch-2 control pulse for S2 )
Fig. 3.37 Control pulses for S2 and VC2
(Ch-1 – VC2 & Ch-2 control pulse for S2 )
50
Fig. 3.38 shows the voltage across the synchronous rectifier S6 . Additional
inductance, which is added to aid ZVS, oscillates with the junction capacitance of the body
diode of S6 . From fig. 3.38 it is clear that the peak of the ringing voltage goes twice the
nominal voltage. This is a disadvantage of the proposed topology.
A technique is proposed in the reference [17], in which the energy associated with the
ringing is fed back to the source instead of dissipating it in the snubber circuits.
Fig. 3.38 Voltage across synchronous rectifier S6
Fig. 3.39 shows the voltage across the synchronous rectifier S5 .
51
Fig. 3.39 Voltage across synchronous rectifier S5
3.6 Dynamic analysis of ZVS push-pull converter
The small signal dynamic model of push-pull converter is similar to PWM hardswitched converter. This is validated by measuring the small signal characteristics of the
push-pull converter using frequency response analyzer.
The additional leakage inductances, which are introduced for achieving ZVS, are of
small value when compared to the filter inductor. It is assumed that the filter inductor absorbs
these leakage inductances. So the converter function remains same as the hard-switched
PWM converter.
The control transfer function of the converter is of the form,
Vo
2 × n × VDC
G(S ) = =
(1 + sCRESR )
L
d
2
s LC + s + 1
R
L – Filter inductor and leakage inductance
52
(3.46)
C – Filter capacitor.
R – Load resistor
R ESR – ESR of the filter capacitor.
Fig. 3.40 shows the measured and estimated control characteristics of the push-pull
converter.
Fig. 3.40 Control gain characteristic of ZVS push-pull converter
3.6.1 Design of closed loop control
The closed loop controller is designed based on the requirements of steady state error,
bandwidth and transient response.
Based on the above requirements a compensator H(s) is designed such that the loop
gain H ( s ) × G ( s ) satisfies the above requirements. The structure of the compensator H(s) is
shown in fig. 3.41.
53
Vo*
+
d
H 2 ( s)
H1 ( s )
−
Vo
Fig. 3.41 Compensator block diagram
The first part of the compensator H1(s) gives the desired bandwidth and transient
response. The rule to be followed while designing the first part of the compensator is that
the loop gain should cross the 0dB (unity gain) with a single slope (-20dB/dec). The
second part of the compensator is to satisfy the requirements of the steady state error.
The overall compensator is of the form
H ( s ) = H1 ( s) H 2 ( s)
s

1+ ω
z2
H (s) = K 
s

 ω

z2
(3.47)
s 
 
+
1



ω z1 
×
 1+ s 
  ω 
 
p1 
(3.48)
( PI − Controller ) ( Lead − Lag compensator )
Fig. 3.42 shows the analog implementation of the compensator.
Vo*
Vo
−
−
+
+
Fig. 3.42 Analog circuit implementation of the compensator
54
d
Loop gain of the push-pull converter will be of the form
T (s) = G ( s) H (s)
(3.49)
s

1+

2 × n × VDC
ω z2
T (s) =
(1 + sCRESR ) × K 
L
s

s 2 LC + s + 1

R
 ω z2
s 
 
  1+ ω 
z1 
×


s

  1 + ω 
 
p1 
(3.50)
Fig. 3.43 shows the measured and estimated loop gain of the push-pull converter. The
frequency response analyzer used for measuring the loop gain gives reliable measurement up
to 30kHz. The experimental results and estimated results are almost matching in our region of
interest.
Fig. 3.43 Measured and estimated loop gain characteristics of push-pull converter
55
3.7 Line and load regulation
This section gives the line and load regulation of the proposed circuit. Table 3.4 gives
the load regulation of the converter when the input voltage 48V. It is observed that the output
voltage is fairly constant and in the entire load range of 10% to 100%. The converter achieves
the highest efficiency when it is fully loaded. Table 3.5 gives the line regulation of the
converter. The line regulation is observed under fully loaded condition. Fig. 3.44 gives the
plot of efficiency vs. load current.
S.
IL
Vout
Vin
Iin
Pin
Pout
No.
Output
Overall
voltage
η%
regulation
(%)
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
1.6
20.04
48.4
1.6
77.44
32.064
-0.2
41.41
2
20.05
48.3
1.7
82.11
40.1
-0.25
48.84
3
20.01
48.1
2
96.2
60.03
-0.05
62.4
4
20.02
47.9
2.3
110.17
80.08
-0.1
72.69
5
20
47.7
2.6
124.02
100
0
80.63
6
20.02
47.8
3
143.4
120.12
-0.1
83.77
7
20.01
47.7
3.4
162.18
140.07
-0.05
86.37
8
20.01
47.7
3.8
181.26
160.08
-0.05
88.32
9
19.99
47.8
4.2
200.76
179.91
0.05
89.62
9.55
19.98
47.8
4.4
210.32
190.809
0.1
90.72
Table. 3.4 Load regulation of ZVS push-pull converter
56
S. No.
IL
Vout
Vin
Iin
Pin
Pout
Output
Overall
voltage
η%
regulation
1.
2.
3.
4.
5.
9.55
19.98
39.73
5.3
210.569
190.809
0.1
90.62
9.55
19.98
42.1
5
210.5
190.809
0.1
90.65
9.55
19.98
43
4.96
213.28
190.809
0.1
89.46
9.55
19.97
46
4.7
216.2
190.7135
0.15
88.21
9.55
19.98
47.8
4.4
210.32
190.809
0.1
90.72
Table. 3.5 Line regulation of the ZVS push-pull converter
7
Fig. 3.44 Efficiency Vs load current
3.8 Losses in the ZVS push-pull converter
This section gives the distribution of various losses when the converter is loaded fully.
The various losses in the converter are calculated under full load. The input of the converter
is kept at 48V. From the table 3.6 it is seen that the major portion of the losses is because of
the secondary snubber and transformer. Using high frequency ferrite material better than N87
57
can minimize the transformer loss. As the energy associated with the secondary leakage
inductance is more the secondary snubber loss is also more. By using the technique
mentioned in the reference [17] secondary snubber loss can be reduced. The synchronous
rectifier losses can be still reduced by using low R ds (on) Mosfet.
Loss components
Estimated Losses (in W)
Power switching Mosfets
Conduction losses
1.47
Switching losses (Turn-off losses)
1.97
Extra switching Mosfets
Conduction losses
0.35
Switching losses
1.97
Primary additional diode losses
0.78
Secondary rectifier losses
2.38
Snubber losses
Secondary snubber
2.7
Primary snubber
0.69
Magnetics
Transformer losses
3.82
Leakage inductor
1.33
Output filter inductor losses
0.37
Total losses
Estimated
17.82
Measured
19.76
Table 3.6 Loss distributions in 200W ZVS push-pull converter
58
3.9 Conclusion
Complete analysis of the ZVS push-pull converter is taken up in this chapter.
Operation of the converter is explained by 6 different intervals. Equations determining each
interval are presented. Electrical equivalent circuit for each interval is presented. All the basic
intervals and its complimentary intervals are listed in a tabular column. Design procedure of
the converter is explained by a sample design for a converter rated 200W, 300kHz.
Parameters affecting the ZVS are explained. Simulation results and experimental results are
presented. Dynamic characteristics of the converter are presented.
59
CHAPTER 4
Analysis and Design of ZVS Half-Bridge Converter
4.1 Introduction
This chapter introduces the ZVS half-bridge converter. Operation of the circuit is
explained. Design procedure is presented. Simulation and experimental results are presented
to validate the design procedure.
Section 4.2 introduces the ZVS half-bridge converter. The idealized operation of the
proposed circuit is presented. Design procedure is explained in the section 4.3. Section 4.3
also gives the specification of the prototype ZVS half-bridge converter. Simulation and
experimental results are presented in section 4.4. Estimated and experimental loop gain
characteristics are presented in section 4.5.
4.2 Proposed Circuit and Operation
Fig. 4.1 shows the proposed ZVS half-bridge converter. This circuit is obtained from
the hard-switched half-bridge converter by connecting two switches (S3 & S4 ) and two
diodes (D3 & D4 ) as in fig. 4.1. The leakage inductance of the transformer is lumped on the
secondary side and represented as Llk in fig. 4.1. C1 and C2 are the snubber capacitors.
V
Td
g1
Vg
3
Vg2
Vg4
D Ts
D Ts
Fig. 4.1 ZVS half-bridge converter
60
Fig. 4.2 indicates the gate pulses Vg1 , Vg2 , Vg3 and Vg4 for the switches S1 , S2 ,
S3 and S4 respectively. S3 and S4 have a duty ratio of nearly 50% (with a small dead
time). The dead time (Td ) is also shown in Fig. 4.2.
I s1
Is3
Is 2
I D p &
I D n
I c1
Ic 2
t1
t0
t3
t2
t4
t5
Fig. 4.2 Control pulses
Idealized operation of the circuit is explained by a set of 6 intervals. Fig. 4.3 shows
the idealized waveforms of primary switch current, snubber capacitor current and secondary
diode currents.
I s1
I s3
Is2
I Dp & I Dn
I c1
Ic2
t0
t1
t
2
t3 t4
Fig. 4.3 Idealized waveforms
61
t5
The following are the assumptions made during the idealized analysis:
1. Switching devices are ideal.
2. Diodes are ideal.
3. Device output capacitance is neglected. Only the effect of snubber capacitor is
considered.
The notations Vp , Is1, Is2 , Vc1 and Vc2 used in the analysis throughout this chapter
are referred to fig. 4.1. The following are the symbols used in the analysis,
Im = Magnetizing current
n = Turns ratio
(IDn ∼ IDp )
n
IDn , IDp = Secondary rectifier current
Irefl = Reflected load current =
Interval T1 (t0 < t < t1)
In interval T1 , S1 and S3
are on. When S1 is conducting, diode D3 is reverse
biased in the primary circuit. In the secondary circuit diode D p is forward biased. This
interval is known as power transfer interval. During this interval power is transferred from
primary to secondary. The following equations are valid for this interval. Fig. 4.4 shows the
conduction path and fig. 4.5 shows the equivalent circuit for interval T1 .
Primary Circuit:
I p = I m + I refl
I refl =
(4.1)
( I Dp − I Dn )
n
(4.2)
Vc 2 = VDC
(4.3)
V
= DC
2
(4.4)
V
p
62
Secondary Circuit:
I Dp = I L ; I Dn = 0
(4.5)
VDC
dI
− Vo = ( L + Llk ) L
dt
2n
(4.6)
D2
VDC
2
S2
Dp
Llk
C2
L
Co
S4
VDC
2
D3
S3
D4
R
Vp I p
S1
C1
Llk
D1
Dn
Fig. 4.4 Conducting path in interval T1
L + Llk
VDC
2
Im
Lm
VDC
2n
IL
n
Co
Vo
R
Fig. 4.5 Equivalent circuit for interval T1
Interval T2 (t1 < t < t 2 )
Interval T2 begins when S1 is turned off. The snubber capacitor C1 assists the turn-
off process of S1 . As the turn-off process is capacitor assisted, the turn-off process is low loss
switching transition. The magnetizing current and reflected current charge C1 from 0 to
VDC
V
and discharge C2 from VDC to DC . Although S3 is on, D3 is still reverse biased
2
2
because the voltage VC1 has not reached to
VDC
.
2
63
In the secondary circuit D p takes the load current. This interval is known as resonant
transition-I interval. Fig. 4.6 shows the conduction path and fig. 4.7 shows the equivalent
circuit for interval T2 . The following equations are valid for this interval,
Primary circuit:
I p = I m + I refl ; Irefl =
I Dp − I Dn
n
(4.7)
dVc 2 I m + I refl
=
; C1 = C 2 = C
dt
2C
(4.8)
Vc1 (t ) = VDC − Vc 2 (t )
(4.9)
The initial conditions for this interval are,
Vc1 (t1 ) = 0;Vc 2 (t1 ) = VDC
This interval ends when VC1 reaches
(4.10)
VDC
and current commutates to S3 , D3 .
2
V
V
Vc1 (t2 ) = DC ;Vc 2 (t2 ) = DC
2
2
(4.11)
Secondary circuit:
Vsec ( t ) − Vo = ( L + Llk )
dI L
dt
( 4.12 )
VDC
− Vc1( t )
Vsec ( t ) = 2
n
( 4.13)
64
D2
S2
VDC
2
C2 I
p2
Dp
Llk
L
Co
VDC
2
D3
Ip
D4
S4
S3
R
C1 I p1
S1
Llk
D1
Dn
Fig. 4.6 Conducting path in interval T2
VDC
2
L + Llk
C2 = C
Im
VDC
2
Lm
IL
n
Vsec (t )
Co
Vo
R
C1 = C
Fig. 4.7 Equivalent circuit for interval T2
Interval T3 (t 2 < t < t 3 )
Interval T3 begins when C1 charged to
VDC
V
. As C1 charged to DC , D3 is
2
2
forward biased. The magnetizing current and reflected current Ip freewheel through S3 and
D3 . This interval is known as freewheeling interval. The leakage inductance Llk ensures
that only D n takes the load current. Fig. 4.8 shows the conduction path and fig. 4.9 shows
the equivalent circuit for interval T3 .
65
D2
VDC
2
Dp
Llk
C2
S2
L
CL
D4
S4
VDC
2
D3
S3
R
IP
S1
C1
Llk
D1
Dn
Fig. 4.8 Conducting path in interval T3
L + Llk
Lm
IL
n
Vo
Co
R
Fig. 4.9 Equivalent circuit for interval T3
Primary circuit:
Vp = 0
(4.14)
V
Vc1 = Vc 2 = DC
2
(4.15)
Secondary circuit:
−Vo = ( L + Llk )
dI L
dt
(4.16)
Interval T4 (t 3 < t < t 4 )
At the start (t = t 3 ) of this interval T4 , S3 is switched off. The magnetizing current
and reflected current charge C1 from
VDC
V
to VDC and discharge C2 from DC to 0.
2
2
This interval is known as resonant transition – II interval. From the equivalent circuit (fig.
4.11) it is seen that reflected current and magnetizing current discharges C2 . So magnetizing
inductance and leakage inductance has to be designed to discharge C2 . In the secondary
66
circuit the load current starts shifting from D p to D n . Fig. 4.10 shows the conduction path
and fig. 4.11 shows the equivalent circuit for interval T4 .
D2
S2
VDC
2
Llk
C2
Dp
L
Co
S4
VDC
2
D3
S3
D4
R
Ip
C1
S1
Llk
D1
Dn
Fig. 4.10 Conducting path in interval T4
VDC
2
L
C2 = C
Lm
Im
VDC
2
IL
n
Llk
Vsec ( t )
I Dn
C1 = C
Llk
Co
I Dp
Fig. 4.11 Equivalent circuit for interval T4
The equations valid for this interval are,
Primary circuit:
I p = I m + I refl ; Irefl =
I Dp − I Dn
n
(4.17)
dVc 2 I m + I refl
; C1 = C 2 = C
=
2C
dt
(4.18)
Vc1 (t ) = VDC − Vc 2 (t )
(4.19)
67
R
The initial conditions for this interval are,
V
V
Vc 2 (t3 ) = DC ;Vc1 (t3 ) = DC
2
2
(4.20)
This interval ends when VC1 reaches VDC and VC2 discharges fully.
Vc 2 (t 4 ) = 0;Vc1 (t4 ) = V DC
(4.21)
Secondary circuit:
V
Vc1( t ) − DC
2
Vsec ( t ) =
n
−Vsec ( t ) = Llk
Vsec (t ) = Llk
−Vo = L
( 4.22 )
dI Dp
( 4.23)
dt
dI Dn
dt
(4.24)
dI L
dt
(4.25)
Interval T5 (t 4 < t < t 5 )
Interval T5 begins when C2 is discharged fully. As C2 is discharged, the
magnetizing current and reflected load current forward biases D 2 . The magnetizing current
and reflected load current ( Ip ) flow through D 2 . When current is flowing through D 2 , S2
and S4 are turned on. Thus zero voltage switching of device S2 is achieved. This interval is
known as ZVS interval. When S2 is on D 4 is reverse biased in the primary circuit.
When the primary current direction changes its direction, S2 takes the current from
D 2 . Fig. 4.12 shows the conduction path in interval T5 . At the end of this interval D p
blocks fully and D n takes the full load current. The time of interval T5 is decided by the
leakage inductance. Fig. 4.12 shows the conduction path and fig. 4.13 shows the equivalent
circuit for interval T5 . The following are the equations determining this interval.
68
Primary circuit:
I p = I m + I refl
I refl =
(4.26)
( I Dp − I Dn )
n
(4.27)
V
V p = DC
2
(4.28)
Secondary circuit:
dI Dp
V
− DC = Llk
dt
2n
(4.29)
VDC
dI
= Llk Dn
2n
dt
(4.30)
−Vo = L
dI L
dt
(4.31)
D2
VDC
2
Llk
C2
S2
Dp
Co
Ip
S4
VDC
2
S3
S1
L
C1
Llk
D1
Fig. 4.12 Conducting path in interval T5
69
Dn
R
L + Llk
VDC
2
IL
n
Lm
Llk
VDC
2n
I Dn
Llk
Vo
Co
R
I Dp
Fig. 4.13 Equivalent circuit for interval T5
Interval T6 (t > t 5 )
This interval is known as power transfer interval. During this interval S2 and S4 are
on in the primary circuit. D4 is reverse biased in the primary circuit. Dn is forward biased
in the secondary circuit. Fig. 4.14 shows the conduction path and 4.15 shows the equivalent
circuit in interval T6 . This interval is followed by similar sets of intervals as before to
achieve ZVS for S1 .
Interval T6 is the complimentary interval of T1 . Each cycle consists of 10 intervals.
These are given in table 4.1. Table 4.2 gives the currents and voltages in the secondary
circuit.
Primary circuit:
I p = I m + I refl
I refl =
(4.32)
( I Dn − I Dp )
n
(4.33)
Vc1 = VDC
(4.34)
V
= DC
p
2
(4.35)
V
70
Secondary circuit:
Vsec − Vo = ( L + Llk )
dI L
dt
( 4.36 )
V
V sec = DC
2n
VDC
2
( 4.37 )
S2
Llk
C2
Dp
L
Co
S4
VDC
2
D1
S3
R
D2
S1
C1
Llk
Dn
Fig. 4.14 Conducting path in interval T6
L + Llk
VDC
2
Lm
IL
n
VDC
2n
Fig. 4.15 Equivalent circuit for interval T6
71
Co
Vo
R
Interval Conducting
Vc1
Vc2
Vp
Interval
devices
Intervals for S1
T1
S1
0
VDC
VDC
2
Power transfer
T2
C1 , C2
Vc1 (t)
Vc2 (t)
VDC
− Vc1 (t)
2
Resonant transition-I
T3
S3 , D3
VDC
2
VDC
2
0
Freewheeling
T4
C1, C2
Vc1 (t)
Vc2 (t)
VDC
− Vc1(t)
2
Resonant transition –II
T5
D 2 , S2
VDC
0
V
− DC
2
ZVS interval
Complimentary intervals for S2
T6
S2
VDC
0
V
− DC
2
Power transfer′
T7
C1 , C2
Vc1 (t)
Vc2 (t)
VDC
-Vc1(t)
2
Resonant transition-I′
T8
S4 , D 4
VDC
2
VDC
2
0
Freewheeling′
T9
C1 , C2
Vc1 (t)
Vc2 (t)
VDC
-Vc1(t)
2
Resonant transition –II′
T10
D1 , S1
0
VDC
VDC
2
ZVS interval′
Intervals for S1 (Next Cycle)
T1
S1
0
VDC
VDC
2
Power transfer
Table 4.1 Tabular columns showing the voltages in the primary circuit
(′ - Represents the intervals for the switch S2)
72
Interval Conducting
I Dp
I Dn
devices
Vsec
Slope of the Inductor (L)
(Secondary
current
voltage)
Intervals for S1
T1
Dp
IL
0
VDC
2n
 1 

 ( Vsec - Vo )
 L + Llk 
T2
Dp
IL
0
VDC
- Vc1 (t)
2
n
 1 

 ( Vsec - Vo )
 L + Llk 
T3
Dp
IL
0
0
 1 

 ( Vsec - Vo )
 L + Llk 
T4
Dp , Dn
IL - IDn (t)
IDn (t)
V
Vc1(t) − DC
2
n
V
− o
L
T5
Dp , Dn
IL - IDn (t)
IDn (t)
VDC
2n
V
− o
L
Complimentary intervals for S 2
T6
Dn
0
IL
VDC
2n
 1 

 ( Vsec - Vo )
 L + Llk 
T7
Dn
0
IL
 1 

 ( Vsec - Vo )
 L + Llk 
T8
Dn
0
IL
V
Vc1(t) − DC
2
n
0
T9
Dp , Dn
IL - IDn (t)
IDn (t)
T10
Dp , Dn
IL - IDn (t)
IDn (t)
VDC
− Vc1(t)
2
n
VDC
2n
 1 

 ( Vsec - Vo )
 L + Llk 
V
− o
L
V
− o
L
Intervals for S1 (Next cycle)
T1
Dp
IL
VDC
2n
0
 1 

 ( Vsec - Vo )
 L + Llk 
Table 4.2 Tabular column showing voltages and currents in the secondary
73
4.3 Designing for ZVS
4.3.1 Parameters affecting ZVS
As in ZVS push-pull converter magnetizing current, leakage inductance, time delay,
load current and device output capacitance are the parameters that affect ZVS in half-bridge
converter. Unlike ZVS push-pull converter leakage inductance of the primary also aids ZVS
in half-bridge converter. Hence the primary voltage waveforms are free from ringing.
4.3.2 Design Procedure
Design procedure is same as the push-pull converter. The basic equations to calculate
the delay and leakage inductance will vary from the push-pull converter. This section
presents the derivation of the essential equations.
C2 = C
C2 = C
VDC
2
VDC
2
⇒
C1 = C
Im
Lm
IL
n
VDC
2
VDC
2
Im
C1 = C
Lm || L*lk
Fig. 4.16 Equivalent circuit in the primary side during interval T4
The following equations are used to design the leakage inductance, magnetizing
inductance and time delay.
VDC = Vc1 + L
dI1
dt
(4.38)
VDC = Vc 2 + L
dI 2
dt
(4.39)
L 
L = Lm || L*lk ; L*lk =  lk 
 2n 2 
(4.40)
74
On solving,
1
t
2 LC
(4.41)
V
1
L
sin
VC1 (t ) = DC + i(0)
t
2
2C
2 LC
(4.42)
V
1
L
sin
VC 2 (t ) = DC − i (0)
t
2
2C
2 LC
(4.43)
I (t ) = i (0) cos
Equation 4.43 gives the condition to achieve ZVS. The condition is,
VDC
L
; i (0) = I m + I refl
≤ i (0)
2
2C
(4.44)
From 4.43 minimum time required discharge the effective capacitance can be
determined.
ϖ=
1
;
2 LC
( 4.45)
T = π 2 LC is the total time period .
∴the time taken to disch arg e the snubber capaci tan ceTd =
∴ Minimum time delay = π
LC
2
T
4
( 4.46 )
( 4.47 )
The design steps to be followed are same as the push-pull converter.
4.3.3 Specifications of a 300kHz / 640W Half-Bridge converter
This section presents the specifications and block diagram of the power supply.
Input voltage
170V
Output voltage
32V
Output power
640W
Switching frequency
300kHz
Closed loop bandwidth
20kHz
Table 4.3 Specification of the power supply
75
4.4 Simulation and Experimental results
4.4.1 Simulation results
The converter designed above is simulated using Saber. Simulation results and
experimental results are presented for the following operating point:
Input voltage, VDC = 170V
Output voltage, Vo = 32V
Output power, Po = 500W
Fig. 4.17 shows the voltage across the primary of the transformer and current through
the transformer. From the fig. 4.17 it is clear that during the switching on transition current
through the transformer and the voltage across it are of different polarities. This indicates that
the switches achieve ZVS during turn-on.
Fig. 4.17 Voltage across the transformer and the current through transformer
4.4.2 Experimental Results
Fig. 4.18 shows the control pulses for the switches S1 and S2 . The duty cycle of each
pulse is kept at 36%. The switching frequency is 300kHz.
76
Fig. 4.18 Control pulses for S1 and S2
(Ch-1 – Control pulse for S1 & Ch-4 control pulse for S2 )
Fig. 4.19 shows the control pulses for the switches S1 and S3 . Duty cycle of the
switch S1 is 36% and the duty cycle of the switch S3 is near to 50%, with dead time. As
discussed earlier switch S3 provides a freewheeling path in the primary when S1 is off.
77
Fig. 4.19 Control pulses for S1 and S3
(Ch-1 – Control pulse for S1 & Ch-2 control pulse for S3 )
Fig. 4.20 shows the control pulses for S2 and S4 . Duty cycle of the switch S2 is
36% and the duty cycle of the switch S4 is near to 50%, with dead time. As discussed earlier
switch S4 provides a freewheeling path in the primary when S2 is off.
78
Fig. 4.20 Control pulses for S2 and S4
(Ch-3 control pulse for S4 & Ch-4 Control pulse for S2 )
Fig. 4.21 shows the voltage across S1 and current through transformer.
Fig. 4.22 shows the voltage across S1 and current through the transformer at the
instant of ZVS. Fig. 4.22 shows the expanded time scale of fig. 4.21. From the fig. 4.22 it is
clear that the current through the transformer is negative just before the switch is turned on.
This indicates that the S1 achieve ZVS.
79
Fig. 4.21 Voltage across S1 and current through transformer
(Ch-1 voltage across S1 & Ch-2 current through transformer 10A/div.)
Fig. 4.22 voltage across S1 and current through transformer
(Ch-1 voltage across S1 & Ch-2 current through transformer 10A/div.)
80
Fig. 4.23 shows the voltage across S2 and current through transformer.
Fig. 4.24 shows the voltage across S2 and current through the transformer at the
instant of ZVS. Fig. 4.24 shows the expanded time scale of fig. 4.23. From the fig. 4.24 it is
clear that the current through the transformer is negative just before the switch is turned on.
This indicates that the S2 achieve ZVS.
Fig. 4.23 Voltage across S2 and current through transformer
(Ch-1 voltage across S2 & Ch-2 current through transformer 10A/div.)
81
Fig. 4.24 Voltage across S2 and current through transformer
(Ch-1 voltage across S2 & Ch-2 current through transformer 10A/div.)
Fig. 4.25 shows the voltage across the secondary diode D p . Additional inductance,
which is added to aid ZVS, oscillates with the junction capacitance of D p . From fig. 4.25 it
is seen that the peak of the ringing voltage goes almost twice the nominal voltage. This is a
disadvantage of the proposed topology. Fig. 4.26 shows the voltage across D n . As discussed
in the chapter 3 the technique proposed in the reference [17] can be used to feed back the
energy associated with ringing is fed back to the source instead of dissipating it in the
snubber circuits.
82
Fig. 4.25 Voltage across D p
Fig. 4.26 Voltage across D n
83
4.5 Dynamic analysis of ZVS half-bridge converter
The small signal dynamic model of half-bridge converter is similar to PWM
hard-switched converter. This is validated by measuring the loop gain characteristics of ZVS
half-bridge converter using network analyzer.
The closed loop design is similar to ZVS push-pull converter. Fig. 4.27 shows the
estimated and measured loop gain of half-bridge converter.
Fig. 4.27 Measured and estimated loop gain characteristics of half-bridge converter
4.6 Losses in the ZVS half-bridge converter
This section gives the distribution of various losses when the converter is 70% loaded.
The input voltage of the converter is kept at 165V. From the table 4.4 it is seen that the major
portion of the losses is because of the transformer, secondary rectifier and secondary
snubbers. Using high frequency ferrite material better than N67 can minimize the transformer
loss. Instead of diode rectifiers if synchronous rectifiers are used efficiency can be increased.
84
As the energy associated with the secondary leakage inductance is more, secondary snubber
loss is also more. By using the technique mentioned in the reference [17] secondary snubber
loss can be reduced.
Loss components
Estimated Losses (in W)
Power switching Mosfets
6.12
Conduction losses
4
Switching losses (Turn-off losses)
Extra switching Mosfets
1.4
Conduction losses
Switching losses
3
Primary additional diode losses
2
Secondary rectifier losses
14
Secondary snubber losses
5
Input capacitor ESR losses
1.2
Magnetics
Transformer losses
13
Leakage inductor
4.7
Output filter inductor losses
2.78
Total losses
Estimated
57.2
Measured
62.86
Table 4.4 Loss distributions in 200W ZVS push-pull converter
Fig. 4.28 shows the efficiency vs. load current. The converter achieves maximum
efficiency when it is 45% loaded. The ZVS limit is fixed at 12A.
85
Fig. 4.28 Efficiency Vs load current
4.7 Conclusion
Complete analysis of the ZVS half-bridge converter is taken up in this chapter.
Operation of the converter is explained by 6 different intervals. Equations determining each
interval are presented. Electrical equivalent circuit for each interval is presented. All the basic
intervals and its complimentary intervals are listed in a tabular column. Simulation results
and experimental results of a prototype converter rated for 300kHz, 640W converter is
presented. Measured and estimated loop gain characteristics of the converter are presented.
86
CHAPTER 5
CONCLUSION
The objective of the work is to develop improvised push-pull and half-bridge
converters suitable for soft switching. The improvised push-pull converter and half-bridge
converters use two additional switches and two diodes. The additional switches introduce
freewheeling intervals in the circuit and thus enable loss-less switching. In classical push-pull
and half-bridge converters, the transformer primary is left open during two sub-intervals in a
period. On account of this feature, the turn-on of the switch in these converters is always
hard. The new circuit topology converts these open circuit intervals into freewheeling
intervals with such a modification, all trapped energy in the core is conserved to achieve ZVS
during all the transition.
The following are the features are the new circuit,
•
Loss-less switching transition for all the switches employed.
•
Switch stress similar to hard-switched PWM converter.
•
Control and small signal behavior similar to hard-switched PWM converter.
•
ZVS range of the converter is dependent on the load current. In order to have wider
range of ZVS, additional inductance is added to the secondary of the transformer. The
inductance that is added to aid ZVS resonates with the junction capacitance of the
diode and produces ringing in the secondary voltage waveforms. This is a
disadvantage of this topology.
Based on the proposed topology prototypes of ZVS push-pull and ZVS half-bridge
converter are built.
ZVS push-pull converter rated 200W, 300kHz achieves an efficiency of 91%. As ZVS
push-pull converter uses synchronous rectifiers and soft switching technique the efficiency is
better by about 7% compared to hard switched push-pull converter. Bandwidth of the
converter is 30kHz.
87
ZVS half-bridge converter rated 640W, 300kHz achieves an efficiency of 85% at full
load. ZVS half-bridge converter efficiency is better by about 3.5% compared to hardswitched half-bridge converter. Bandwidth of the converter is 20kHz.
Loop gain characteristics of the push-pull and half-bridge converter are measured
using network analyzer to validate the model developed. An appendix has been devoted to
introduce the network analyzer. Applications of the network analyzer are also presented in
the appendix.
The contributions made in this thesis are,
1) A modified circuit topology capable of soft switching. The idea is applicable to pushpull and half-bridge converters. Idealized analysis and design methodology for the
proposed converters.
2) Use of synchronous rectifiers in the ZVS push-pull converter to achieve high
efficiency. It is interesting to see that the drives for the synchronous rectifier device are
practically the same as the additional switches.
3) Validation of the design through circuit simulation as well as prototypes - a 300kHz,
200W push-pull converter and a 300kHz, 640W half-bridge converter.
4) Evaluation of dynamic performance functions with network analyzer and closed loop
controller design.
The drawback of the proposed topology is the excessive ringing in the secondary side.
Future scope is to achieve soft transition for the secondary rectifiers.
88
REFERENCES
1. Philip T. Krein, “Elements of Power Electronics,” Oxford University Press, 1992.
2. Robert W. Erickson, “Fundamental of Power Electronics,” Chapman & hall, 1997.
3. Issa Batarseh, “Power Electronic Circuits,” Wiley International Edition, 2004
4. Vatche Vorperian, “Analysis of Resonant Converters,” Ph.D Thesis, California Institute
of Technology Pesadena, California, May 1984.
5. S. Freeland, R. D. Middlebrook, “ A Unified Analysis of Converters with Resonant Switches,”
IEEE Proc. Power Electronics Specialist Conf. 1987 Record, pp 20-30.
6. Ivo Barbi, J. C. O. Bolacell, D. C. Martins, and F. B. Libano, “Buck quasi-resonant converter
operating at constant frequency: Analysis, design, and experimentation,” IEEE Trans. on
Power Electronics, July 1990, pp 276–283.
7. Steigerwald, R. L. 'High-Frequency Resonant Transistor DC-DC Converters', IEEE
Trans. on Industrial Electronics, May 1984, pp 181-191.
8. Robert. L. Steigerwald, “ A Comparison of Half-Bridge Resonant Converter topologies,” IEEE
Trans. on Power Electronics, April 1988, pp 174-182.
9. Kwang-Hwa Liu, Ramesh Oruganti, Fred C. Y. Lee, “Quasi-Resonant ConvertersTopologies and Characteristics,” IEEE Trans. On Power Electronics, April 1987, pp 62- 71.
10. Claudio Manoel C. Duarte, Ivo Barbi, “ An Improved Family of ZVS-PWM ActiveClamping DC-to-DC Converters,” IEEE Trans. On Power Electronics, January 2002, pp 1-7.
11. Biju S. Nathan, “Analysis, Simulation And Design of Series Resonant Converter For High
Voltage Applications,” M.Sc (Engg) Thesis, Indian Institute of Science, India, December
1999.
89
12. Krishna Vasudevan, “Study of Quasi Resonant Converters,” M.E. Thesis, Indian Institute of
Science, India, January 1991.
13. A. Rajapandian, “A Constant Frequency Resonant Transition Converter,” M.Sc (Engg)
Thesis, Indian Institute of Science, India, August 1995.
14. Masahito Shoyama, Koosuke Harada, “Zero-Voltage-Switching Realized By Magnetizing
Current Of Transformer In Push-Pull DC-DC Converter,” IEEE-INTELEC, November 1991,
pp 640-647.
15. Bob Mammano, “Isolated Power Conversion: making the Case For Secondary-Side
Control,” www.ednmag.com, June 2001.
16. Bob Bell, “Introduction to Push-Pull and Cascaded Power Converter Topologies,”
ON-Line Seminars, www.national.com, July, 2003.
17. A. Rajapandian, “A Novel Configuration for Switched Mode Power Supplies”, Patent
Application No. 3437, Indian Institute of Science, May 1999.
18. N. Mohan, Undeland, Robbins, “Power Electronics: Converters, Applications and Design,”
John Wiley & Sons, 1995.
19. Abraham I. Pressman, “Switching Power Supply Design,” McGraw-Hill International
Editions, 1992.
20. V. Ramanarayanan, “Class notes: E6: 221 Switched mode power conversion,”
Department of Electrical Engineering, Indian Institute of Science, India.
21. “Ferrites And Accessories – Siemens Matsushita Components”, Data Book 1997.
22. “Mospower Applications”, Siliconix Incorporated, 1984.
90
APPENDIX
INTRODUCTION TO NETWORK ANALYSER AND ITS
APPLICATIONS
A.1 Introduction
This chapter introduces the network analyzer. Some of the popular network analyzers,
which are available in the market, are presented. Further this section introduces the AP
instruments model 200 parallel network analyzer. The features of the above model are
presented. Some of the applications of the network analyzer like characterization of inductor,
capacitor and transformer are explained. This section further explains the measurement of
performance functions such as input impedance, audio susceptibility, output impedance,
control voltage gain and control current gain of power supply. Measurement procedures are
validated with sample buck and boost converter. Loop gain measurement is explained in
detail. Loop gain measurement technique then employed to evaluate to push-pull converter
and half-bridge converter is presented in the thesis.
A.2 Network analyzer or Frequency response analyzer
Network analyzer or frequency response analyzer is used to measure the frequency
response of any electrical network. Fig. A.1 shows the block diagram of frequency response
analyzer. The frequency response analyzer consists of central processing unit and display
unit. The central processing unit consists of a source, two receivers and a mathematical
processing unit.
Operation of network analyzer
The source (or oscillator) outputs a test frequency, which is injected in the test circuit.
At the same frequency the two receivers measure the voltages of excitation signal ( VA ) and
response signal ( VB ) of the circuit. The mathematical processing unit calculates the ratio of
response signal ( VB ) to the excitation signal ( VA ). The frequency of the source is
incremented in discrete steps from the start to the stop frequency and the ratio is found out at
all points. The display device plots the gain vs. frequency graph. A dwell time should be
given at each point to allow the circuit to stabilize.
91
Central Processing unit
Source
Channel A
Channel B
Display device / PC
VA
Vsource
VB
To electrical network From electrical network
A-1 Block diagram of network analyzer
A.3 Requirements of a frequency response analyzer
A good frequency-response analyzer is a very specialized instrument, which has the
following features:
1. Operating frequency range from below 1 Hz to greater than 10 MHz.
2. Swept-sine output oscillator to drive circuit under test
3. Dual receiver channels to measure ratio of signals and phase shift of signals at the
frequency of the oscillator.
4. High noise rejection with selectable bandwidth of the receiver channels.
5. Direct interface to a computer for post-processing of data.
Some of the commonly available network analyzers are Hewlett Packard frequency
response analyzer (Model: HP4194A), AP instruments (Model: 200), Solartran frequency
response analyzer, Powertek frequency response analyzer (Model: GP102) and Venable
industries network analyzer. Features of AP instruments network analyzer (Model 200) and
its applications to characterize the power components and measurement small signal
parameters of power supplies are explained in this chapter.
92
A.4 Features of AP instruments network analyzer (Model 200 parallel
frequency response analyzer)
The Model 200 Frequency response analyzer system composed of an analog
source/receiver unit, a digital signal-processing (DSP) unit with parallel port connection and
software for a user provided IBM PC compatible computer. The following section presents
the features of source, receiver (Channel A and Channel B) and the software. The list of
accessories provided with the network analyzer is also presented.
Source
1) 11.6 mHz to 15 MHz range, 11.6 mHz resolution.
2) Output level adjustable in 1 dB steps from 1.25 mV to 1.77V rms.
3) 50 ohm output with current limiting.
4) Output can be DC offset up to +/- 10 V eliminating large coupling capacitors at low
measurement frequencies.
Receiver
1) Two channels for transfer function (B/A) measurements.
2) High selectivity two stage receiver architecture for high noise immunity.
3) Digital signal processing provides a user selectable IF bandwidth, optimizing noise
immunity and measurement speed.
4) Selectable AC ( >=10Hz ) or DC coupling with one megohm input impedance.
5) Inputs can be DC offset up to +/- 10 V facilitating DC coupled measurements.
Software
The software is a connectivity program between the network analyzer and PC. Main
function of the software is to control the network analyzer and to plot the acquired data from
the network analyzer. The software has 4 basic graph display modes.
They are
1) Magnitude and Phase
2) Absolute magnitude
3) Complex impedance
4) IEC 555-2
93
1. Magnitude and phase
The first display mode, magnitude and phase, graphs the ratioed measurement of
channel B divided by channel A. The magnitude represented is expressed in dB while the
phase is expressed in degrees. A positive value of magnitude indicates gain through the
network under test while a negative value of magnitude indicates attenuation.
2. Absolute magnitude
The second display mode, measures the absolute magnitude of channels A and B
displaying it in RMS volts. This mode is useful for diagnosing a noisy B/A measurement by
showing the actual (absolute) signal strength of each channel.
3. Complex impedance
The third display mode, measures the complex impedance of a network under test.
This method uses an external reference resistor connected to the network in a specific
manner. The reference resistor value is entered as a parameter in the software. The complex
impedance Z, can be displayed as one of the following:
i.
Real Z and imaginary Z
ii.
Magnitude and Phase of Z
iii.
Equivalent capacitance and resistance
iv.
Equivalent inductance and resistance
4. IEC 555-2
The fourth display mode graphs a plot of the first forty harmonics of the input signal.
The input signal frequency is user selectable as 50Hz or 60Hz.
Accessories
1) Injection isolator
2) Differential probes
3) Probes
1. Injection isolator
Injection isolator is a transformer with a wide range of operating frequency (11mHz
to 15MHz). It is used for coupling the oscillator (source) signal into the electrical network.
94
2. Differential probes
Differential probes are called as isolation probes. Two signals, which are at different
ground levels, can be measured using differential probes. Attenuation ratio of differential
probes can be set at 1:20 or 1:200. Two differential probes are provided with the network
analyzer.
3. Probes
Two probes are provided with the network analyzer. The attenuation ratio can be set
at 1:1 or 1:10.
A.5 Applications of network analyzer to find the frequency response of
circuit components
A.5.1 Frequency response of RC – circuit
Fig. A.2 shows the measurement setup for RC - circuit. The following are the steps to
be followed to find the frequency response of the RC - circuit.
Step: 1: The source of the network analyzer is used as the excitation signal for the RC
– circuit.
Step: 2: The channel – A is connected across the input of the circuit (excitation
signal).
Step: 3: The channel – B is connected to the output of the circuit (response signal).
Step: 4: The start frequency, stop frequency and dwell time are mentioned in the
software as per the requirements.
Step: 5: The display mode is kept at magnitude and phase. As earlier discussed this
mode plots the ratio of voltage measured by the channel B to the voltage
measured by the channel A.
1 

Voltage measured by the channel A, V A = I  R +

sC 

95
 1 
Voltage measured by the channel B, VB = I 

 sC 
VB
1
=
V A sCR + 1
Precautions:
If C is electrolytic capacitor, then DC bias should be given along with the AC signal.
Network analyzer
Source
Channel A
Channel B
R
C
Fig. A.2 Experimental setup for finding the frequency response of RC - circuit
Fig. A.3 shows the experimental results of an RC – circuit. The following are the
essential values.
R = 10k
C = 1n
Corner frequency =
1
= 15.9kHz
2π RC
From the fig. A.3 it is clear that phase starts from 0º to -90º (first order system). The
frequency corresponds to -45º represents the corner frequency and is 15kHz.
96
fc =
1
= 15kHz
2π RC
−45D
Fig. A.3 Experimental results of frequency response of RC - circuit
A.5.2 Characterization of circuit component
The circuit components like capacitor, inductor and transformer will have
various non-idealities. This section explains the measurement procedure for characterizing
the circuit components. Fig. A.4 shows the measurement setup. A 1Ω resistor is used as the
reference resistor, which is shown in fig. A.4. The following are the steps to be followed to
characterize any circuit component.
Step: 1: The source of the network analyzer is used as the excitation signal.
Step: 2: The channel – A is connected across the reference resistor.
Step: 3: The channel – B is connected across the component under test.
97
Step: 4: The start frequency, stop frequency and dwell time are mentioned in the
software as per the requirements.
Step: 5: The display mode is kept at magnitude and phase. As earlier discussed this
mode plots the ratio of voltage measured by the channel B to the voltage
measured by the channel A. The software plots the impedance vs. frequency
of the component, which is clear from the following equations.
Voltage measured by the channel A, V A = IR;
R = 1Ω
Voltage measured by the channel B, VB = IZ
V
∴ B =Z
VA
Precautions:
The grounds of channel 1 and channel 2 are not same. So differential probe
should be used.
Network analyzer
Source
Channel 1
Channel 2
Differential Pr obe
Z
Injection isolator
R = 1Ω
Fig. A.4 Experimental setup for characterizing any circuit component
98
The above measurement procedure is used to determine the non-idealities of the
circuit components like capacitor, inductor and transformer. The following section discusses
the non-idealities of the circuit components with experimental results.
1. Characterization of capacitor
Fig. A. 5 shows the various parasitic elements in the capacitor. In the fig. A.5, ESR
represents equivalent series resistance and ESL represents equivalent series inductance of the
capacitor C. Fig. A.6 shows the frequency response of the capacitor. The lower frequency
region fl the impedance is purely capacitive (C). In the mid-frequency f m region the
impedance is resistive (ESR). The high frequency region f h the impedance is inductive
impedance (ESL). So from this graph it is possible to find C, ESR and ESL of any capacitor.
C
ESR
ESL
Fig. A.5 Capacitor and its parasitics
fl
Capacitive
fh
fm
ESR
Inductive
Z
Frequency
Fig. A.6 Frequency response of a capacitor
Fig. A.7 shows the experimental results of 2 different capacitors. Both the capacitors
are of Alcon make and their values are 2.2µF (Polypropylene type) and 0.1µF (Polyester
type). From the experimental results the following are the points identified for the
polypropylene capacitor.
1) Up to 300kHz with the increase in frequency the impedance decreases. In this region
the nature of impedance is capacitive.
99
2) Between 300kHz and 500kHz the resonance occurs between capacitor and its lead
inductance. From this region it is possible to determine ESR. Polypropylene capacitor,
2.2µF has an ESR of 4.46mΩ.
3) Between 500kHz and 3MHz, the impedance increases with the increase in frequency.
In this region it is possible to determine the ESL of the capacitor.
4) Above 3MHz region it is difficult to identify the parasitics in the capacitor.
Similarly from the experimental results it is possible to identify C, ESR (12.5mΩ) and
ESL for the 0.1µF, polyester capacitor.
fc =
1
2π Lesl C
Fig. A.7 Frequency response of capacitor
2. Characterization of coil
Fig. A. 8 shows the various parasitic elements of a coil. In the fig. A.5 ESR represents
equivalent series resistance and C w represents the winding capacitance of the coil L. Fig.
100
A.9 shows the estimated frequency response of the coil. The lower frequency region f l the
impedance is purely resistive (ESR). In the mid-frequency f m region the impedance is
inductive (L). The high frequency region f h the impedance is capacitive impedance ( C w ).
The frequency at which winding capacitance ( C w ) and the coil resonates is represented as
f r in fig. A.9. So from this graph it is possible to find L, ESR and C w of any coil. Fig. A.7
shows the experimental results of a coil.
L
ESR
Cw
fl
fm
ESR
Inductive
fr
fh
Capacitive
Z
Frequency
Fig. A.8 Coil and its parasitics
Fig. A.9 Frequency response of a coil
Fig. A.10 shows the frequency response of an inductor of value 1mH. From the fig.
A.10 for frequencies less than 100Hz, the impedance is resistive (ESR). For frequencies
100Hz to 200kHz, the impedance is inductive. The resonance occurring at 500kHz is because
of winding capacitance and inductance. Above 600kHz, the impedance is capacitive (winding
capacitance)
101
R
fc = e sr
2π L
fc =
1
2π Lesl C
45D
Fig. A.10 Frequency response of an inductor
3. Characterization of transformer
Fig. A. 11 shows the various parasitic elements of a transformer. The following are
the non-idealities of the transformer,
1) Magnetizing inductance ( L m )
2) Leakage inductance ( Llk )
3) Winding capacitance ( C w )
4) Resistance component of the transformer ( R l )
The estimated frequency response of a transformer is shown in fig. A.12.
1) In the lower frequency region ( f1 ), the impedance of the transformer constant. This
indicates that the impedance offered is purely resistive ( R l ), which is clear from the
fig. A.12.
102
2) In the frequency region ( f 2 ), the impedance offered by the transformer increases with
the frequency. This indicates that impedance offered is inductive ( L m + Ll ).
3) If the frequency is further increased the winding capacitance ( C w ) of the transformer
resonates with the magnetizing inductance ( L m ). This resonant frequency is
represented as f r1 .
4) In the frequency region ( f3 ), the impedance offered by the transformer decreases with
the increase in frequency. This indicates that the impedance offered is capacitive
( C w ).
5) If the frequency is further increased the winding capacitance resonates with the
leakage inductance and the resonant frequency is represented as f r2 .
6) It is assumed that the winding capacitance ( Cw ) and resistance ( R l ) of the winding
are concentrated. Practically C w and R l are distributed parameters. So it is difficult
to separate out the non-idealities in this region.
Rl
Ll
Lm
Cw
Fig. A.11 Transformer and its parasitics
f1
f2
f r1
fr 2
f3
f4
Z
Frequency
Fig. A.12 Frequency response of transformer
103
Fig. A.13 shows the experimental frequency response of a HV transformer. The
resonance f r1 and f r2 are mentioned in the fig. A.13. For a HV transformer leakage
inductance and winding capacitance are high. So it is possible to identify the entire frequency
region.
f r1 =
1
2π Lm Cw
Fig. A.13 Frequency response of a HV transformer
104
fr 2 =
1
2π Ll Cw
A.6 Applications of network analyzer to find the performance functions of
power supplies
The objective of measuring the performance functions is to verify the small signal
analytical models developed for the power supply. To determine the performance functions
of the power supply it is necessary to perturb the various inputs of the power supply. There
are some standard procedures that are available to perturb voltage, current and duty cycle.
The following section explains the procedure to perturb voltage, current and duty cycle of the
power supply.
1. Perturbation of voltage
Fig. A.14 shows the block diagram representation of introducing perturbation in the
voltage. In fig. A.14, V represents the voltage to be perturbed and Vinj shows the perturbing
voltage. From the block diagram it is clear that by adding the perturbing voltage Vinj it is
possible to introduce disturbance in the required voltage (V).
Vinj
t
+
V
+
V + Vinj
V + Vinj
V
t
t
Fig. A.14 Block diagram representation of introducing a disturbance in a voltage
Fig. A.15 shows the various circuits to introduce a perturbation in the voltage. The
rule to be followed while perturbing any voltage is that the injected voltage is connected in
series.
105
Source of the network analyzer has a 50Ω current limit resistor. So the circuit shown
in fig.A.15 – (a) cannot be used for power supplies where the current (I) through the voltage
source (V) is high. Further the source of the network analyzer is not isolated for the circuit
shown in fig.A.15 - (a).
The network analyzer is isolated through injection isolator in the circuit shown in fig.
A.15 – (b). As injection isolator is rated for 0.5A, the circuit in fig. A.15 - (b) cannot be used
for the power supplies if the current (I) through the voltage source (V) is above 0.5A.
I
Vinj
I
I
V + Vinj
V + Vinj
Vinj
V + Vinj
V
Vinj
V
V
(a)
(b)
(c)
Fig. A.15 Circuits used to introduce perturbation in the voltage
Fig. A.15 – (c) is a better circuit to introduce perturbation in the voltage. Circuit in
fig. A.15- (c) can be used even when the current through voltage source (V) is high. The
Mosfet shown in fig.A.15 - (c) is operating in active region. From fig. A.16 it is clear that any
change in gate to source voltage of the Mosfet affects drain current and drain to source
voltage along the load line. So this circuit can be used to introduce the disturbance in voltage.
It is to be noted that the voltage injected has both DC (undesired) and AC (desired)
components.
106
Load line
Id
Vgs 2
Vgs 2
Vgs1
Vds
Fig. A.16 Mosfet characteristics
2. Perturbation of current
Fig. A.17 shows the block diagram representation of introducing a perturbation in the
current. In fig. A.17, I represents the current to be perturbed and Iinj shows the perturbing
current.
Iinj
t
+
I
+
I + Iinj
I + Iinj
I
t
t
Fig. A.17 Block diagram representation of introducing a disturbance in a current
Circuits shown in fig. A.18 are used to introduce perturbation in current. The circuits
shown in fig. A.18 are the dual of the circuits used for introducing perturbation in voltage.
107
The source of network analyzer is not isolated for the circuit in fig. A.18 - (a). The
circuit shown in fig. A.18 – (b) the network analyzer is isolated and can be used for low
power circuits.
The circuit in fig. A.18 – (c) uses an active device. The circuit in fig. A.18 – (c) is
used for higher power where a larger signal injection level is needed.
I
I + Iinj
Iinj
I
Iinj
I + Iinj
I
I + Iinj
Iinj
V
V
V
Vinj
Vinj
(a)
(b)
(c)
Fig. A.18 Circuits used to introduce perturbation in the current
3. Perturbation in duty cycle
In PWM converters the duty cycle is generated by comparing ramp voltage and
constant DC voltage. Fig. A. 19 shows the block diagram of PWM converter. In the fig. A.19
Vramp represents the ramp voltage and Vcont represents the control voltage. From the fig.
A.19 it is clear that by changing the control voltage it is possible to change the duty cycle.
Vcont
Vcont
t
−
+
Vramp
Duty cycle
Duty cycle
Vramp
t
t
Fig. A.19 Block diagram of the PWM converter
108
To introduce the perturbation in duty cycle it is required to introduce the perturbation
in control voltage. Fig. A.20 shows the block diagram representation of introducing
perturbation in the duty cycle. The circuit employed is similar to voltage injection as in fig.
A-15- (b).
Vinj
t
+
Vcont
+
Vcont + Vinj
Vcont
Vcont + Vinj
t
t
−
Vramp
+
Duty cycle
Vramp
Duty cycle
t
t
Fig. A.20 Block diagram representation of introducing perturbation in the duty cycle
A.6.1 Small signal analysis of buck converter
This section explains the measurement technique to measure the performance
functions of buck converter.
The following are the details of the buck converter,
Input voltage, VDC = 12V
Output voltage, Vo = 5V
Output filter inductor, L = 300µH
Output filter capacitor, C = 100µF
109
Fig. A.21 shows the buck converter.
300 µ H
D = 50%
Vo
L
R
5Ω
C
100 µ F
VDC = 12V
Fig. A.21 Buck converter
1. Measurement of audio susceptibility
The audio susceptibility of the converter quantifies the amount of input voltage
variations that will reach the output voltage. The audio susceptibility is a function of
frequency. To measure the audio susceptibility the perturbation is introduced in the input
voltage of the power supply and its effect is observed in the output voltage. Fig. A.22 shows
the voltage injection point and measurement points for measuring audio susceptibility of buck
converter.
VDS
L
Channel A
(VDC + VDS )
Vo + Vo
C
Vinj
Fig. A.22 Buck converter audio susceptibility measurement setup
110
R Channel B
In buck converter the audio susceptibility is of the form,
Vo ( s )
D
=
Vg ( s ) 1 + s L + s 2 LC
R
( A.1)
In the equation A. 1 the non-idealities like ESR of the capacitor, source resistance and
resistance of the inductor are not included.
Fig. A.23 shows the experimental and estimated characteristics of audio
susceptibility. The second order pole because of the LC - filter is around 1kHz and is
mentioned in the fig. A.23. The ESR of the filter capacitor is a non-ideality and its value is
0.2Ω. The ESR of the capacitor introduces a zero in the audio susceptibility transfer function.
It also mentioned in the fig. A.23.
f LC = 1kHz
f z,esr = 8kHz
Fig. A.23 Buck converter audio susceptibility estimated and measurement results
111
2. Measurement of input admittance
Input admittance of the converter relates how the converter interfaces with the source.
To measure the input admittance the disturbance is introduced in the input voltage and its
effect is seen in the input current. Input current is measured through Hall effect current
sensor. Fig. A.24 shows the buck converter input admittance signal injection and
measurement points.
L
VDC
Channel A
Vo
C
R
Vinj
Channel B( Input current )
Fig. A.24 Buck converter input admittance measurement setup
In buck converter the input admittance is of the form,
Ig (s)
D 2 (1 + sCR )
=
L
Vg ( s )


R  1 + s + s 2 LC 
R


( A.2 )
The various non-idealities of the converter are not in the equation A. 2. Fig. A.25
shows the experimental and estimated characteristics of input admittance. The zero because
of C and R (load resistance) is 0.3kHz and is mentioned in the fig. A.25. The second order
pole because of the LC - filter is around 1kHz and is mentioned in the fig. A.25.
112
f RC = 0.3kHz
f LC = 1kHz
Fig. A.25 Buck converter input admittance estimated and measurement results
3. Measurement of output impedance
The output impedance relates the capacity of the converter to cater dynamic loads. To
measure the output impedance a disturbance is introduced in the output load current and its
effect is observed in the output voltage. Buck converter output impedance is of the form,
Vo ( s )
sL
=
L
Iz (s) 
2 
 1 + s + s LC 
R


( A.3)
Fig. A.26 output impedance signal injection and measurement points for the buck
converter. A 1Ω resistor is used to measure the injected current.
113
L
Vo
Cinj
VDC
C
Channel B
R
Vinj
1Ω
Channel A
Fig. A.26 Buck converter output impedance measurement setup
f LC = 1kHz
Fig. A.27 Buck converter output impedance estimated and measurement results
114
4. Measurement of control voltage gain
The control voltage gain transfer function relates the output voltage and the control
duty ratio. To measure the control voltage gain perturbation is introduced in the duty cycle
and its effect is seen in the output voltage.
The control voltage gain of the buck converter is of the form,
Vg
Vo ( s )
=
L
d (s) 
2 
 1 + s + s LC 
R


( A.4 )
In PWM controller, comparing the control voltage with a ramp voltage produces duty
cycle. As discussed earlier to perturb the duty cycle perturbation is introduced in the control
voltage.
The following equations explain the control voltage gain measurement.
Vo ( s )
Control voltage gain = d (s)
( A.5 )
Vo ( s ) Vc ( s )
Control voltage gain = × Vc ( s ) d( s )
( A.6 )
In the equation A.6,
Vo ( s )
= Transfer function of output voltageto control voltage
Vc ( s )
and
Vc ( s )
= PWM gain
d( s )
 Vo ( s ) 
Step: 1 - Measurement of output voltage to control voltage ratio   V ( s ) 
 c

The transfer function between the output voltage and control voltage is measured in
the step: 1. Fig. A.28 shows the voltage injection point and measurement points for the step:
1.
115
L
Vo
C
VDC
R Channel B
Vinj
PWM controller
−
+
Vcont
Channel A
Vramp
Fig. A.28 Buck converter output voltage to control voltage transfer function measurement setup
Step: 2 – PWM gain measurement
PWM controller gain is calculated in the step: 2. The equation A.7 is used to calculate
the PWM gain.
Vc
V − VH
= L
d
DL − DH
( A.7 )
In the equation A.7, DL and D H are the duty cycle in (%), and the corresponding
control voltages are VL and VH . Fig. A.29 shows the variation of the duty cycle with the
control voltage.
116
Duty cycle(%)
DH
DL
VL
VH
Control voltage(Vc )
Fig. A.29 Variation of duty cycle with control voltage
Fig. A.30 shows the experimental and estimated results of control voltage gain
characteristics. The second order pole because of output LC filter is 1kHz is mentioned in the
fig. A.30. ESR zero is around 8kHz, is mentioned in the fig. A.30.
f LC = 1kHz f z,esr = 8kHz
Fig. A.30 Buck converter control voltage gain estimated and measurement results
117
5. Measurement of control current gain
The control current gain transfer function relates the control duty ratio and the input
current. To measure the control voltage gain perturbation is introduced in the duty cycle and
its effect is seen in the input current.
Control current gain transfer function is of the form,
I g ( s ) DVg
=
+
R
d (s)
DVg (1 + sCR )
L


R 1 + s + s 2 LC 
R


( A.8)
The following equations explain the control voltage gain measurement.
Ig (s)
Control current gain = d (s)
( A.9 )
I g ( s ) Vc ( s )
Control current gain = × Vc ( s ) d( s )
( A.10 )
In the equation A.10,
Ig (s)
= Transfer function of input current to control voltage
Vc ( s )
and
Vc ( s )
= PWM gain
d( s )
Like control voltage gain transfer function, control current gain transfer function is
also measured in 2 steps. In the step: 1, the transfer function between input current and
control voltage is measured.
In the step: 2, the PWM gain is calculated.
118
 Ig (s) 
Step: 1 - Measurement of output voltage to control current ratio  
 Vc ( s ) 


The transfer function between the input current and control voltage is measured in the
step: 1. Fig. A.31 shows the voltage injection point and measurement point for the step: 1.
The input current is measured using a Hall effect current sensor.
L
Vo
C
VDC
R
Vinj
PWM controller
−
+
Vcont
Channel B
Channel A
Vramp
Fig. A.31 Buck converter input current to control voltage transfer function measurement setup
Step: 2 PWM gain measurement
This is measured as explained in the previous section.
Fig. A.32 shows the estimated and experimental results of control current transfer
function.
119
f LC = 1kHz
Fig. A.32 Buck converter control current gain estimated and measurement results
A.6.1 Small signal analysis of boost converter
This section presents the estimated and measurement results of performance
functions of boost converter. The measurement procedures for measuring various
performance functions are same as the procedures used for buck converter. Fig. A.21 shows
the boost converter.
The following are the details of the boost converter,
Input voltage, VDC = 12V
Output voltage, Vo = 24V
Output filter inductor, L = 1mH
Output filter capacitor, C = 100µF
120
D = 50%
L
Vo
1mH
C
100 µ F
VDC = 12V
R
100Ω
Fig. A.33 Boost converter
1. Measurement of audio susceptibility
The transfer function of audio susceptibility of boost converter is of the form,
Vo
1
=
Vin (1 − D )( Ds )
where,Ds = 1 +
sL
R (1 − D )2
+ s2
LC
(1 − D )2
Fig. A.22 shows the measurement and experimental results of audio susceptibility of
boost converter.
Fig. A.34 Boost converter audio susceptibility estimated and measurement results
121
2. Measurement of input admittance
The transfer function of input admittance of boost converter is of the form,
Vo
1 + sCR
=
Vin R (1 − D )2 ( D )
s
where,Ds = 1 +
sL
R (1 − D )2
+ s2
LC
(1 − D )2
Fig. A.23 shows the measurement and experimental results of input admittance of
boost converter.
Fig. A.35 Boost converter input admittance estimated and measurement results
122
3. Measurement of output impedance
The transfer function of output impedance of boost converter is of the form,
Vo
sL
=
Vin (1 − D )2 ( D )
s
where,Ds = 1 +
sL
R (1 − D )2
+ s2
LC
(1 − D )2
Fig. A.24 shows the measurement and experimental results of output impedance of
boost converter.
Fig. A.36 Boost converter output impedance estimated and measurement results
123
4. Measurement of control voltage gain
The transfer function of control voltage gain of boost converter is of the form,
L

1− s
Vg 
R (1 − D )2
Vo
=

Ds
d
(1 − D )2 


where,Ds = 1 +
sL
R (1 − D )2
+ s2







LC
(1 − D )2
Fig. A.25 shows the measurement and experimental results of control voltage gain of
boost converter.
Fig. A.37 Boost converter control voltage estimated and measurement results
124
5. Measurement of control current gain
The transfer function of control current gain of boost converter is of the form,
Vo Vg ( 2 + sCR )
=
d
R (1 − D )3 Ds
where,Ds = 1 +
sL
R (1 − D )2
+ s2
LC
(1 − D )2
Fig. A.26 shows the measurement and experimental results of control current gain of
boost converter.
Fig. A.38 Boost converter control current estimated and measurement results
125
A.7 Loop gain measurement technique
Every control loop should be properly designed and validated before shipping a power
supply. This section explains the loop gain measurement technique of the power supply. The
block diagram shown in the fig. A.39 represent power supply.
Vin
+
Vo
Power supply ( G )
−
V fb
Feed back ( H )
Fig. A.39 Power supply block diagram
In fig. A. 39,
Power supply transfer function = G
Feedback transfer function = H
Loop gain transfer function = GH
To measure loop gain of the power supply, it is required to inject the perturbation
signal in the loop and allowing the perturbation signal to travel throughout the loop. Fig. A.
40 shows the block diagram representation of measurement of loop gain and measurement
points are also shown in the fig. A. 40.
Vin
+
Power supply ( G )
−
Vo
V fb
Feed back ( H )
+
Channel A
+
Vinj Channel B
Fig. A.40 Block diagram of loop gain measurement setup
126
Fig. A. 41 shows a typical block diagram of isolated power supply. The perturbation
signal (Vinj ) is injected through the injection isolator and the measurement points are shown
in the fig. A. 41.
Vin
+
Vo
Powerstage
−
Error amplifier
PWM controller
Optocoupler
Vinj
3
2
1
4
Fig. A.41 Power supply block diagram
Without changing the voltage injection it is possible to measure various parameters.
Table A.1 shows the voltage measurement points for the channel A and channel B.
Channel A
Channel B
Measuring Parameter
1
2
Loop gain
3
2
Compensation network gain (Error amplifier)
1
4
Control voltage gain
4
3
Voltage sensor gain
Table A. 1 Measurement points and measuring parameter
Hints for successful loop gain measurement
1) It is strongly advised to avoid the usage of differential probes. In the case of isolated
power supplies if possible it is advised to short the ground of secondary, primary and
control circuitry.
127
2) When measuring switching power supplies, use the lowest bandwidth for the best
noise rejection. For a faster sweep speed, use a higher bandwidth receiver setting.
3) Loop measurements above 30 kHz can be very difficult due to instrument grounding
and high frequency cross talk between cables on injected and return channels. This is
true of any network analyzer, and great care must be taken if you want to extend
measurements beyond this frequency.
4) Inject the signal into a low-ripple part of the circuit if at all possible.
5) It is not required to operate the converter at its full operating condition while
measuring the loop gain. By trail and error procedure it is possible to find the suitable
operating point and measurement can be done.
Experimental and estimated results of loop gain for the push-pull converter and halfbridge converter is presented in the Chapter 3 and Chapter 4 of this thesis respectively.
128