Radiation hard design
in CMOS image sensors
Bart Dierickx, Caeleste
CPIX Workshop 15-17 sept 2014, Bonn
Outline
• Introduction
• Design for total dose
Total ionizon dose TID
Displacement damage DD
• Design for single events
SEU single event upset
SEL single event latch-up
• Take home message
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radhard design in CMOS image sensors
2
Introduction
TID total ionizing dose
DD displacement damage
SEU single event [upset...]
SEL single event latch-up
Take home message
Introduction
About us
Background in Radhard CMOS design
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3
About us
Founded 2006
Mechelen, Belgium
17p
Mission
and business model
Supplier of
Custom designed
Beyond “State of the Art”
Image sensors
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radhard design in CMOS image sensors
space
X-ray
scientific
TOF
no
specialties
category
4
Caeleste radhard background
Where we come from
Historical contribution to radhard and cryo design for space
(ISOPHOT..., OISL, STAR250, HAS...)
Background in design for particle physics and X-ray
integrating and photon counting detectors
Close relationships with foundry technologists
Expertise in circuit & device physics & technology
Present
Routine radhard design (TID, TnID, SE, SEL)
Proton & SE hard pixels
ROICs and image sensors
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Heritage
OISL 2000
first >10Mrad
QX 2010
Analog domain 2-energy
“color” X-ray photon
counting
1989
1992
XYW event detector RD-19 SOI-CMOS
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ISOPHOT FIR ROIC 1989
SEU hard wo TR
2013 wafer scale X-ray
radhard design in CMOS image sensors
STAR250/1000 2003
6
Disclaimer
• This paper focuses on design countermeasures,
while understanding the damage mechanism itself
• This is not a design course. Details of actual
designs are not shown
• Technology countermeasures, temperature effects,
annealing not treated
• No guarantee on effectiveness of techniques, nor of
IP freedom
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Introduction
TID total ionizing dose
DD displacement damage
SEU single event [upset...]
SEL single event latch-up
Take home message
TID
total ionizing dose
also referred to as IEL ionizing energy
loss
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TID
Radiation:
Primarily X, γ, but essentially all particles
Dominant effect :
Creation of positive space charge in the SiO2 (SiN) dielectric
layers
Also: increase of interface states at Si-SiO2 interface
Effect on CMOS circuits:
 Moderate shift of Vth, μ degradation and 1/f noise increase
 Parasitic S-D leakage via STI/field in nMOSFETs resulting
in large dissipation and malfunction
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TID
Effect on CMOS pixels:
 Moderate offset shift and 1/f noise increase
 Lateral shunting between pixels
 Lower gain and increased PRNU
 Increased average Idark and DNSU
Most publications are describing this last effect
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Design countermeasures
• Buried diodes as the general way to reduce
dark current
• Avoiding the parasitic source-drain leakage in
nMOSFETs
• Several case-by-case other measures
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TID-hard CMOS
Regular transistor
Leaks when STI/field
inverts
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Annular transistor:
No path over STI/field
radhard design in CMOS image sensors
H-gate transistor:
Leakage path over STI/field
is blocked by P-implant
12
The “CES” IR ROIC
Fully radhard & cryo77K
UMC018
Digital: DARE library
Analog: CaelesteRH
>>1Mrad, not tested yet
ESA consortium
Caeleste+Easics+Selex
2014
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4 SAR ADCs, detail
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Digital logic, detail
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Caeleste RH library
CaelesteRH as compared to SotA
Available in 3 technologies, porting is
standardized
Full analog & mixed mode
Very high TID & TnID hardness
Very high SEL hardness
Very high SEU hardness wo TR
<20% increased Cin and power
<50% area increase
Normal
Caeleste
mixed
mode
Caeleste RH
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TID Gamma
Radhard pixels
LAP2010 device
TID of
gamma 60Co
Idark [e-/s]
Gamma TID
Tower TSL018
2011
10000
1000
Compared to
published SotA
10
TID [kGy]
0.01
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100000
0.1
2009innocent1
2009innocent2
2009innocent (HAS)
2000bogaert/dierickx
2002dierickx (STAR250)
LAP default
LAP DS
LAP DX
LAP XS 100
100
10
1
1
radhard design in CMOS image
sensors
10
100
1000
17
TID Gamma ≠ Electrons
LAP2010 device
factor increase Idark []
100
Tower TSL018
10 devices; many pixels per
device
TID of
• 300keV
electrons
• 1.2/1.3 MeV
gamma 60Co
1E+08
Silicon
1E+07
10
e-/H+/α range or photon absorption [µm]
1E+06
1E+05
e- PPD
1E+04
e- FD
1E+03
γ PPD
1E+02
γ FD
1E+01
electrons
1
protons
1E+00
0
1E-01
1E-02
1E+03
10
20
1E+04
1E+05
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20141E+06
photons
30
1E+07
40alpha
50
60
[kRad
70 Si]
radhard
1E+09 design
1E+10 in CMOS image sensors
1E+08
initial energy [eV]
80
Effect on
• Buried PPD
• Surface FD
18
DD
displacement
damage
Introduction
TID total ionizing dose
DD displacement damage
SEU single event [upset...]
SEL single event latch-up
Take home message
also referred to as “NIEL”
non-ionizing energy loss
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DD
Radiation:
HE particles: protons and heavier
Dominant effect :
Non-elastic displacement of Si atoms
Often creating an initial vacancy+interstitial
Effect on CMOS pixels:
 Point-wise heavily leaking diodes, hot pixels
 Often blinking “RTS” dark current pixels
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Photodiode redundancy?
Proton/Neutron/other_particle
 displacement damage in the photodiode creates “hot” or
“RTS” pixel
SE creates flash
No way to remove or calibrate this?
Suppose we split the pixel in 2...100 parts. The defect will
reside in only one
Redundancy?
 Readout all, remove the defect part’s signal and average.
 Take a weighted maximum voltage by winner take all circuit or
sourcefollower
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confidential
21
Photodiode redundancy
RESET
RESET
SELECT
SELECT
PPD/2
PPD/2
FD/2
FD
TG
PPD
FD/2
TG
RESET
Column
Column
PPD/2
US patent US8426828
Introduction
TID total ionizing dose
DD displacement damage
SEU single event [upset...]
SEL single event latch-up
Take home message
SEU
single event [upset]
Also SEE, SEFI, SET, SEGR, SEB ... ()
SEL is separately treated
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SEU
Radiation
Sometimes X, γ, e-, but rather much heavier
particles
Dominant effect :
Creation of instantanous + or – charge packet
sufficient to toggle a latch
Effect on CMOS and CMOS pixels:
 register or memory loosing information
 flash seen by the photodiode
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SEU
The loss of bits in SRAM cells or Flip-flops
electrons
1
1 0
0
0
0
1
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SEU
Mechanism
• Particle deposited charge packet charges one
node of a latch to the oppisite logic value
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Flipping the invertor @t0
3.3V
VDD
VSS
+++++++++3.3V
+++++++++++++-
0V
Flipping the invertor @t0+0.5ns
3.3V
VDD
VSS
2V
+
- -- - -
3.3V
+
++ +
+-
+
+-
+ +
+-
+
-
Hole drift/diffusion
Electrons drift/diffusion
SEU countermeasures
•
•
•
•
•
Shield against particles
Make vulnerable volume small
Make vulnerable node capacitance large
Triple (and other froms of) redundancy
Detectability, read-back, re-upload
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Introduction
TID total ionizing dose
DD displacement damage
SEU single event [upset...]
SEL single event latch-up
Take home message
SEL
single event latch-up
SEL
SEL
Radiation
Protons and rather even heavier particles
Dominant effect :
Creation of instantanous + or – charge packet
sufficient to initiate a PNPN latch-up
Effect on CMOS:
 Circuit collapsing and potential destruction due to
excessive supply current
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Bulk CMOS has an annoying
thyristor
VDD
VSS
0
3.3
...
...
3.3
0
NPN
PNP
Bulk CMOS has an annoying
thyristor
VDD
VSS
0
3.3
...
...
2.5
0.8
NPN
PNP
Attention: these two
resistors are physically
partly the same
This external element
model is imperfect!
Thyristor = 2 * BJT
VSS
 NPN
VDD
Q
PNP
 Threshold for ignition: Q, C
 Conditions for sustaining: , R
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Modeling SEL
Quantitative compact (=SPICE) model?
 Much better: a 3D device simulator.
What lacks: value for series resistances
 Series resistances in E, B, C. Can estimate it from techology data.
 Pay attention that “resistance” applies to majority carriers. Base
resistance is thus over/underestimated and partly uncorrelated
 Emitter and Base resistances partly overlap: Emitter current increases
IR drop of Base.
What lacks: models of the parasitic BJTs
 : must eventually “measure” that. Start with default value (100...1000)
for “qualitative” estimate.
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Design countermeasures
Avoid ignition
 minimize sensitive volume
 maximize C/Q: increase node capacitances
Avoid sustaining
 Maximally reduce the series resistance in the thyristor
 Between the nWELL and pWELL: guard rings metallically tied to VDD/VSS
Avoid proliferation
 nWELLs (actually the well not being the substrate) should be fragmented. So
that the latchup remains confined: when one section latches, the general
supply voltage does not collapse.
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Design style
Classic CMOS
design style
VDD=nWELL
Metal guardring
around wells
Rails in the middle
VDD=nWELL
VSS=substrate
VDD=nWELL
VSS=substrate
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radhard design in CMOS image sensors
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VDD=nWELL
VSS=substrate
VDD=nWELL
VSS=substrate
VDD=nWELL
VDD=nWELL
VSS=substrate
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VSS=substrate
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radhard design in CMOS image sensors
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Technology measures
Avoid the thyristor
 SOI, FinFET
Reduce the bipolar feedback
Poor BJTs
 Trenches
 Low sheet resistances
 Epi wafers (p- on p++ or n- on n++): reduces 1 Base resistor
 Increased recombination → reduces minority current and increases Idark
Reduce the pick-up
 Small charge collecting volume in the Bases
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Triple well...
The number of possible thryristors increases
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Good to know
nMOS-only or pMOS-only circuit parts cannot
latchup.
A standalone BJT does not latchup
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SEL and vulnerable nodes
 How much charge is deposited on a vulnerable
node
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Vulnerable volume @t0
VDD
VSS
++++++++++++++++++++++-
Vulnerable volume @t0+10ps
VDD
VSS
++++++
+ -
-
+++-
++++++++-
Vulnerable volume @t0+0.5ns
VDD
VSS
+ ++ +
recombination
-- -
+
++ -
+
+-
+
+-
+-
+
-
Net node charge
as function of time the nWELL case
electrons
Substrate electrons diffuse
into depletion layer then drift
into nWELL
Electrons diffuse to nWELL
VDD tie
Holes in nWELL diffuse into
depletion layer then drift into
substrate
Holes drift out of depletion layer to substrate
Electrons drift into nWELL
Event
time
~10ps
~1ns
How to estimate Q?
LET linear energy transfer
Heavy ions are commonly described by amount of energy lost
per unit track length = Linear Energy Transfer
Linear Energy Transfer




Energy loss per unit path length
dE/dx= MeV/cm
Divide by material density = MeV.cm2/mg
LET of 100 MeV.cm2/mg corresponds to charge deposition of 1pC/μm = 6E6 e-/h+
How does LET spectrum relate to the real space environment?
 A measure for the heaviest ions/events that can be expected
 Says nothing about number of particles or probability
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e-h+ pairs per µm
100 MeV.cm2/mg ≈ 1pC/µm = 6Me-h+/µm
This is a linear function, thus 50 MeV.cm2/mg is still 3
million charges/µm.
deposited e-h+/µm in Silicon
[e-h+/µm]
For reference /µm
1,E+06
e: e-/µm
α: 4E6 eh, max @1MeV
H+: 30000 eh, max @80keV
β (and γ): <5000 e-h+
h+: e-/µm
1,E+05
alfa: e-/µm
1,E+04
1,E+03
More energy: less charges!
1,E+02
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1,E+04sensors
1,E+05
radhard design in CMOS image
1,E+06
1,E+07
1,E+08
1,E+09
48 1,E+10
actual energy [eV]
Voltage drop
assuming instantanous charge deposition
Minimal junction size and capacitance
1fF & 1µm: 6000 e- = 1V
Electrons (hence gamma) cannot create Vforward
Protons can (marginally) ignite LU
Proton SEL hard junction?
5fF & 1µm: 30000 e- = 1V. Yet, shallow angle?
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electrons
Net node charge
as function of time
Maximum effect alfa
LET 100 MeV.cm2/mg
Maximum effect proton
Worst case threshold for SEL
Maximum effect electron / gamma <1GeV
time
~10ps
~1ns
Introduction
TID total ionizing dose
DD displacement damage
SEU single event [upset...]
SEL single event latch-up
Take home message
Take home
message
conclusions
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Take home
CMOS imagers can be made hard against TID,
SEL, SEU etc by design
TID: avoid field leakage
SEL: reduce bipolar feedback
SEU: vulnerable volume & circuit redundancy
Photodiode hardening for SE and displacement
damage remains a question
• Photodiode redundancy?
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Thank you
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