Methods for Signal Shorting in the PCB
Front to Back Flow
Product Version 16.2
April 8, 2011
Copyright Statement
© 2011 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence and the
Cadence logo are registered trademarks of Cadence Design Systems, Inc. All others are the
property of their respective holders.
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Contents
Purpose ....................................................................................................................... 4
Audience...................................................................................................................... 4
Overview ...................................................................................................................... 4
NET_SHORT Property ................................................................................................ 4
Allowed Global Shorts in DE-HDL ............................................................................... 5
Using NET_SHORT in the Schematic (force/sense example) ..................................... 6
Plane Shorts (AGND/DGND Example) ........................................................................ 9
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Purpose
This application note illustrates various methods for implementing shorted signals within
the Cadence PCB Front to Back flow. The specific design intent may be indicated in the
Allegro® Design Entry HDL schematic or the Allegro PCB Editor layout. The methods
presented allow the deliberate override of design rule checks for shorted signals.
Audience
Users of Allegro Design Entry HDL (DE-HDL) and Allegro PCB Editor and the resultant
design flow implemented with these tools. An Electrical Engineer may wish to embed in
the schematic the intention to short specific signal names. A PCB Editor user may need
to override the DRC for a shorted pair of ground signals at the board level. Alternatively,
the need to short global signals like grounds may be required.
Overview
In a majority of cases, two uniquely named signals in a design, SIG_1 and SIG_2 or
VCC and VDD would not be shorted together and as such the checking routines within
the tools will trap these situations and flag them as DRCs.
The need may arise to intentionally short two or more signals that have unique names in
the schematic for a design. An example of this would be for a force/sense set of signals
that are required to be shorted at the point of sense. This type of situation occurs in test
fixture designs. Another need for signal shorting occurs in designs that use separate
analog and digital grounds that will need to be connected together for a common
reference point at some location in the design.
This application note presents a number of things that can be done for different
scenarios. Outlined below are two features within the design tools that may be used to
facilitate the signal shorting.
NET_SHORT Property
The NET_SHORT property may be applied to indicate that a set of specified signals
connected together are to be ignored by the DRC system. The property may be placed
on a component pin or, alternatively, on a via. The NET_SHORT property may be
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placed on a pin in the schematic and will pass through to the Allegro PCB Editor board
(.brd).
The syntax for this property is a set of signal names separated by colons:
NET_SHORT sig1:sig2:sig3:…..
Allowed Global Shorts in DE-HDL
DE-HDL provides for defining allowed global signal shorts. Signal pairs may be defined
as being allowed to be connected together in the schematic. To do this, choose Tools >
Options and select the Output tab.
Figure 1
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The section near the bottom of this form is marked Allowed Global Shorts. Pairs of
signals are entered into the form. In this example, net 5V_1 will be allowed to short to
net 5V_NEW.
What this does, is prevent the check routine in DE-HDL from flagging this as a shorted
global signal. The resulting signal name (net) seen in PCB Editor will be one net with
the name 5V_1. If both signal names need to be available in the board, this method
should not be used.
Using NET_SHORT in the Schematic (force/sense
example)
In this scenario, the requirement is to define in the schematic, a pair of signals, one to
provide a force voltage and one used to measure it at the device under test. The two
routes will be shorted close to the device under test.
To implement this, a symbol is made for DE-HDL. One pin on this symbol is assigned
the NET_SHORT attribute. If this is built into the symbol as a place holder with a value
of “?” the symbol can be placed and then the value added, as it depends on the signal
names in the design.
Figure 2
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In this case, pin 1 of the NET_SHORT symbol carries the NET_SHORT attribute. To
use this symbol, the values of the signals on pin2 and pin3 are added. For example,
SENSE:IN0.
A matching PCB Editor symbol is constructed, to facilitate the sort point in the physical
representation. The symbol comprises a larger pin with embedded pins represented; in
this case, by vias. This will result in an object that can be placed at the desired location
and will have rats to guide routing to meet the design intent.
Figure 3
In Figure 4, the NET_SHORT symbol is shown in use, with the NET_SHORT property
on pin 1 assigned the value of the signals on pins 2 and 3. Net-based properties have
been used to set the line widths in the board.
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Figure 4
Figure 5 shows the result in the PCB Editor board. The NET_SHORT property is
passed to the board.
Figure 5
Figure 6 shows the routed connections with appropriate trace widths as defined in the
schematic.
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Figure 6
Plane Shorts (AGND/DGND Example)
Often the need arises to bring planes to a common point of reference in a design. The
most common need for this is analog and digital grounds. Two approaches are
available. First, the NET_SHORT symbol may be used (see previous section). This will
allow for the design intent to be indicated in the schematic. A physical symbol will be
required.
Alternatively, an approach driven from the PCB Editor board may be used. A padstack
or via may be inserted in the design with the NET_SHORT property attached. This may
be done at a point of close proximity of plane shapes on the same layer, as shown in
Figure 7. Note that in this case, each signal name on each plane shape is added.
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Figure 7
For connecting planes on different layers, a via or series of vias may be placed, each
carrying the NET_SHORT property with the signal name of the planes they connect.
Figure 8
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