Lecture 11: Inversion Coefficient
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Notes from
Review of notes from Dr. Fox
Example from
1
Bipolar collector current and transconductance
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The bipolar transistor collector current, base–emitter
voltage relationship is given by
Bipolar Transconductance
Bipolar transistor transconductance efficiency
For a thermal voltage UT = 25.9mV at room temperature (300K
or 27 C), bipolar transistor transconductance efficiency is
38.6/V or 38.6uS/uA. This means a transconductance of 38.6uS
or 38.6mS is produced for a collector bias current of 1A or 1mA,
respectively, found by multiplying the transconductance
efficiency by the collector bias current.
2
1
MOS Drain Current and Transconductance
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In Weak Inversion
MOS transconductance, gm= ID/VGS, in weak inversion is
given by
Transconductance efficiency, gm/ID, in weak inversion
is then given by
MOS transconductance, like bipolar transistor transconductance
is equal to the product of transconductance efficiency and drain
current, as given by
For a thermal voltage UT= 25.9mV at room temperature and
substrate factor n = 1.5, MOS weak inversion transconductance
efficiency is 25.7uS/uA, which is approximately 67% of the
bipolar transistor transconductance efficiency of 38.6uS/uA
where n, again, is effectively unity.
In weak inversion, n is related to
the capacitive voltage division
between the gate voltage and
silicon surface potential resulting
from the gategate-oxide, depletion, and
interface state capacitances. In
weak inversion, n is expressed by
The required increase in gate–source
voltage for a factor-of-10 increase in drain
current is given by the subthreshold swing
The weak inversion swing is
approximately 90 mV/decade
for bulk CMOS processes at
room temperature, assuming n
3
= 1.5 and UT = 25.9mV.
MOS Drain Current and Transconductance
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In Strong Inversion
In strong inversion, the drain–
source saturation voltage is
frequently taken as VDSsat≈
VGS−VT , while VDSsat≈
(VGS−VT)/n may be a better
choice since body effect along the
channel raises the local threshold
voltage and lowers the drain–
source voltage required
for inversion charge pinch-off.
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Transconductance efficiency in strong inversion is then given
by
4
2
In Moderate Inversion and All Regions of Operation
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Unified expressions for drain current
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More complex expression include velocity saturation, DIBL, CLM
effects
5
Designing with Inversion Coefficient (IC)
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Bias point of the MOS transistor can be quantified by
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Gate overdrive VGS-VT
Transconductance current ratio, gm/ID
Or the inversion coefficient (IC)
Inversion Coefficient (IC) is a
normalized measure of MOS
drain current that numerically
describes the level of channel
inversion
6
3
Inversion Coefficient (IC)
Equating the weak-inversion transconductance, with the strong-inversion
transconductance, gives
Solving for the drain current ID= ID (moderate) that gives equal weakand strong-inversion transconductance gives
This is the drain current for a device operating in
the center of moderate inversion where the
predicted weak- and strong-inversion
transconductances are equal.
Define IC as the ratio of ID to ID in Moderate Inversion
IC 
ID

I D ( M .I .)
ID
W 
2n  μ  C OX U  
 L
2
T

ID
W 
IO  
 L
IO is the technology current I O  2n  μ  C OX U T2
7
gm/ID and IC
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Relationship between transconductance efficiency and IC
Differentiating the drain current
with respect to the gate–source
voltage followed by dividing by
the drain current
A more accurate expression
And simple expression
8
4
VEFF and IC
VEFF from weak through strong inversion can be derived
from the continuous drain current expression.
Solving for VEFF in terms of the inversion coefficient requires
expressing drain current in terms of the inversion coefficient.
Substituting the drain current
Solving for VEFF gives
9
Inversion Coefficient (IC)
For analog design useful to define gm/I valid
over all regions of operation using EKV model
[Enz, et.al., Analog Integrat. Circuits Signal
Process.,1995]:
 IC
gm 1  e
1
2



I D nU T IC nU T 1  1  4  IC

VEFF  VGS  VT  2  n  U T ln e
IC
35
30
gm/ID (1/V)

25
20
15
10

1
5
IC
VGS-VT (mV)
moderate
weak
strong
0
0.01
0.1
1
10
-155.2
-68.1
37.3
214.9
100
688.9
10
5
Typical Drain Current Parameters
11
Shape Factor and Gate Size
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Recall
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IC 
ID

I D ( M .I .)
ID
ID

W 
W 
2n  μ  C OX U T2   I O  
 L
 L
Two ways to change IC
-
Through drain current (ID) or
Gate size W/L, or the shape factor (S)
Or, W derived from fixed ID and L
12
6
MOSFET Noise
Dominant noise sources for MOSFET
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Thermal noise and
Flicker noise due to carrier trapping and dede-trapping from SiO2 interface
VG2  f  
*

I
2
D
KF
COX WL  f
AF
 f   4kT  ng m
Root spectral
density –
Vn (nV/√Hz)

1/f noise
thermal
fc
Gate referred noise
*
-
(noiseless)
Vn2  f  
KF
COX WL  f
AF
 4kT 
freq
n
gm
KF flicker noise factor and AF is the frequency exponent
Г is 0.5 in W.I. and 2/3 in S.I.
n is the substrate factor
13
Gate Referred Thermal Noise
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Gate referred thermal noise for
MOSFET
n
V  f   4kT 
gm
2
n

(noiseless)
Input referred noise for fixed ID
increases with increasing
inversion level
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saturation thermal noise factor Г
increases
-
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*
Note that Vn2 decreases as ID increases
(even as IC increases)
1/2 in W.I. and 2/3 in S.I.
gm decreases in strong inversion as
IC increases
Flicker noise coefficient also
increases in strong inversion
14
7
Amplifier Design Example with IC
15
Recall Noise Analysis
16
8
Input Referred Noise
17
Noise Efficiency Factor
18
9
Supply current versus normalized noise
19
10