Appendix B
Page 1
54/74 FAMILIES OF COMPATIBLE TTL CIRCUITS
PIN ASSIGNMENT (TOP VIEWS)
See page 3
See page 7
See page 3
See page 14
See page 9
See page 16
See page 10
TEXAS INSTRUMENTS LTD have given their permission for this material to be reproduced for educational purposes (their letter, 29 June 1982, Mr K Goldup, Operations Manager).
Appendix B
Page 2
You can see more detailed versions of the following data sheets as PDF files at:
http://www2.eng.cam.ac.uk/~dmh/ptiialab/3B2
For further information and data sheets, point your browser at:
http://focus.ti.com/docs/logic/logichomepage.jhtml
TEXAS INSTRUMENTS LTD have given their permission for this material to be reproduced for educational purposes (their letter, 29 June 1982, Mr K Goldup, Operations Manager).
Page 3
MM54C00MM74C00 Quad 2-Input NAND Gate
MM54C02MM74C02 Quad 2-Input NOR Gate
MM54C04MM74C04 Hex Inverter
MM54C10MM74C10 Triple 3-Input NAND Gate
MM54C20MM74C20 Dual 4-Input NAND Gate
General Description
Features
These logic gates employ complementary MOS (CMOS) to
achieve wide power supply operating range low power consumption high noise immunity and symmetric controlled
rise and fall times With features such as this the 54C74C
logic family is close to ideal for use in digital systems Function and pin out compatibility with series 5474 devices minimizes design time for those designers already familiar with
the standard 5474 logic family
All inputs are protected from damage due to static discharge by diode clamps to VCC and GND
Y
Y
Y
Y
Y
Wide supply voltage range
Guaranteed noise margin
High noise immunity
Low power consumption
Low power
TTL compatibility
3V to 15V
1V
045 VCC (typ)
10 nWpackage (typ)
Fan out of 2
driving 74L
Connection Diagrams
Dual-In-Line Packages
MM54C00MM74C00
MM54C02MM74C02
TLF5877–1
MM54C04MM74C04
TLF5877–2
TLF5877–3
Top View
Top View
Top View
Order Number MM54C00 or
MM74C00
Order Number MM54C02 or
MM74C02
Order Number MM54C04
or MM74C04
MM54C00MM74C00 MM54C02MM74C02 MM54C04MM74C04
MM54C10MM74C10 MM54C20MM74C20
February 1988
Absolute Maximum Ratings
Operating VCC Range
Maximum VCC Voltage
If MilitaryAerospace specified devices are required
please contact the National Semiconductor Sales
OfficeDistributors for availability and specifications
b 03V to VCC a 03V
Voltage at Any Pin
Operating Temperature Range
54C
74C
Storage Temperature Range
30V to 15V
18V
Power Dissipation (PD)
Dual-In-Line
Small Outline
Lead Temperature
(Soldering 10 seconds)
b 55 C to a 125 C
b 40 C to a 85 C
b 65 C to a 150 C
700 mW
500 mW
300 C
DC Electrical Characteristics
MinMax limits apply across the guaranteed temperature range unless otherwise noted
Symbol
Parameter
Conditions
Min
Typ
Max
Units
CMOS TO CMOS
VIN(1)
VIN(0)
VOUT(1)
VOUT(0)
Logical ‘‘1’’ Input Voltage
Logical ‘‘0’’ Input Voltage
Logical ‘‘1’’ Output Voltage
Logical ‘‘0’’ Output Voltage
VCC e 50V
35
VCC e 10V
80
V
V
VCC e 50V
15
V
VCC e 10V
20
V
VCC e 50V IO e b10 mA
45
VCC e 10V IO e b10 mA
90
V
V
VCC e 50V IO e 10 mA
05
VCC e 10V IO e 10 mA
VCC e 15V VIN e 15V
IIN(1)
Logical ‘‘1’’ Input Current
IIN(0)
Logical ‘‘0’’ Input Current
VCC e 15V VIN e 0V
ICC
Supply Current
VCC e 15V
0005
b 10
10
V
10
mA
b 0005
001
V
mA
15
mA
LOW POWER TO CMOS
VIN(1)
VIN(0)
VOUT(1)
VOUT(0)
Logical ‘‘1’’ Input Voltage
Logical ‘‘0’’ Input Voltage
Logical ‘‘1’’ Output Voltage
Logical ‘‘0’’ Output Voltage
54C VCC e 45V
VCC b 15
74C VCC e 475V
VCC b 15
V
V
54C VCC e 45V
08
V
74C VCC e 475V
08
V
54C VCC e 45V IO e b10 mA
44
V
74C VCC e 475V IO e b10 mA
44
V
54C VCC e 45V IO e 10 mA
04
V
74C VCC e 475V IO e 10 mA
04
V
CMOS TO LOW POWER
MM54C10MM74C10
MM54C20MM74C20
VIN(1)
VIN(0)
VOUT(1)
VOUT(0)
TLF5877–4
Top View
Order Number MM54C10 or
MM74C10
Order Number MM54C20 or
MM74C20
TLF5877
Logical ‘‘0’’ Input Voltage
Logical ‘‘1’’ Output Voltage
Logical ‘‘0’’ Output Voltage
TLF5877–5
Top View
C1995 National Semiconductor Corporation
Logical ‘‘1’’ Input Voltage
RRD-B30M115Printed in U S A
54C VCC e 45V
40
V
74C VCC e 475V
40
V
54C VCC e 45V
10
V
74C VCC e 475V
10
V
54C VCC e 45V IO e b360 mA
24
V
74C VCC e 475V IO e b360 mA
24
V
54C VCC e 45V IO e 360 mA
04
V
74C VCC e 475V IO e 360 mA
04
V
OUTPUT DRIVE (see 54C74C Family Characteristics Data Sheet) TA e 25 C (short circuit current)
ISOURCE
Output Source Current
VCC e 50V VIN(0) e 0V VOUT e 0V
b 175
ISOURCE
Output Source Current
VCC e 10V VIN(0) e 0V VOUT e 0V
b 80
mA
ISINK
Output Sink Current
VCC e 50V VIN(1) e 50V VOUT e VCC
175
mA
ISINK
Output Sink Current
VCC e 10V VIN(1) e 10V VOUT e VCC
80
mA
2
mA
Page 4
AC Electrical Characteristics TA e 25 C CL e 50 pF unless otherwise specified
Symbol
Parameter
Conditions
Min
Typical Performance Characteristics
Typ
Max
Units
50
90
ns
60
MM54C00MM74C00 MM54C02MM74C02 MM54C04MM74C04
VCC e 50V
tpd0 tpd1
Propagation Delay Time to
Logical ‘‘1’’ or ‘‘0’’
VCC e 10V
30
CIN
Input Capacitance
(Note 2)
60
pF
CPD
Power Dissipation Capacitance
(Note 3) Per Gate or Inverter
12
pF
ns
Propagation Delay vs
Ambient Temperature
MM54C00MM74C00
MM54C02MM74C02
MM54C04MM74C04
(Continued)
Propagation Delay vs
Ambient Temperature
MM54C00MM74C00
MM54C02MM74C02
MM54C04MM74C04
Propagation Delay Time vs
Load Capacitance
MM54C00MM74C00
MM54C02MM74C02
MM54C04MM74C04
MM54C10MM74C10
tpd0 tpd1
Propagation Delay Time to
Logical ‘‘1’’ or ‘‘0’’
VCC e 50V
60
100
VCC e 10V
35
70
ns
ns
CIN
Input Capacitance
(Note 2)
70
pF
CPD
Power Dissipation Capacitance
(Note 3) Per Gate
18
pF
VCC e 50V
70
115
ns
VCC e 10V
40
80
ns
MM54C20MM74C20
tpd0 tpd1
Propagation Delay Time to
Logical ‘‘1’’ or ‘‘0’’
CIN
Input Capacitance
(Note 2)
9
pF
CPD
Power Dissipation Capacitance
(Note 3) Per Gate
30
pF
TLF5877 – 7
Propagation Delay Time vs
Load Capacitance
MM54C10MM74C10
Propagation Delay Time vs
Load Capacitance
MM54C20MM74C20
AC Parameters are guaranteed by DC correlated testing
Note 1 ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed Except for ‘‘Operating Temperature Range’’
they are not meant to imply that the devices should be operated at these limits The table of ‘‘Electrical Characteristics’’ provides conditions for actual device
operation
Note 2 Capacitance is guaranteed by periodic testing
Note 3 CPD determines the no load AC power consumption of any CMOS device For complete explanation see 54C74C Family Characteristics Application
NoteAN-90
Typical Performance Characteristics
Gate Transfer Characteristics
Guaranteed Noise Margin
Over Temperature vs VCC
Power Dissipation vs Frequency
MM54C00MM74C00
MM54C02MM74C02
MM54C04MM74C04
TLF5877 – 8
TLF5877 – 9
Switching Time Waveforms and AC Test Circuit
CMOS to CMOS
TLF5877 – 11
TLF5877–6
TLF5877 – 10
Note Delays measured with input tr tf s 20 ns
3
4
Page 5
Page 6
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Page 9
SN5490A, SN5492A, SN5493A, SN54LS90, SN54LS92, SN54LS93
SN7490A, SN7492A, SN7493A, SN74LS90, SN74LS92, SN74LS93
DECADE, DIVIDE-BY-TWELVE AND BINARY COUNTERS
SN5490A, SN5492A, SN5493A, SN54LS90, SN54LS92, SN54LS93
SN7490A, SN7492A, SN7493A, SN74LS90, SN74LS92, SN74LS93
DECADE, DIVIDE-BY-TWELVE AND BINARY COUNTERS
SDLS940A – MARCH 1974 – REVISED MARCH 1988
SDLS940A – MARCH 1974 – REVISED MARCH 1988
Page 10
Copyright ¤ 1988, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
x DALLAS, TEXAS 75265
1
POST OFFICE BOX 655303
x DALLAS, TEXAS 75265
3
SN5490A, SN5492A, SN5493A, SN54LS90, SN54LS92, SN54LS93
SN7490A, SN7492A, SN7493A, SN74LS90, SN74LS92, SN74LS93
DECADE, DIVIDE-BY-TWELVE AND BINARY COUNTERS
SN5490A, SN5492A, SN5493A, SN54LS90, SN54LS92, SN54LS93
SN7490A, SN7492A, SN7493A, SN74LS90, SN74LS92, SN74LS93
DECADE, DIVIDE-BY-TWELVE AND BINARY COUNTERS
SDLS940A – MARCH 1974 – REVISED MARCH 1988
SDLS940A – MARCH 1974 – REVISED MARCH 1988
Page 11
4
POST OFFICE BOX 655303
x DALLAS, TEXAS 75265
POST OFFICE BOX 655303
x DALLAS, TEXAS 75265
5
SN5490A, SN5492A, SN5493A, SN54LS90, SN54LS92, SN54LS93
SN7490A, SN7492A, SN7493A, SN74LS90, SN74LS92, SN74LS93
DECADE, DIVIDE-BY-TWELVE AND BINARY COUNTERS
SN5490A, SN5492A, SN5493A, SN54LS90, SN54LS92, SN54LS93
SN7490A, SN7492A, SN7493A, SN74LS90, SN74LS92, SN74LS93
DECADE, DIVIDE-BY-TWELVE AND BINARY COUNTERS
SDLS940A – MARCH 1974 – REVISED MARCH 1988
Page 12
6
SDLS940A – MARCH 1974 – REVISED MARCH 1988
POST OFFICE BOX 655303
x DALLAS, TEXAS 75265
POST OFFICE BOX 655303
x DALLAS, TEXAS 75265
7
SN5490A, SN5492A, SN5493A, SN54LS90, SN54LS92, SN54LS93
SN7490A, SN7492A, SN7493A, SN74LS90, SN74LS92, SN74LS93
DECADE, DIVIDE-BY-TWELVE AND BINARY COUNTERS
SN5490A, SN5492A, SN5493A, SN54LS90, SN54LS92, SN54LS93
SN7490A, SN7492A, SN7493A, SN74LS90, SN74LS92, SN74LS93
DECADE, DIVIDE-BY-TWELVE AND BINARY COUNTERS
SDLS940A – MARCH 1974 – REVISED MARCH 1988
Page 13
8
SDLS940A – MARCH 1974 – REVISED MARCH 1988
POST OFFICE BOX 655303
x DALLAS, TEXAS 75265
POST OFFICE BOX 655303
x DALLAS, TEXAS 75265
9
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