EE 3CL4, §6
1 / 63
Tim Davidson
Compensators
Lead
compensation
Design via Root
Locus
Lead Compensator
example
Cascade
compensation
and
steady-state
errors
Lag
Compensation
Design via Root
Locus
Lag compensator
example
EE3CL4:
Introduction to Linear Control Systems
Section 6: Design of Lead and Lag Controllers using
Root Locus
Tim Davidson
McMaster University
Prop. vs Lead
vs Lag
Concluding
Insights
Winter 2016
EE 3CL4, §6
2 / 63
Outline
Tim Davidson
Compensators
Lead
compensation
Design via Root
Locus
Lead Compensator
example
Cascade
compensation
and
steady-state
errors
1 Compensators
2 Lead compensation
Design via Root Locus
Lead Compensator example
3 Cascade compensation and steady-state errors
Lag
Compensation
Design via Root
Locus
Lag compensator
example
Prop. vs Lead
vs Lag
Concluding
Insights
4 Lag Compensation
Design via Root Locus
Lag compensator example
5 Prop. vs Lead vs Lag
6 Concluding Insights
EE 3CL4, §6
4 / 63
Compensators
Tim Davidson
Compensators
Lead
compensation
Design via Root
Locus
Lead Compensator
example
Cascade
compensation
and
steady-state
errors
• Early in the course we provided some useful guidelines
regarding the relationships between the pole positions
of a system and certain aspects of its performance
• Using root locus techniques, we have seen how the
pole positions of a closed loop can be adjusted by
varying a parameter
Lag
Compensation
Design via Root
Locus
Lag compensator
example
Prop. vs Lead
vs Lag
Concluding
Insights
• What happens if we are unable to obtain that
performance that we want by doing this?
• Ask ourselves whether this is really the performance
that we want
• Ask whether we can change the system,
say by buying different components
• seek to compensate for the undesirable aspects of the
process
EE 3CL4, §6
5 / 63
Tim Davidson
Cascade compensation
Compensators
Lead
compensation
Design via Root
Locus
Lead Compensator
example
Cascade
compensation
and
steady-state
errors
Lag
Compensation
Design via Root
Locus
Lag compensator
example
Prop. vs Lead
vs Lag
Concluding
Insights
• Usually, the plant is a physical process
• If commands and measurements are made electrically,
compensator is often an electric circuit
• General form of the compensator is
Q
Kc M
(s + zi )
Gc (s) = Qn i=1
j=1 (s + pj )
• Therefore, the cascade compensator adds open loop
poles and open loop zeros
• These will change the shape of the root locus
EE 3CL4, §6
6 / 63
Compensator design
Tim Davidson
Compensators
Lead
compensation
Design via Root
Locus
Lead Compensator
example
Cascade
compensation
and
steady-state
errors
Lag
Compensation
Design via Root
Locus
• Where should we put new poles and zeros to achieve
desired performance?
• That is the art of compensator design
• We will consider first order compensators of the form
Lag compensator
example
Prop. vs Lead
vs Lag
Concluding
Insights
Gc (s) =
Kc (s + z)
K̃c (1 + s/z)
=
,
(s + p)
(1 + s/p)
where K̃c = Kc z/p
• with the pole −p in the left half plane
• and the zero, −z in the left half plane, too
• For reasons that will soon become clear
• when |z| < |p|: phase lead network
• when |z| > |p|: phase lag network
EE 3CL4, §6
8 / 63
Lead compensation
Tim Davidson
Compensators
Lead
compensation
Design via Root
Locus
Lead Compensator
example
Cascade
compensation
and
steady-state
errors
Kc (s + z)
(s + p)
with |z| < |p|. That is, zero closer to origin than pole
Gc (s) =
Lag
Compensation
Design via Root
Locus
Lag compensator
example
Prop. vs Lead
vs Lag
Concluding
Insights
Let p = 1/τp and z = 1/(αlead τp ). Since z < p, αlead > 1.
Define K̃c = Kc z/p = Kc /αlead . Then
Gc (s) =
K̃c (1 + αlead τp s)
Kc (s + z)
=
(s + p)
(1 + τp s)
EE 3CL4, §6
9 / 63
Tim Davidson
Compensators
Lead
compensation
Design via Root
Locus
Lead Compensator
example
Cascade
compensation
and
steady-state
errors
Lead compensation
With |z| < |p|, αlead > 1, Gc (s) =
Kc (s+z)
(s+p)
=
K̃c (1+αlead τp s)
(1+τp s)
• Frequency response:
Gc (jω) =
K̃c (1 + jωαlead τp )
(1 + jωτp )
• Bode diagram (in the figure, K1 = K̃c )
Lag
Compensation
Design via Root
Locus
Lag compensator
example
Prop. vs Lead
vs Lag
Concluding
Insights
• Between ω = z and ω = p, |Gc (jω)| ≈ K̃c ωαlead τp
• What kind of operator has a frequency response with
magnitude proportional to ω? Differentiator
• Note that the phase is positive. Hence “phase lead”
EE 3CL4, §6
10 / 63
Tim Davidson
A passive phase lead network
Compensators
Lead
compensation
Design via Root
Locus
Lead Compensator
example
Cascade
compensation
and
steady-state
errors
Lag
Compensation
Design via Root
Locus
Lag compensator
example
Prop. vs Lead
vs Lag
Concluding
Insights
Homework: Show that
characteristic
V2 (s)
V1 (s)
has the phase lead
EE 3CL4, §6
11 / 63
Tim Davidson
Active lead and lag networks
Compensators
Lead
compensation
Design via Root
Locus
Lead Compensator
example
Cascade
compensation
and
steady-state
errors
Lag
Compensation
Design via Root
Locus
Lag compensator
example
Prop. vs Lead
vs Lag
Concluding
Insights
Here’s an example of an active network architecture.
EE 3CL4, §6
12 / 63
Tim Davidson
Compensators
Lead
compensation
Design via Root
Locus
Lead Compensator
example
Cascade
compensation
and
steady-state
errors
Lag
Compensation
Design via Root
Locus
Lag compensator
example
Prop. vs Lead
vs Lag
Concluding
Insights
Principles of Lead design via
Root Locus
• The compensator adds poles and zeros to the P(s) in
the root locus procedure.
• Hence we can change the shape of the root locus.
• If we can capture desirable performance in terms of
positions of closed loop poles
• then compensator design problem reduces to:
• changing the shape of the root locus so that these
desired closed-loop pole positions appear on the root
locus
• finding the gain that places the closed-loop pole
positions at their desired positions
• What tools do we have to do this?
• Phase criterion and magnitude criterion, respectively
EE 3CL4, §6
13 / 63
Root Locus Principles
Tim Davidson
Compensators
• The point s0 is on the root locus of P(s) if 1 + KP(s0 ) = 0.
Lead
compensation
• In first order compensator design with G(s) =
Design via Root
Locus
Lead Compensator
example
Cascade
compensation
and
steady-state
errors
Lag
Compensation
Design via Root
Locus
Lag compensator
example
and Gc =
Kc (s+z)
(s+p) ,
QM
(s+z) Qi=1 (s+zi )
n
(s+p)
j=1 (s+pj )
and
K = Kc KG . We will restrict attention to the case of K > 0
• Phase cond. s0 is on root locus if ∠P(s0 ) = 180◦ + k 360◦ :
M
X
(angle from −zi to s0 ) −
i=1
n
X
(angle from −pj to s0 )
j=1
+ (angle from −z to s0 ) − (angle from −p to s0 )
Prop. vs Lead
vs Lag
Concluding
Insights
we have P(s) =
Q
(s+zi )
KG M
Qn i=1
j=1 (s+pj )
= 180◦ + k 360◦
• Mag. cond. If s0 satisfies phase condition, the gain that puts
a closed-loop pole at s0 is K = 1/|P(s0 )|:
Qn
(dist from −p to s0 )
j=1 (dist from −pj to s0 )
K = QM
×
(dist from −zi to s0 ) (dist from −z to s0 )
i=1
EE 3CL4, §6
14 / 63
RL design: Basic procedure
Tim Davidson
1
Translate design specifications into desired positions of
dominant poles
2
Sketch root locus of uncompensated system to see if desired
positions can be achieved
Cascade
compensation
and
steady-state
errors
3
If not, choose the positions of the pole and zero of the
compensator so that the desired positions lie on the root
locus (phase criterion), if that is possible
Lag
Compensation
4
Evaluate the gain required to put the poles there
(magnitude criterion)
5
Evaluate the total system gain so that the steady-state error
constants can be determined
6
If the steady state error constants are not satisfactory, repeat
Compensators
Lead
compensation
Design via Root
Locus
Lead Compensator
example
Design via Root
Locus
Lag compensator
example
Prop. vs Lead
vs Lag
Concluding
Insights
This procedure enables relatively straightforward design of
systems with specifications in terms of rise time, settling time, and
overshoot; i.e., the transient response.
For systems with steady-state error specifications, Bode (and
Nyquist) methods may be more straightforward (later)
EE 3CL4, §6
15 / 63
Lead Comp. example
Tim Davidson
Compensators
Lead
compensation
Design via Root
Locus
Lead Compensator
example
Cascade
compensation
and
steady-state
errors
Lag
Compensation
Design via Root
Locus
Lag compensator
example
Prop. vs Lead
vs Lag
Concluding
Insights
1
Consider a case with G(s) = s(s+2)
and H(s) = 1.
Design a lead compensator to achieve:
• damping coefficient ζ ≈ 0.45 and
• velocity error constant Kv = lims→0 sGc (s)G(s) > 20
• swift transient response (small settling time)
What to do?
• Can we achieve this with proportional control?
• If not we will attempt lead control
EE 3CL4, §6
16 / 63
Attempt prop. control
Tim Davidson
Compensators
Lead
compensation
Design via Root
Locus
Lead Compensator
example
Cascade
compensation
and
steady-state
errors
Lag
Compensation
Design via Root
Locus
Lag compensator
example
Prop. vs Lead
vs Lag
Concluding
Insights
• Sketch root locus of
1
s(s+2)
−1
• Sketch rays of angle cos (0.45) ≈ 60◦ to neg. real axis
• Are there intersections? Yes
• If so, what is the corresponding value of K = KP KG ?
K = d1 d2 = 5
• Does that K generate a large enough velocity error const.?
No, Kv = 2.5 :(
• Do the closed-loop poles have responses that decay
quickly? No, Ts ≈ 4s
EE 3CL4, §6
17 / 63
Tim Davidson
Compensators
Lead
compensation
Design via Root
Locus
Lead Compensator
example
Cascade
compensation
and
steady-state
errors
Lag
Compensation
Design via Root
Locus
Lag compensator
example
Prop. vs Lead
vs Lag
Concluding
Insights
Prop. control, step response
EE 3CL4, §6
18 / 63
Tim Davidson
Lead compensated design
Compensators
Lead
compensation
Design via Root
Locus
Lead Compensator
example
Cascade
compensation
and
steady-state
errors
Lag
Compensation
Design via Root
Locus
Lag compensator
example
Prop. vs Lead
vs Lag
Concluding
Insights
• Plot poles of G(s).
Where should the closed-loop poles be? cos−1 (0.45) ≈ 60◦
• Note that the settling time is not specified; it only needs to be
small. This provides design flexibility.
• However, we need a large Kv which will require large gain.
Need desired positions far from open loop poles.
• Let’s start with desired roots at −4 ± j8
√
• This pair has Ts = 1s and ωn = 42 + 82 ≈ 8.9
EE 3CL4, §6
19 / 63
Tim Davidson
Lead Comp. example
Compensators
Lead
compensation
Design via Root
Locus
Lead Compensator
example
Cascade
compensation
and
steady-state
errors
Lag
Compensation
Design via Root
Locus
Lag compensator
example
Prop. vs Lead
vs Lag
Concluding
Insights
• Now where to put the zero and pole? (Centroid denoted ca )
• Rule of thumb: put zero under desired root, or just to the left
• Determine position of the pole using angle criterion
X
X
angles from OL zeros −
angles from OL poles = 180◦
∼ 90 − (116 + 104 + θp ) = 180
=⇒ θp ≈ 50
• Hence pole at −p ≈ −10.86
EE 3CL4, §6
20 / 63
Tim Davidson
Lead Comp. example
Compensators
Lead
compensation
Design via Root
Locus
Lead Compensator
example
Cascade
compensation
and
steady-state
errors
Lag
Compensation
Design via Root
Locus
Lag compensator
example
Prop. vs Lead
vs Lag
Concluding
Insights
• Gain of compensated system:
d1 d2 dp
Prod. dist. from open-loop poles
=
Prod. dist. from open-loop zeros
dz
8.94(8.25)(10.54)
≈
≈ 97.1
8
• Hence compensated open loop: Gc (s)G(s) =
97.1(s+4)
s(s+2)(s+10.86)
• Velocity constant: Kv = lims→0 sGc (s)G(s) ≈ 17.9 :(
EE 3CL4, §6
21 / 63
What to do now?
Tim Davidson
Compensators
Lead
compensation
Design via Root
Locus
Lead Compensator
example
Cascade
compensation
and
steady-state
errors
Lag
Compensation
Design via Root
Locus
Lag compensator
example
Prop. vs Lead
vs Lag
Concluding
Insights
• We tried hard, but did not achieve the design specs
• Let’s go back and re-examine our choices
• Zero position of compensator was chosen via rule of
thumb
• Can we do better?
Yes, but two parameter design becomes trickier.
• What were other choices that we made?
• We chose desired poles to be of magnitude ωn ≈ 8.9
• We could choose them to be further away
(faster transient response)
• By how much?
• Show that when desired poles have ωn = 10 as well as
the required ζ ≈ 0.45, then the choice of z ≈ 4.47,
p ≈ 12.5 and KC ≈ 125 results in Kv ≈ 22.3
EE 3CL4, §6
22 / 63
Tim Davidson
Root Locus, new lead comp.
Compensators
Lead
compensation
Design via Root
Locus
Lead Compensator
example
Cascade
compensation
and
steady-state
errors
Lag
Compensation
Design via Root
Locus
Lag compensator
example
Prop. vs Lead
vs Lag
Concluding
Insights
Centroid denoted ca
EE 3CL4, §6
23 / 63
New lead comp.
Tim Davidson
Prop.-contr.
Lead contr.
5
125(s+4.47)
(s+12.5)
OL TF, GC (s)G(s)
5
s(s+2)
125(s+4.47)
1
(s+12.5) s(s+2)
Y (s)
R(s)
5
s(s+2)+5
125(s+4.47)
s(s+2)(s+12.5)+125(s+4.47)
CL poles
−1 ± j2
−4.47 ± j8.94, −5.59
CL zeros
∞, ∞
−4.47, ∞, ∞
Compensators
Lead
compensation
Design via Root
Locus
Lead Compensator
example
Cascade
compensation
and
steady-state
errors
Lag
Compensation
Design via Root
Locus
Lag compensator
example
Controller, GC (s)
CL TF,
CL TF, again
5
s2 +2s+5
131(1+0.013s)
s2 +8.94s+100
−
1.71
s+5.59
Prop. vs Lead
vs Lag
Concluding
Insights
• Complex conjugate poles still dominate
• Closed-loop zero at -4.47 (which is also an open-loop
zero) reduces impact of closed-loop pole at -5.59; see
also slide 48 of Section 3: Fundamentals of Feedback
EE 3CL4, §6
24 / 63
Tim Davidson
Compensators
Lead
compensation
Design via Root
Locus
Lead Compensator
example
Cascade
compensation
and
steady-state
errors
Lag
Compensation
Design via Root
Locus
Lag compensator
example
Prop. vs Lead
vs Lag
Concluding
Insights
New lead comp., ramp response
EE 3CL4, §6
25 / 63
Tim Davidson
Compensators
Lead
compensation
Design via Root
Locus
Lead Compensator
example
Cascade
compensation
and
steady-state
errors
Lag
Compensation
Design via Root
Locus
Lag compensator
example
Prop. vs Lead
vs Lag
Concluding
Insights
New lead comp., ramp
response, detail
EE 3CL4, §6
26 / 63
Tim Davidson
New lead comp., step response
Compensators
Lead
compensation
Design via Root
Locus
Lead Compensator
example
Cascade
compensation
and
steady-state
errors
Lag
Compensation
Design via Root
Locus
Lag compensator
example
Prop. vs Lead
vs Lag
Concluding
Insights
Note faster settling time than prop. controlled loop,
However, the CL zero has increased the overshoot a little
Perhaps we should go back and re-design for ζ ≈ 0.40
in order to better control the overshoot
EE 3CL4, §6
27 / 63
Tim Davidson
Outcomes
Compensators
• Root locus approach to phase lead design was
Lead
compensation
Design via Root
Locus
Lead Compensator
example
Cascade
compensation
and
steady-state
errors
Lag
Compensation
Design via Root
Locus
Lag compensator
example
Prop. vs Lead
vs Lag
Concluding
Insights
reasonably successful in terms of putting dominant
poles in desired positions; e.g., in terms of ζ and ωn
• We did this by positioning the pole and zero of the lead
compensator so as to change the shape of the root
locus
• However, root locus approach does not provide
independent control over steady-state error constants
(details upcoming)
• That said, since lead compensators reduce the DC gain
(they resemble differentiators), they are not normally
used to control steady-state error.
• The goal of our lag compensator design will be to
increase the steady-state error constants, without
moving the other poles too far
EE 3CL4, §6
29 / 63
Tim Davidson
Cascade compensation
Compensators
Lead
compensation
Design via Root
Locus
Lead Compensator
example
Cascade
compensation
and
steady-state
errors
Lag
Compensation
Design via Root
Locus
Lag compensator
example
Prop. vs Lead
vs Lag
Concluding
Insights
• Throughout this lecture, and all the discussion on cascade
compensation, we will consider the case in which H(s) = 1.
• We will consider first order compensators of the form
Gc (s) =
K (s + z)
(s + p)
with the pole, −p, and the zero, −z, both in the left half plane
• when |z| < |p|: phase lead network
• when |z| > |p|: phase lag network
EE 3CL4, §6
30 / 63
Steady-state errors
Tim Davidson
Compensators
Lead
compensation
Design via Root
Locus
Lead Compensator
example
Cascade
compensation
and
steady-state
errors
Lag
Compensation
Design via Root
Locus
Lag compensator
example
Prop. vs Lead
vs Lag
Concluding
Insights
If closed loop stable, steady state error for input R(s):
ess = lim e(t) = lim s
t→∞
Let G(s) =
Q
KG i (s+zi )
Q
j (s+pj )
s→0
R(s)
1 + GC (s)G(s)
and consider GC (s) =
KC (s+z)
(s+p)
• Consider the case in which G(s) is a type-0 system.
• Steady state error due to a step r (t) = Au(t):
ess = 1+KAposn , where
Q
KC z KG i zi
Q
Kposn = GC (0)G(0) =
p
j pj
• Note that for a lead compensator, z/p < 1,
• So lead compensation may degrade steady-state error
performance
EE 3CL4, §6
31 / 63
Steady-state error
Tim Davidson
Compensators
Lead
compensation
Design via Root
Locus
Lead Compensator
example
Cascade
compensation
and
steady-state
errors
Lag
Compensation
Design via Root
Locus
Lag compensator
example
Prop. vs Lead
vs Lag
Concluding
Insights
• Now, consider the case
in which G(s) is a type-1
Q
system, G(s) =
KGQ i (s+zi )
s j (s+pj )
• Steady-state error due to a ramp r (t) = At: ess = A/Kv ,
where the velocity constant is
Q
KC z KG i zi
Q
Kv = lim sGc (s)G(s) =
p
s→0
j pj
• Once again, lead compensation may degrade
steady-state error performance
• Is there a way to increase the value of these error
constants while leaving the closed loop poles in
essentially the same place as they were in an
uncompensated system? Perhaps |z| > |p|?
EE 3CL4, §6
33 / 63
Lag compensation
Tim Davidson
Compensators
Lead
compensation
Design via Root
Locus
Lead Compensator
example
Cascade
compensation
and
steady-state
errors
Kc (s + z)
(s + p)
with |z| > |p|. That is, pole closer to origin than zero
Gc (s) =
Lag
Compensation
Design via Root
Locus
Lag compensator
example
Prop. vs Lead
vs Lag
Concluding
Insights
Let z = 1/τz and p = 1/(αlag τz ). Since z > p, αlag > 1.
Define K̃c = Kc z/p = Kc αlag . Then
Gc (s) =
K̃c (1 + τz s)
Kc (s + z)
=
(s + p)
(1 + αlag τz s)
EE 3CL4, §6
34 / 63
Frequency response
Tim Davidson
Compensators
Gc (jω) =
Lead
compensation
Design via Root
Locus
Lead Compensator
example
Cascade
compensation
and
steady-state
errors
Lag
Compensation
Design via Root
Locus
Lag compensator
example
Prop. vs Lead
vs Lag
Concluding
Insights
K̃C (1 + jωτz )
(1 + jωαlag τz )
Magnitude
• Low frequency gain: K̃C
• Corner freq. in denominator at ωp = p = 1/(αlag τz )
• Corner freq. in numerator at ωz = z = 1/τz
• ωp < ωz
• High frequency gain: K̃C /αlag = KC
Phase
• φ(ω) = atan(ωτz ) − atan(αlag ωτz )
• At low frequency: φ(ω) = 0
• At high frequency: φ(ω) = 0
• In between: negative, with max. lag at ω =
√
zp
EE 3CL4, §6
35 / 63
Tim Davidson
Bode Diagram, with K̃c = 1
Compensators
Lead
compensation
Design via Root
Locus
Lead Compensator
example
Cascade
compensation
and
steady-state
errors
Lag
Compensation
Design via Root
Locus
Lag compensator
example
Prop. vs Lead
vs Lag
Concluding
Insights
Note integrative characteristic
EE 3CL4, §6
36 / 63
Tim Davidson
Compensators
Lead
compensation
Design via Root
Locus
Lead Compensator
example
Cascade
compensation
and
steady-state
errors
Lag
Compensation
Design via Root
Locus
Lag compensator
example
Prop. vs Lead
vs Lag
Concluding
Insights
A passive phase lag network
EE 3CL4, §6
37 / 63
Tim Davidson
Active lead and lag networks
Compensators
Lead
compensation
Design via Root
Locus
Lead Compensator
example
Cascade
compensation
and
steady-state
errors
Lag
Compensation
Design via Root
Locus
Lag compensator
example
Prop. vs Lead
vs Lag
Concluding
Insights
Here’s an example of an active network architecture.
EE 3CL4, §6
38 / 63
Lag compensator design
Tim Davidson
Compensators
Lead
compensation
Design via Root
Locus
Lead Compensator
example
Cascade
compensation
and
steady-state
errors
Lag
Compensation
Design via Root
Locus
• Lag compensator: Gc (s) = Kc
s+z
s+p .
with |z| > |p|.
• Recall position error constant for compensated type-0
system and velocity error constant for compensated type-1
system:
Q
Q
KC z KG i zi
KC z KG i zi
Q
Q
Kposn =
,
Kv =
p
p
j pj
j pj
where in the latter case the product in the denominator is
over the non-zero poles.
Lag compensator
example
Prop. vs Lead
vs Lag
Concluding
Insights
Design Principles
• We don’t try to reshape the uncompensated root locus.
• We just try to increase the value of the desired error constant
by a factor αlag = z/p without moving the poles (well not
much)
• Reshaping was the goal of lead compensator design
EE 3CL4, §6
39 / 63
Tim Davidson
Lag compensator design
Compensators
Lead
compensation
Design via Root
Locus
Lead Compensator
example
Cascade
compensation
and
steady-state
errors
Lag
Compensation
Design via Root
Locus
Lag compensator
example
Prop. vs Lead
vs Lag
Concluding
Insights
Design principles:
• Don’t reshape the root locus
• Adding the open loop pole and zero from the
compensator should only result in a small change to the
angle criterion for any point on the uncompensated root
locus
• Angles from compensator pole and zero to any point on
the locus must be similar
• Pole and zero must be close together
• Increase value of error constant:
• Want to have a large value for αlag = z/p.
• How can that happen if z and p are close together?
• Only if z and p are both small, i.e., close to the origin
EE 3CL4, §6
40 / 63
Lag comp. design via Root
Locus
Tim Davidson
Compensators
Lead
compensation
Design via Root
Locus
1
2
Lead Compensator
example
Cascade
compensation
and
steady-state
errors
3
Lag
Compensation
5
4
Design via Root
Locus
Lag compensator
example
Prop. vs Lead
vs Lag
Concluding
Insights
6
Obtain the root locus of uncompensated system
From transient performance specs, locate suitable
dominant pole positions on that locus
Obtain the loop gain for these points, K = KP KG ;
hence the (closed-loop) steady-state error constant
Calculate the necessary increase. Hence αlag = z/p
Place pole and zero close to the origin (with respect to
desired pole positions), with z = αlag p.
Typically, choose z and p so that their angles to desired
poles differ by less than 1◦ .
Set KC = KP
What if there is nothing suitable at step 2?
• Perhaps do lead compensation first,
• then lag compensation on lead compensated plant.
i.e., design a lead-lag compensator
EE 3CL4, §6
41 / 63
Tim Davidson
Example
Compensators
Lead
compensation
Design via Root
Locus
Lead Compensator
example
Cascade
compensation
and
steady-state
errors
Lag
Compensation
Design via Root
Locus
Lag compensator
example
Prop. vs Lead
vs Lag
Concluding
Insights
1
Let’s consider, again, the case with G(s) = s(s+2)
.
Design a lag compensator to achieve damping coefficient
ζ ≈ 0.45 and velocity error constant Kv > 20
Note: we will get a different closed loop from our lead
design.
First step, obtain uncompensated root locus, and locate
desired dominant pole locations
EE 3CL4, §6
42 / 63
Example
Tim Davidson
Compensators
Lead
compensation
Design via Root
Locus
Lead Compensator
example
Cascade
compensation
and
steady-state
errors
Lag
Compensation
Design via Root
Locus
Lag compensator
example
Prop. vs Lead
vs Lag
Concluding
Insights
• Gain required to put closed loop poles in desired position =
prod. distances from open loop poles
• That is, K = 2.242 = 5. Therefore KP = K /KG = 5
• Velocity error const: Kv ,unc = lims→0 sKP G(s) = K /2 = 2.5
• The increase required is 20/2.5 = 8
• That implies must choose p = z/8, where z is chosen to be
close to the origin with respect to dominant closed-loop poles
EE 3CL4, §6
43 / 63
Tim Davidson
Example
Compensators
Lead
compensation
Design via Root
Locus
Lead Compensator
example
Cascade
compensation
and
steady-state
errors
Lag
Compensation
Design via Root
Locus
Lag compensator
example
Prop. vs Lead
vs Lag
Concluding
Insights
Let’s choose z = 0.1. Hence, p = 1/80.
EE 3CL4, §6
44 / 63
Example
Tim Davidson
Compensators
Lead
compensation
Design via Root
Locus
Lead Compensator
example
Cascade
compensation
and
steady-state
errors
Lag
Compensation
Design via Root
Locus
Lag compensator
example
Prop. vs Lead
vs Lag
Concluding
Insights
Root locus of lag comp’d system with GC (s) =
•
•
•
•
KC (s+0.1)
(s+1/80)
’s: closed-loop poles for prop.-control with KP = 5
×’s: open-loop poles of lag comp’d system
◦: OL zero of lag comp’d system; also a CL zero
4’s: Closed-loop poles for lag-control with KC = 5
EE 3CL4, §6
45 / 63
Example
Tim Davidson
Prop.-contr.
Lag contr.
5
5(s+0.1)
(s+1/80)
OL TF, GC (s)G(s)
5
s(s+2)
5(s+0.1)
1
(s+1/80) s(s+2)
Y (s)
R(s)
5
s(s+2)+5
5(s+0.1)
s(s+2)(s+1/80)+5(s+0.1)
CL poles
−1 ± j2
−0.955 ± j1.979, −0.104
CL zeros
∞, ∞
−0.1, ∞, ∞
Compensators
Lead
compensation
Controller, GC (s)
Design via Root
Locus
Lead Compensator
example
Cascade
compensation
and
steady-state
errors
Lag
Compensation
Design via Root
Locus
Lag compensator
example
CL TF,
CL TF, again
5
s2 +2s+5
4.999(1+7×10−4 s)
s2 +1.909s+4.827
+
−0.004
s+0.104
Prop. vs Lead
vs Lag
Concluding
Insights
• Complex conjugate poles still dominate
• Closed-loop zero at -0.1 (which is also an open-loop
zero) reduces impact of closed-loop pole at -0.104; see
also slide 48 of Section 3: Fundamentals of Feedback
EE 3CL4, §6
46 / 63
Tim Davidson
Compensators
Lead
compensation
Design via Root
Locus
Lead Compensator
example
Cascade
compensation
and
steady-state
errors
Lag
Compensation
Design via Root
Locus
Lag compensator
example
Prop. vs Lead
vs Lag
Concluding
Insights
Ramp response
EE 3CL4, §6
47 / 63
Tim Davidson
Compensators
Lead
compensation
Design via Root
Locus
Lead Compensator
example
Cascade
compensation
and
steady-state
errors
Lag
Compensation
Design via Root
Locus
Lag compensator
example
Prop. vs Lead
vs Lag
Concluding
Insights
Ramp response, detail
EE 3CL4, §6
48 / 63
Tim Davidson
Step response
Compensators
Lead
compensation
Design via Root
Locus
Lead Compensator
example
Cascade
compensation
and
steady-state
errors
Lag
Compensation
Design via Root
Locus
Lag compensator
example
Prop. vs Lead
vs Lag
Concluding
Insights
Note longer settling time of lag controlled loop,
and slight increase in overshoot, due to CL zero
EE 3CL4, §6
50 / 63
Design Comparisons
Tim Davidson
Compensators
Lead
compensation
For given example: G(s) =
Design via Root
Locus
Lead Compensator
example
Cascade
compensation
and
steady-state
errors
Lag
Compensation
Design via Root
Locus
Lag compensator
example
Prop. vs Lead
vs Lag
Concluding
Insights
GC (s)
1
s(s+2) ,
ζ ≈ 0.45, Kv ≥ 20.
Prop.-contr.
Lead contr.
Lag contr.
5
125(s+4.47)
(s+12.5)
5(s+0.1)
(s+1/80)
4.999(1+7×10−4 s)
s2 +1.909s+4.827
Y (s)
R(s)
5
s2 +2s+5
131(1+0.013s)
s2 +8.94s+100
CL poles
−1 ± j2
−4.47 ± j8.94, −5.59
−0.955 ± j1.979, −0.104
CL zeros
∞, ∞
−4.47, ∞, ∞
−0.1, ∞, ∞
0.4
0.045
0.05
1/Kv
−
1.71
s+5.59
+
−0.004
s+0.104
• Lag design retains similar CL poles to prop. design,
plus a “slow” pole
• CL poles of lead design quite different
• Lead and lag meet Kv specification (1/Kv = ess,ramp )
EE 3CL4, §6
51 / 63
Tim Davidson
Compensators
Lead
compensation
Design via Root
Locus
Lead Compensator
example
Cascade
compensation
and
steady-state
errors
Lag
Compensation
Design via Root
Locus
Lag compensator
example
Prop. vs Lead
vs Lag
Concluding
Insights
Ramp response
EE 3CL4, §6
52 / 63
Tim Davidson
Compensators
Lead
compensation
Design via Root
Locus
Lead Compensator
example
Cascade
compensation
and
steady-state
errors
Lag
Compensation
Design via Root
Locus
Lag compensator
example
Prop. vs Lead
vs Lag
Concluding
Insights
Ramp response, detail
EE 3CL4, §6
53 / 63
Tim Davidson
Compensators
Lead
compensation
Design via Root
Locus
Lead Compensator
example
Cascade
compensation
and
steady-state
errors
Lag
Compensation
Design via Root
Locus
Lag compensator
example
Prop. vs Lead
vs Lag
Concluding
Insights
Step response
EE 3CL4, §6
54 / 63
Tim Davidson
Compensators
Lead
compensation
Design via Root
Locus
Lead Compensator
example
Cascade
compensation
and
steady-state
errors
Lag
Compensation
Design via Root
Locus
Lag compensator
example
Prop. vs Lead
vs Lag
Concluding
Insights
Step response, detail
EE 3CL4, §6
55 / 63
Tim Davidson
Compensators
Lead
compensation
Design via Root
Locus
Lead Compensator
example
Cascade
compensation
and
steady-state
errors
Lag
Compensation
Design via Root
Locus
Lag compensator
example
Prop. vs Lead
vs Lag
Concluding
Insights
Anything else to consider?
EE 3CL4, §6
56 / 63
Anything else to consider?
Tim Davidson
Compensators
Lead
compensation
Design via Root
Locus
Lead Compensator
example
Cascade
compensation
and
steady-state
errors
Lag
Compensation
With H(s) = 1,
Y (s) =
Design via Root
Locus
Lag compensator
example
Prop. vs Lead
vs Lag
Concluding
Insights
E(s) =
Gc (s)G(s)
G(s)
R(s) +
Td (s)
1 + Gc (s)G(s)
1 + Gc (s)G(s)
Gc (s)G(s)
−
N(s)
1 + Gc (s)G(s)
1
G(s)
R(s) −
Td (s)
1 + Gc (s)G(s)
1 + Gc (s)G(s)
Gc (s)G(s)
+
N(s)
1 + Gc (s)G(s)
EE 3CL4, §6
57 / 63
Tim Davidson
Compensators
Lead
compensation
Design via Root
Locus
Lead Compensator
example
Cascade
compensation
and
steady-state
errors
Lag
Compensation
Design via Root
Locus
Lag compensator
example
Prop. vs Lead
vs Lag
Concluding
Insights
Response to step disturbance
EE 3CL4, §6
58 / 63
Tim Davidson
Compensators
Lead
compensation
Design via Root
Locus
Lead Compensator
example
Cascade
compensation
and
steady-state
errors
Lag
Compensation
Design via Root
Locus
Lag compensator
example
Prop. vs Lead
vs Lag
Concluding
Insights
Response to step disturbance,
detail early
EE 3CL4, §6
59 / 63
Tim Davidson
Compensators
Response to step disturbance,
detail late
Lead
compensation
Design via Root
Locus
Lead Compensator
example
Cascade
compensation
and
steady-state
errors
Lag
Compensation
Design via Root
Locus
Lag compensator
example
Prop. vs Lead
vs Lag
Concluding
Insights
Homework: Show that ess for a step disturbance is 0.2,
0.0225 and 0.025 for prop., lead, lag, resp.
EE 3CL4, §6
60 / 63
Tim Davidson
Compensators
Lead
compensation
Design via Root
Locus
Lead Compensator
example
Cascade
compensation
and
steady-state
errors
Lag
Compensation
Design via Root
Locus
Lag compensator
example
Prop. vs Lead
vs Lag
Concluding
Insights
Error due to Gaussian sensor
noise
EE 3CL4, §6
61 / 63
Tim Davidson
Compensators
Lead
compensation
Design via Root
Locus
Lead Compensator
example
Cascade
compensation
and
steady-state
errors
Lag
Compensation
Design via Root
Locus
Lag compensator
example
Prop. vs Lead
vs Lag
Concluding
Insights
Bode diagram of
GC (s)G(s)/(1 + GC (s)G(s))
EE 3CL4, §6
63 / 63
Insights
Tim Davidson
Compensators
Lead
compensation
Design via Root
Locus
Lead Compensator
example
Cascade
compensation
and
steady-state
errors
Lag
Compensation
• If we would like to improve the transient performance of
a closed loop
• We can try to place the dominant closed-loop poles in
desired positions
• One approach to doing that is lead compensator design
• However, that typically requires the use of an amplifier
in the compensator, and hence requires a power supply
• Broadening of bandwidth improves transient
performance but exposes loop to noise
Design via Root
Locus
Lag compensator
example
Prop. vs Lead
vs Lag
Concluding
Insights
• If we would like to improve the steady-state error
performance of a closed loop without changing the
dominant transient features too much
• We can consider designing a lag compensator to
provide the required gain
• However, that typically produces a “weak” slow pole that
slows the decay to steady state