Chapter
p 2
RAM Functional Faults
Jin-Fu Li
Advanced Reliable Systems (ARES) Lab
Lab.
Dept. of Electrical Engineering
National Central University
Jhongli, Taiwan
Outline
•
•
•
•
•
Functional RAM Model
Reducing the Functional Model
Definition of Reduced Functional Faults
Fault Combinations
Fault
l Mapping
i
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2
Memory Testing
Fault modeling
Wafer
f b i ti
fabrication
Probe test
Test generation
Repair
Post-repair
Probe test
Die separation,
separation
packaging
Pre-BI Test
Fault simulation
Burn in
Burn-in
Final Test
DFT & DFM
Shipment
Test Preparation Phase
Test-Preparation
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Test Execution Phase
Test-Execution
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3
Memory Test Design
•
•
A memory test consists of a series of
measurements that applied
pp
by
yp
programmable
g
automatic test equipment (ATE) or built-in test
circuitry to unseparated dice or packaged ICs
Tests can be divided into the following four
categories
− DC parametric tests
∗ Measure static analog
g characteristics of the
device’s input/output interface
∗ E.g., measure the leakage current, static and
dynamic power supply current
current, output voltage
level, and so on
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4
Memory Test Design
− AC parametric tests
∗ Measure dynamic parameters of the device’s
i
input/output
t/ t t interface
i t f
∗ E.g., measure setup time, hold time, rise time, fall,
time, etc.
− Functional tests
∗ Also called Boolean tests, verify
y whether or not
the memory under test performs the correct logic
functions
− Dynamic tests
∗ Detect timing faults affecting internal deviceunder- test circuitry
y
∗ E.g., detect slow sense amplifier operation, slow
address decoder operation, etc.
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Functional RAM Model
address
address
latch
column decoder
rrow deco
oder
memory
cell array
write
it d
driver
i
read/write
ead/ te &
enable
sense amplifier
lifi
d t register
data
i t
data
out
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data
in
6
Reduced Functional Model
D
Data
Rea
ad/write
llogic
Mem
mory cell
array
a
Ad
ddress
De
ecoder
Ad
ddress
• The address latch, the row, and the columndecoder are combined to the address decoder
− They
y all concern addressing
g the right
g cell or word
• The write driver, the sense amplifier, and the
data register are combined to the read/write
logic
− They all concern the transport of data from and
to the memory cell array
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7
Reduced Functional Faults
• Stuck-at fault (SAF)
− Definition:
∗ The logic value of a stuck-at (SA) cell or line is
always 0 or 1.
∗ It is always
y in state 0 or in state 1 and cannot be
changed to the opposite state
− Detection requirement:
∗ From each cell or line
line, a 0 or 1 must be read
• Transition fault (TF)
− Definition:
fi i i
∗ A cell that fails to undergo a 0 to 1 transition when
it is written is said to contain an up transition fault
∗ A down transition fault indicates that a cell fails to
undergo a 1 to 0 transition
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Reduced Functional Faults
− A TF can be thought of as a set/reset (S/R)-type
flip-flop with a SAF on the set or reset input
SA0
S
Q
R
Q
− Detection requirement:
∗ Each cell should undergo up and down transitions
and be read after each transition before
undergoing further transitions
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9
State Diagram for SAFs & TFs
w1
w0
S0
w0
S1
w1
State diagram of a good cell
w1
w0
0
S0
w1
1 w0
0
S1
w1
1
w0
0
S0
w0
S1
w1
SA0 fault
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SA1 fault
TFu
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10
Reduced Functional Faults
• Coupling
C
li ffaults
l (CF
(CFs))
− 2-coupling faults
− Different types of CFs
∗ Inversion CF (CFin)
∗ Idempotent
Id
t t CF (CFid)
∗ State CF (CFst)
∗ Dynamic CF (CFd)
• CFin
− A 0 to
t 1 (or
( 1 to
t 0) transition
t
iti in
i one cell
ll inverts
i
t
the content of a second cell
− An CFin can be thought of as a D
D-type
type flip
flip-flop
flop
with an extra clock input Cd and the Q’ output
ttied
ed to the
t e D input,
put, as dep
depicted
cted in tthe
e following
o o
g
figure.
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11
Reduced Functional Faults
D
Cn
Cd
Q
Q
• CFid
− A 0 to 1 (or 1 to 0) transition in one cell forces the
content of a second cell to a certain value, 0 or 1.
− An idempotent
p
coupling
p g fault can be thought
g of
as an S/R-type flip-flop with an OR-gate in the
Set or Reset line, as depicted in the following
fig re Sn is the normal set inp
figure.
inputt whereas
hereas Sd is
the undesired set input due to coupling with one
or more other flip flops.
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Reduced Functional Faults
Sn
Sd
S
Q
Rn
R
Q
• CFst
− A 0 or 1 state in one cell forces the content of a
second cell to a certain value, 0 or 1.
− It can be thought
g of as a D-type
yp flip-flop
p
p with an
OR/AND-gate in the data line (D), as depicted in
the following figure. Dn is the normal set input
whereas
hereas Dd is the undesired
ndesired set inp
inputt d
due
e to
coupling with one or more other flip flops.
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13
Reduced Functional Faults
Dn
Dd
D
clk
Q
Q
• Dynamic Coupling Fault (CFd)
− Occur between cells in different words
words. A read or
write operation on one cell forces the content of
the second cell either 0 or 1.
− Denoted as <rx|wy; z> where | denotes the or of
the read and write operations
− Four possible CFd faults
∗ <r0|w0;0>, <r0|w0;1>,<r1|w1;0>, and <r1|w1;1>
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14
State Diagrams for CFin & CFid
w1/j
w0/i,
w0/j
w0/i
1/i
w1/i,
w0/j
S00
S01
w0/j
w0/i
w1/i
w1/jj
S10
S11
w0/j
w0/i,
w1/j
w1/i
w1/i,
w1/i
w1/j
State diagram of two good cells
w0/i,
w0/jj
w0/i
S00
w0/j
w1/j
1/j
w1/i
S01
w0/i,
w1/jj
w0/i,
w0/jj
S00
S10
w0/i
w0/j
w0/i
w1/i
S11
w1/i,
w1/j
w1/i,
w0/j
State diagram of an CFin<u;i>
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S01
w0/i,
w1/j
w1/j
w0/i
w1/i
w1/j/j
w1/i,
w0/j
w0/j
S10
w1/j
w0/j
S11
w1/i
w1/i,
1/i
w1/j
State diagram of an CFid<u;1>
Jin-Fu Li
15
State Diagrams for CFst & TF
w1/j
w0/i,
w0/j
w0/i
1/i
w1/i,
w0/j
S00
w0/j
w0/i
w1/i
w1/jj
S10
S01
w0/j
S11
w0/i,
w1/j
w1/i
w1/i,
w1/i
w1/j
State diagram of two good cells
w0/i,
w0/j
w0/j
S00
w1/j
S01
w0/i,
w1/j
w0/i,
w0/j
S00
w1/j
w0/i
w1/i,
w0/j
w0/i
w1/i
S10
w1/j
1/j
w0/j
S11
w1/i w1/i
w1/i
w0/i
w1/i,
w1/j
State diagram of a CFst<1;1>
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w0/j
w0/i,
w1/j
S01
w1/i,
w0/j
w0/i
S10
w1/j
1/j
w0/j
S11
w1/i,
w1/j
State diagram of TFu & TFd
Jin-Fu Li
16
Summary of CFs
• Note that all definitions talk abo
aboutt single
single-way
a
faults, that is, the presence of a CF from cell i to
cell j does not imply the presence of a CF from
cell j to cell i.
• Suppose that
h a transition or state in cell
ll j can
induce a coupling fault in cell i. Cell i is then said
t be
to
b coupled
l d cellll ((or victim
i ti );
) cell
ll j iis called
ll d th
the
coupling cell (or aggressor).
• A test that has to detect and locate all coupling
faults should satisfy
− For all coupled cells, each cell should be read
after a series of possible coupling faults may
h
have
occurred
d
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17
NPSFs
• Neighborhood Pattern Sensitive Fault (NPSF)
− A subset of the Pattern Sensitive Fault (PSF)
• PSF is defined as follows:
− The contents of a cell is affected by the contents
of a group of cells
• Th
The PSF iis th
the mostt generall k-coupling
k
li ffault
lt,
where k=n (all of the memory)
• In the PSF, the neighborhood could be
anywhere
y
in the memory
y array,
y whereas in a
NPSF, the neighborhood must be in a single
position surrounding the base cell
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18
NPSFs
• Neighborhood
N i hb h d P
Pattern S
Sensitive
ii F
Fault
l (NPSF)
− Type-1 neighborhood
Base cell
Deleted
neighborhood
1
0
2
3
4
− Type-2
yp
neighborhood
g
0
3
6
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1
4
7
2
5
8
19
Types of NPSFs
• Three types of NPSFs
− Active NPSF (ANPSF)
− Passive NPSF (PNPSF)
− Static NPSF (SNPSF)
• ANPSF
− The
Th base
b
cell
ll changes
h
d
due to a change
h
in
i the
h
pattern of the deleted neighborhood
− An
A ANPSF ttestt has
h this
thi necessary condition
diti
∗ Each base cell must be read in state 0 and state 1,
for all possible deleted neighborhood pattern
changes
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20
Types of NPSFs
• PNPSF
− A specific neighborhood pattern prevents the
base cell from changing
− The necessary condition to detect and locate a
PNPSF
∗ Each base cell must be written and read in state 0
and in state 1, for all deleted neighborhood
pattern permutations
• SNPSF
− The base cell is forced into a particular state
when the deleted neighborhood contains a
particular p
p
pattern
− The necessary condition of test is
∗ Each base cell must be read in state 0 and in state
1 for all deleted neighborhood pattern
1,
permutations
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21
Relation Between Faults & Defects
Vdd
R
R
d1
d5
d7
d4
•
Defect
D
f t d1 (inverse
(i
node
d shorted
h t d to
t
Vdd) causes a SA0 fault
•
Defect d2 (true node shorted to Vss)
causes a SA0 fault
•
Defect d3 (open true node gate)
cause a SA1 fault
•
Defect d4 (an open word line)
causes all cells after the WL fault to
be inaccessible (AF)
•
Defect
D
f t d5 (a
( short
h t between
b t
the
th true
t
node and BL) will pull BL down if the
cell contains a 0, but will not affect
BL if the cell contains 1. This is the
state coupling fault <0;0>
•
Defect d6 (short between inverse
node and BL’) is similar, as is the
state coupling
li ffault
l <1;1>
11
•
Defect d7 (open BL’) prevents cells
after the open defect from passing
a logic
l i 1 value
l on BL’
WL
d6
d3 d2
BL
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Vss
BL
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22
Relation Between Faults & Defects
•
Vdd
R
•
R
d3
d1
d2
BL
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WL
•
Defect d1 (a word line connected to
Vss) causes all cells in the word line
to be stuck open.
A defect in the poly silicon layer
covering a diffusion region may
result in the creation of an extra
pass transistor.
i
This
hi d
defect
f
(d
d2)
causes a transition fault.
Defect d3 ((a broken pull
p up
p resistor))
introduces a data retention fault. If
the cell is not accessed, the cell
node with the broken pull up
Vss
resistor
i t can b
be fl
floating
ti hi
high
h or
active low. If the node is floating
BL
high, the leakage current from the
cell node to the substrate will
decline the voltage at the node. If
the node voltage passes the
g Vth the data in the
threshold voltage
cell will invert. If the node is active
low, the cell will function correctly.
Jin-Fu Li
23
Relation Between Faults & Defects
•
WL
d2
•
•
WL
d1
d3
d4
WL
d5
BL
BL
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d6
•
•
BL
•
Defect
D
f t d1 (a
( short
h t between
b t
two
t
WLs)
WL )
results in an AND bridging fault
between pairs of cells located in the
same column for the two shorted
WLs
Defect d2 (a capacitor-WL short)
causes a SA1 fault
Defect d3 (a short between two
capacitors) causes a state coupling
f lt
fault
Defect d4 (a shorted capacitor) is a
SA0 fault
Defect d5 (a short between
capacitor and BL) is an AND
g g fault with all cells in the
bridging
same column
Defect d6 (a short between two
neighboring BLs) causes an AND
bridging fault between pairs of cells
Jin-Fu on
Li the same word line and on the 24
shorted bit lines
Design Dependent Conditions
•
pre
charge
row
select
•
col
select
•
WE
RE
data
latch
OE
I/O pin
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Detection of all faults is only assured
if the R/W logic is transparent for all
y
faults in the cell array.
Suppose a cell is SA0. When the cell is
read, the sense amplifier in the R/W
logic
og c will interpret
te p et this
t s as a logic
og c 0.
The fault is thus detected as SA0 at
the output pin and the R/W logic is
transparent for SA0 faults.
Suppose a cell is stuck open, i.e., the
cell is not accessible. When the cell is
read, the sense amplifier
p
in the R/W
logic will detect that both bit lines are
high (due to the preceded bit line
precharge). It is not clear what value
the sense amplifier will pass to the
output pin. The transparency of the
R/W logic for stuck-open faults
depends on the design of the sense
amplifier.
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25
•
Fault Combinations
The test engineer
Th
i
has
h assumed
d that
h a certain
i
complicated functional fault (such as CF) is likely to
occur
− It is not only assumed that any number of faults of that
particular type can occur but also that any number of
f lt off a more simple
faults
i
l ffunctional
ti
l ffault
lt ttype ((such
h as SAF
SAFs))
can occur
•
When multiple faults occur
occur, these faults can be linked or
•
Linked faults
unlinked
− A fault is linked when that fault influences the behavior of
other faults
•
∗ May cause the fault masking effect
Unlinked faults
− A fault is unlinked when that fault does not influence the
behavior of other faults Jin-Fu Li
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26
•
Fault Combinations
For example,
F
l suppose there
h
are ffour CF
CFs iin a memory as
in the following figure
<u;1> <d;0>
<d;1>
<u;0>
U li k d ffaults
Unlinked
lt
i
j
k
l
m
n
<u;1> <d;0>
<d;1>
<u;0>
i
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m
k
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Linked faults
j=l=n
27
Fault Combinations
fault combinations
single fault
multiple fault
unlinked
linked
same fault
class
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different fault
class
28
Linked Faults of the Same Class
• SAF
− A SAF involves only one cell, and only one SAF
• TF
can occur in
i any one cell.
ll B
Because only
l one cell
ll iis
involved, a SAF is inherently unlinked.
− A TF involves only one cell, and at most two
different transition
diff
i i ffaults
l can occur iin any one
cell (TFu and TFd). Because only one cell, a TF
cannot be linked to another TF.
TF
• CF
− With a CF (of the 2-coupling type) two cells per
fault are involved. The case of multiple faults will
be analyzed by considering two faults
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29
Linked Faults of the Same Class
• These two faults can have the following
relationships:
− All four cells are different:
− The coupling cell of one of the faults is the
coupled cell of the other fault, whereas the other
two cells
ll are diff
different
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30
Linked Faults of the Same Class
− The coupling cell of the first fault is the coupled
cell of the other fault, and, vice versa, the
coupling
li
cell
ll off th
the second
d ffault
lt iis th
the coupled
l d
cell of the first fault
− The coupled cells are the same cell, whereas the
coupling cells are different
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31
Linked Faults of the Same Class
− The coupling cells are the same cell, whereas the coupled
cells are different
− The coupled cells are the same cell, and the coupling cells
are the same cell
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32
Fault Mapping
• A reduced functional model has been defined
consisting
g of three blocks:
− The address decoder, the memory cell array, and the
read/write logic
• When one wants to test a memory for SAFs,
three tests would be necessary
y
− One test that detects SAFs in the address decoder
− One test that detects SAFs in the memory
y cell array
y
− One test that detects SAFs in the read/write logic
• Most faults occurring in the read/write logic and
the address decoder can be mapped to faults in
the memory cell array
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33
Fault Mapping
• Mapping read/write logic faults into memory
array faults
− A test that detects SAFs in the memory array will
also detect SAFs in the read/write logic
∗ A SAF in
i the
th read/write
d/ it logic
l i will
ill appear as a llarge
group of cells stuck-at faults
− The same arguments are valid for TFs and CFs
• For NPSFs, this cannot be proven generally
− A test that detects NPSFs in the memory cell
array will also detect NPSFs in the read/write
logic under the condition
∗ Each neighborhood in the data register is a subset
of a neighborhood
g
in the cells of the memory
y cell
array
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34
•
Fault Mapping
For example
− A test for defecting Type 1 NPSFs can also detect the
neighborhood faults in data register
− A test for detecting column neighborhood faults can not
detect the neighborhood faults in the data register
Type 1 neighborhood
Column neighborhood
w2
x2
b2
z2
y2
x1
b1
z1
w4
w5
w6
x4
x5
x6
b4
b5
b6
y4
y5
y6
z4
z5
z6
u3
b3
v3
Data register
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35
•
•
•
Address Decoder Faults
An address decoder fault (AF) represents an
address decoding error
Assumptions
− The decoder logic
g does not become sequential
− The fault is the same during both read and write
operations
AFs can be classified into four cases
− Fault 1: no cell is accessed for a certain address
− Fault 2: no address can access a certain cell
− Fault 3: with a particular address, multiple cells
are simultaneously accessed
− Fault 4: a particular cell can be accessed with
multiple addresses
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36
Address Decoder Faults
Cx Ax
Ax
Cx Ax
Fault 1
Fault 2
Cx
Cy Ay
Fault 3
Fault 4
Address decoder faults
Ax
Ax
Cx Ax
Cx Ax
Cx
Cx Ay
Cy Ay
Cy Ay
Cy
Fault A (1+2)
Fault B(1+3)
Fault C(2+4)
Fault D (3+4)
Combinations of AFs that must be tested
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37
Address Decoder Faults
•
•
•
Fault A & fault B are inherently unlinked
− It is impossible to mask the fault occurring when
one reads Ax
Fault C & fault D may be linked
− It is possible that writing in Ax masks the fault
that occurred when Cx was erroneously
y written
through
h
h Ay
Therefore,, fault C & fault D are extended to the
general case, with more than two addresses
− See the figure shown in the next page
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38
Address Decoder Faults
Av
Cv Av
Cv
Aw
Cw Aw
Cw
Ax
Cx Av
Cv
Ax
Cx Ax
Cx
Ay
Cy Aw
Cw
Ay
Cy Ay
Cy
Az
Cz Ax
Cx
Az
Cz Az
Cz
Fault
au t C
Fault
au t D1
Fault
au t D2
Fault
au t D3
Note that any number of cells and addresses with the same fault can be
inserted between v and w and between y and z.
z
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39
•
Address Decoder Faults
If multiple cells are accessed simultaneously with
a single address, as in fault D, a read operation
can yield one of the following two results
− All addressed cells have the same contents
− Not all addressed cells have the same contents Two
•
cases can be distinguished
∗ The memory returns a value that is a deterministic
function of the contents of all addresses cells
∗ The memory returns a random or pseudorandom
result
In general, it is safest for AF tests to expect the
memory to return a random value, except for the
case in
i which
hi h all
ll cells
ll contain
t i th
the same value
l
− The tests should be designed such that they are not
influenced by random results
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40
Specific Address Decoder Fault
•
•
•
•
The address decoder can be implemented with
different technologies
g
− NMOS, CMOS, etc.
Open defects in NMOS logic can be mapped to
SAFs
Only a subset of open defects in CMOS logic
can be mapped to SAFs
A subset of open defects in CMOS logic causes
sequential
q
behavior in logic
g circuit
− These defects in address decoders can not be
detected by
y conventional tests
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41
•
Specific Address Decoder Fault
O
Open
defects
d f
in
i NMOS llogic
i
A
B
•
1
Out
Stuck-open
Open defects in CMOS logic
0 1
0 0
Stuck-open
Stuck
open
A
B
C
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0 1/0
42
Specific Address Decoder Fault
•
A graphical representation of the open defects causing
sequential fault behaviors
A2 A1 A0
Let the PMOS connected to A7
has a stuck-open defect
Column decoder
111
A6
A5
A4
A3
00100
Row decoder
A7
00110
10110
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X
Y
Z
Jin-Fu Li
1.
Write address Z(10110 111)
with logic 1
2.
Write address X(00100 111)
with logic 0
3
3.
Read address Z: result is
logic 1, that is correct
4.
Write address Y(00110 111)
with logic 0
5.
Read address Z: result is
logic 0, that is wrong!
43
Specific Faults for Multi-Port RAMs
•
•
•
The memory cell array faults can be detected as
the single
single-port
port RAMs
Multi-port RAM specific faults should be
covered
− Inter-port faults
− Intra-port
I t
t faults
f lt
To reduce the test complexity,
p
y, usually,
y, the
testing of inter-port and intra-port faults is
based on the following assumption
− Physical layout is known
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44
References
•
•
•
•
•
[1] A. J. van de Goor and C. A. Verruijt,”An Overview of Deterministic
Functional RAM Chip Testing”, ACM Computing Surveys, vol. 22, no. 1,
March 1990.
[2] A.
A K.
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National Central University
Jin-Fu Li
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