Contents
Features ...........................................................1
Pin Assignment ................................................1
Block Diagram..................................................2
Absolute Maximum Ratings .............................2
Recommended Operating Conditions..............2
Pin capacitance................................................2
UC
T
DC Electrical Characteristics............................3
Data Hold Characteristics ................................3
AC Electrical Characteristics............................4
OD
Instruction Set ..................................................5
Operation .........................................................6
Interface with CPU with Serial Port ..................9
Characteristics ...............................................12
DI
SC
ON
TI
NU
E
D
Dimensions ....................................................16
PR
Ordering Information ......................................11
Rev.1.1
S-24 Series
SERIAL NON-VOLATILE RAM
The S-24 Series is a non-volatile CMOS RAM, composed of a CMOS
static RAM and a non-volatile electrically erasable and programmable
2
memory (E PROM) to backup the SRAM. The organization is 16word×16-bit (total 256 bits) for the S-24H45 and the S-24S45, and 8word×8-bit (total 64 bits) for the S-24H30 and the S-24S30.
OD
NU
E
D
PR
• 256 bits
S-24H45 : TTL input, compatible with the X2444 of Xicor
S-24S45 : Schmitt input for STORE and RECALL pins
• 64 bits
S-24H30 : TTL input
S-24S30 : Schmitt input for STORE and RECALL pins
• Non-volatile functions can be controlled by software and hardware
• Erroneous store protection :≅3.5 V
• All inputs and outputs are compatible with TTL
* Except STORE and RECALL pins for the S-24S Series
• +5-V single power supply (+5 V±10%)
• Low current consumption
Operating : 5 mA typ.
Standby : 1 µA max.
• E2PROM store cycles : 105 times
• E2PROM data retention: 10 years
• 8-pin DIP/SOP package
UC
T
n Features
8-pin DIP
Top view
1
8
SK
2
7
DI
3
6
DO
4
VCC
STORE
RECALL
DI
5
8-pin SOP
Top view
STORE
VCC
1
2
8
7
RECALL
GND
CE
SK
3
4
6
5
DO
DI
GND
SC
CE
ON
TI
n Pin Assignment
CE
SK
DI
DO
RECALL
STORE
GND
VCC
Chip enable
Serial clock
Serial data input
Serial data output
Recall
Store
Ground
Power supply voltage (+5 V)
Figure 1
Seiko Instruments Inc.
1
SERIAL NON-VOLATILE RAM
S-24 Series
n Block Diagram
Non-volatile E2PROM
Memory Array
Store
Recall
Row
Decoder
RECALL
Control Logic
Static RAM
STORE
Column
Decoder
Instruction
Decoder
DO
OD
Instruction
Register
Counter
Figure 2
n Absolute Maximum Ratings
D
Table 1
PR
CE
DI
SK
UC
T
VCC
GND
Symbol
NU
E
Parameter
VCC
VIN
VOUT
Tbias
Tstg
ON
TI
Power supply voltage
Input voltage
Output voltage
Storage temperature under bias
Storage temperature
Ratings
Unit
-0.3 to +6.0
-0.3 to VCC+0.3
0.0 to VCC
-50 to+95
-65 to+150
V
V
V
°C
°C
n Recommended Operating Conditions
Parameter
VCC
VIH
SC
Power supply voltage
High level input voltage 1
Symbol
DI
High level input voltage 2
Low level input voltage 1
Low level input voltage 2
Operating temperature
VIHS
VIL
VILS
Topr
Table 2
Conditions
S-24H Series : All inputs
S-24S Series : CE, SK and DI
S-24S Series : STORE and RECALL
S-24H Series : All inputs
S-24S Series : CE, SK and DI
S-24S Series : STORE and RECALL
Min.
Typ.
Max.
Unit
4.5
2.0
5.0

5.5
VCC
V
V
3.4
0.0


VCC
0.8
V
V
0.0
-40


0.8
+85
V
°C
n Pin Capacitance
Table 3
(Ta=25°C, f=1.0 MHz, VCC=5 V)
Parameter
Input capacitance
Output capacitance
2
Symbol
CIN
COUT
Conditions
VIN=0 V
VOUT=0 V
Seiko Instruments Inc.
Min.
Typ.
Max.
Unit




6
8
pF
pF
SERIAL NON-VOLATILE RAM
S-24 Series
n DC Electrical Characteristics
Table 4
(Ta=-40°C to 85°C, VCC=+5 V±10%)
Symbol
High level output voltage
VOH
Store inhibition voltage
Schmitt width
VWI
VWD
Conditions
DO unloaded
All inputs are VCC
CE=GND, Other inputs are VCC
VIN =GND to VCC
VOUT =GND to VCC
CMOS : IOL=100 µA
TTL
: IOL=2.1 mA
CMOS : IOH=-100 µA
TTL
: IOH=-400 µA
S-24S Series : STORE and RECALL
n Data Hold Characteristics
Table 5
Symbol
VDH
tCDH
tR
Max
Unit
5


5
0.1
0.1




3.5

10
1
1
10
1
1
0.1
0.4


4.2

mA
µA
µA
mA
µA
µA
V
V
V
V
V
V
Min.
Typ.
Max
Unit
1.5
50
300



5.5


V
ns
ns
Conditions
CE≤0.2V, RECALL≥VCC-0.2V
D
Data hold voltage
Data hold setup time
Recovery time
Typ.








VCC -0.1
2.4

0.4
PR
Parameter
Min.
UC
T
ICC
ISL
ISB
ISTO
ILI
ILO
VOL
OD
Parameter
Operating current consumption
Sleep current
Standby current
Store current
Input leakage current
Output leakage current
Low level output voltage
4.5V
NU
E
Data hold mode
VCC
tCDH
CE
ON
TI
VIH
tR
VDH
VIL
GND
DI
SC
Figure 3 Data hold timing chart
Seiko Instruments Inc.
3
SERIAL NON-VOLATILE RAM
S-24 Series
n AC Electrical Chracteristics
Table 6 Measuring conditions
Parameter
Conditions
Input pulse voltage
S-24H Series : All inputs
S-24S Series : CE, SK and DI
S-24S Series : STORE and RECALL
0.0 to 3.0 V
0.0 to 4.0 V
10 ns
1.5 V
1TTL+100pF
1. Data input/output timing
Table 7
Min.
Typ.
fSK
tSKH
tSKL
tDS
tDH
tPD
tHZ
tCES
tCEH
tCDS

0.4
0.4
0.4
0.08


0.8
0.4
0.8










D
SK frequency
SK high level pulse width
SK low level pulse width
Input data setup time
Input data hold time
SK data valid time
Output disable time
CE setup time
CE hold time
CE deselect time
tCES
tSKH
SK
NU
E
CE
Max
Unit
1




0.3
1.0



MHz
µs
µs
µs
µs
µs
µs
µs
µs
µs
OD
Symbol
PR
Parameter
UC
T
Input pulse rise/fall time
I/O reference voltage
Output load
tCDS
tCEH
tSKL
tDS tDH
DI
Invalid data
tPD
•
•
tPD
Hi-Z
ON
TI
Hi-Z
DO
Invalid data
tHZ
Valid data
CE must be kept high during instructions.
When SK rises after selecting CE, the first 1 is taken into DI input and the fetch of an instruction
starts. All previous 0 is ignored.
Figure 4 Control data timing
Table 8
SC
2. Recall Cycle
Parameter
Symbol
Min.
Typ.
Max
Unit
tRCC
tRCP
tRCZ
tORC
tARC
2500
500

10








500

1000
ns
ns
ns
ns
ns
DI
Recall cycle time
Recall pulse width
Recall disable time
Recall enable time
Recall data access time
* Recall times are not limited.
tRCC
tRCP
tARC
RECALL
tRCZ
DO
Hi-Z
Figure 5 Hardware recall
4
Undefined data
tORC
Seiko Instruments Inc.
Valid data
SERIAL NON-VOLATILE RAM
S-24 Series
3. Store Cycle
Table 9
Parameter
Symbol
Min.
Typ.
Max
Unit
tST
tSTP
tSTZ

0.2




10

1.0
ms
µs
µs
Store time
Store pulse width
Store disable time
Store times: 105 times
Data retention : 10 years
STORE
tSTZ
Hi- Z
DO
n Instruction Set
1XXXX000
1XXXX100
1AAAA11X
1AAAA011
1XXXX001
1XXXX101
1XXXX010
Reset write enable latch (Disable write and store)
Set write enable latch (Enable write and store)
Read data from RAM address AAAA
Write data into RAM address AAAA
Store RAM data in E2PROM
Recall E2PROM data into RAM
Enter sleep mode
SC
ON
TI
Don’t care
Address bit
The format is composed of a start bit(1), address(A3 A2 A1 A0) and an instruction(I2 I1 I0).
Address A0 is “X” for the S-24H30 and the S-24S30.
DI
X:
A:
•
•
WRDS
WREN
READ
WRITE
STO
RCL
SLEEP
Function
D
Write enable latch reset
Write enable latch set
Read
Write
Store
Recall
Sleep
Symbol
NU
E
Instruction
PR
Table 10
Format
I2 I1 I0
OD
Figure 6 Hardware store
UC
T
tST
tSTP
Seiko Instruments Inc.
5
SERIAL NON-VOLATILE RAM
S-24 Series
n Operation
1. Internal latches
The S-24 Series has two latches, one of which controls write operation of the SRAM, and both of which control
permission/inhibition of store operation of the E2PROM.
1.1 Previous recall latch
The previous recall latch controls permission/inhibition of store operation of E2PROM. It is reset when the power is
turned on, and it inhibits store operation of the E2PROM. It is set by executing the software recall instruction or
hardware recall, and it permits store operation of the E2PROM.
UC
T
1.2 Write enable latch
The write enable latch controls permission/inhibition of both store operation of the E2PROM and write operation of the
SRAM. It is reset when the power is turned on or by executing WRDS instruction, and it inhibits both store operation of
the E2PROM and write operation of the SRAM.
It is set by executing WREN instruction, and it permits both store operation of the E2PROM and write operation of the
SRAM.
OD
When store operation of the E2PROM is completed, the write enable latch is automatically reset. Therefore, in order to
execute store operation again, it is necessary to execute WREN instruction and to set the write enable latch.
Set
Hardware recall operation
NU
E
Reset
Power-on
Previous
recall
latch
Set : permission
Reset : inhibition
D
Software recall instruction
PR
1.3 Both the previous recall latch and the write enable latch must be set for permission of store operation.
E2PROM
store
operation
control
Set
WREN instruction
Reset
ON
TI
Power-on
WRDS instruction
Store operation completed
Write enable
latch
Set : permission
Reset : inhibition
SRAM
write
operation
control
Figure 7 Internal latch
2. SRAM mode
DI
SC
2.1 Read
The data is read from the SRAM through READ instruction. Inputting a start bit, address and instruction code causes
data output on DO. In the S-24 Series, a bi-directional serial interface can be made by connecting DI and DO. See
Figures 8 and 9 for the timing.
2.2 Write
The data is written into the SRAM through WRITE instruction. Input data on DI after a start bit, address and instruction
code. See Figures 10 and 11 for the timing. The write enable latch must be set before WRITE instruction.
6
Seiko Instruments Inc.
SERIAL NON-VOLATILE RAM
S-24 Series
2
3. E PROM mode
Data is input to and output from the E2PROM through the SRAM.
3.1 Store
The SRAM data is copied into the E2PROM when STO instruction is executed or STORE goes low. The SRAM data
does not change after STO instruction. Since the data stored in the E2PROM is non-volatile, it is retained even if power
is turned off. In the case that store operation is performed while data is output on DO and during read operation of the
SRAM, DO becomes high-impedance. During store operation, all other operations are inhibited.
Both the previous recall latch and the write enable latch must be set before store operation.
UC
T
3.2 Recall
The E2PROM data is recopied into the SRAM when RECALL goes low or RCL instruction is executed. In the case that
recall operation is performed while data is output on DO and during read operation of SRAM, DO becomes highimpedance. During recall operation, all other operations are inhibited.
4. Sleep mode
OD
Executing SLEEP instruction disables operation of the SRAM. The E2PROM data is retained. The sleep mode can be
released by recall operation.
Since the S-24 Series is in standby status and the current consumption is low when CE is at GND level, it is not necessary to
execute SLEEP instruction in order to reduce the current consumption while not operating.
PR
5. Operation timing
After CE rose, when SK clock rises and DI goes high, a start bit is recognized and the fetch of an instruction starts. Data is
fetched to DI terminal at the rise of SK clock.
CE
SK
DI
1
2
1
A
3
4
A
A
5
A
6
1
7
1
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
X
Hi-Z
D0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
D0
Hi-Z
X : Don’t care
ON
TI
DO
NU
E
D
5.1 Read
D0 is output at the fall of the 8th clock, and others are output at the rise of the clock.
Figure 8 Read mode timing(S-24H45, S-24S45)
SK
1
1
2
A
DI
DI
SC
CE
DO
3
A
4
A
Hi-Z
5
X
6
1
7
1
8
9
10
11
12
13
14
15
16
X
D0
1
2
3
4
5
6
7
0
X : Don’t care
Figure 9 Read mode timing(S-24H30, S-24S30)
Seiko Instruments Inc.
7
SERIAL NON-VOLATILE RAM
S-24 Series
5.2 Write
Data is written to the SRAM at the rise of SK clock.
CE
1
SK
DI
1
2
A
3
A
4
A
5
6
A
7
0
8
1
9
1
D0
10
11
12
13
14
15
16
17
18
1
2
3
4
5
6
7
8
9
19
10
20
11
21
12
UC
T
Figure 10 Write mode timing(S-24H45, S-24S45)
CE
DI
1
2
A
3
A
4
A
5
6
X
0
7
1
8
1
9
D0
10
1
11
2
12
3
13
4
5.3 Other operation modes
CE must be low between instructions.
CE
1
X
3
X
4
5
6
X
X
I2
NU
E
DI
2
D
1
PR
Figure 11 Write mode timing(S-24H30, S-24S30)
SK
7
I1
8
I0
DI
SC
ON
TI
Figure 12 Other operation modes timing
8
14
5
OD
1
SK
Seiko Instruments Inc.
15
6
16
7
22
13
23
14
24
15
SERIAL NON-VOLATILE RAM
S-24 Series
n Interface with CPU with Serial Port
• When SK and DI are high at the rise of CE, high of DI is regarded as a start bit and the clock 1 generates and the high of DI is
fetched. When DI is low, DI is not regarded as a start bit until DI becomes high at the rise of SK.
• After power on or after an instruction is performed, DI must be set 1 for preparing the fetch of the start bit of the next
instruction.
Figures 13 to 17 show the timings of write/read, and other operation modes, and interfacing examples are shown in Figures 18 to
20.
CE
Fetch data
2
SK
DI
A
Start bit
3
Fetch CPU data
4
A
5
A
A
6
7
8
1
1
X
10
12
13
14
15
16
X
Hi-Z
DO
11
D0
1
2
3
4
5
17
18
19
20
21
22
UC
T
~CLK1
6
7
8
9
10
11
23
24
25
Hi-Z
12
13
14
15
D0
Hi-Z
Fetch CPU data
Need not to be fetched
OD
D15
dummy bit
Figure 13 Read mode timing(S-24H45, S-24S45)
CE
SK
DI
Start bit
Fetch CPU data
00
2
3
4
5
6
7
8
A
A
A
X
1
1
X
9
10
11
12
13
14
15
16
17
X
Hi-Z
D
Hi-Z
DO
PR
Fetch data
~CLK1
D0
1
2
NU
E
D7
dummy bit
3
4
5
6
7
0
Fetch CPU data
Need not to be fetched
Figure 14 Read mode timing(S-24H30, S-24S30)
~CLK1
4
A
A
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
D0
1
2
3
4
5
6
7
8
9
10
11
12
13
17
ON
TI
A
Start bit
Write to SRAM
3
A
0
1
1
X
24
14
25
15
Dummy bit
Figure 15 Write mode timing(S-24H45, S-24S45)
CE
SC
DI
Fetch data
2
SK
Fetch data
~CLK1
SK
DI
2
3
DI
CE
Start bit
A
A
Write to SRAM
4
5
6
7
A
X
0
1
8
1
9
00
10
X
D0
11
12
13
14
15
16
1
2
3
4
5
6
7
Dummy bit
Figure 16 Write mode timing(S-24H30, S-24S30)
Execute instruction
CE
Fetch data
~CLK1
SK
DI
Start bit
2
3
4
5
6
7
8
9
X
X
X
X
I2
I1
I0
X
Dummy bit:
Recommended to be set to 1 for fetching the
start bit of next instruction
Figure 17 Other operation mode timing
Seiko Instruments Inc.
9
SERIAL NON-VOLATILE RAM
S-24 Series
Interfacing example 1 : With Intel 8051, 8052
PX.X
CE
8051, 8052 P3.1
SK
STORE
DI
RECALL
P3.0
VCC
DO
GND
Figure 18
UC
T
Interfacing example 2 : With other CPU
When the S-24 Series is connected to CPU other than Intel 8051 and 8052, delay circuit should be set by a capacitor and a
resistor at DO terminal (Figure 19), delaying the signal more than 200 ns as in Figure 20 to assure the data hold time (tDHU)
and the data setup time (tDSU) of CPU.
VCC
SK
STORE
CPU
OD
CE
DI RECALL
PR
1kΩ
GND
DO
D
200pF
NU
E
Figure 19
tSK
tPD
SK
DO
Valid data
Valid data
DO
(with delay)
ON
TI
(without delay)
Valid data
tPD
Valid data
tDSU
tDHU
SC
Figure 20
The maximum speed of the SK clock (fSKMAX) is expressed by the following formula:
1
tSK
DI
fSKMAX=
=
1
tDSU+tDHU+tPD max.
For example, when interfacing with NEC µPD75XX series, fSKMAX is as follows:
µPD75XX series
tDSU
tDHU
S-24 Series
fSKMAX=
10
tPD
: 300 ns min.
: 450 ns min.
: 0 ns min. , 300 ns max.
1
tSK
=
1×109
300+450+300
=
Seiko Instruments Inc.
1
1.05 µs
= 952 kHz
SERIAL NON-VOLATILE RAM
S-24 Series
n Ordering Information
S-24X XX X X XX
: 105 times
10
Package
Blank : DIP
F
: SOP
Temperature
I
: −40°C to 85°C
Memory size
30
45
: 64-bit
: 256-bit
Input level
H
S
: All pins TTL compatible
: Schmitt input for STORE and RECALL pins
DI
SC
ON
TI
NU
E
D
PR
OD
UC
T
Rewriting times
Seiko Instruments Inc.
11
SERIAL NON-VOLATILE RAM
S-24 Series
n Characteristics
1. DC Characteristics
1.1 Operating current consumption ICC −
Ambient temperatureTa
1.2 Operating current consumption ICC −
Power supply voltage VCC
Ta=-40°C
6
VCC=5.5 V
6
ICC
(mA)
2
4
2
0
−40
0
0
85
1.3 Operating current consumption ICC −
SK frequency fSK
ISL/ISB
(µA)
VCC=5.5 V
0
−40
0
Ta=−40°C
ISTO
(mA)
2
4
5
DI
VCC (V)
1.7 Store inhibition voltage VWI −
Ambient temperature Ta
6
4
2
85
Ta (°C)
12
4
0
85
0
85
6
Ta (°C)
0
−40
0
Ta (°C)
SC
2
VWI
(V)
VCC=5.5 V
D
4
0
−40
0.5
1.6 Store current consumption ISTO −
Power supply voltage VCC
ON
TI
1.5 Store current consumption ISTO −
Ambient temperature Ta
NU
E
1M
fSK (Hz)
6
6
1.0
4
100k
5
OD
Ta=25°C
VCC=5.5 V
10k
4
1.4 Sleep/standby current consumption
ISL/ISB − Ambient temperature Ta
2
ISTO
(mA)
3
PR
ICC
(mA)
2
VCC (V)
Ta (°C)
6
UC
T
4
ICC
(mA)
Seiko Instruments Inc.
6
SERIAL NON-VOLATILE RAM
S-24 Series
1.8 Input voltage VIN − Ambient temperature Ta
S-24H Series : All inputs
S-24S Series : CE, SK and DI
1.9 Input voltage VIN − Power supply voltage VCC
S-24H Series : All inputs
S-24S Series : CE, SK and DI
Ta=85°C
VCC=4.5 V
2.0
2.0
VIN
(V)
VIN
(V)
1.5
−40
0
UC
T
1.5
4
85
Ta (°C)
1.10 Input voltage VIN − Ambient temperature Ta
S-24S Series : STORE and RECALL
OD
3
VIHS
2
PR
VIN
(V)
VILS
1
0
−40
0
85
NU
E
Ta (°C)
1.12 High level output current IOH −
Ambient temperature Ta
IOH
(mA) 5
0
SC
0
−40
VIHS
2
VILS
1
Ta=85°C
0
4
5
6
VCC (V)
1.13 Low level output current IOL −
Ambient temperature Ta
VCC=4.5 V
VOL=0.4V
10
ON
TI
VCC=4.5 V
VOH=2.4V
10
D
VCC=4.5 V
IOL
(mA) 5
0
−40
85
0
85
Ta (°C)
Ta (°C)
DI
1.14 High level output voltage VOH −
Ambient temperature Ta
1.15 Low level output voltage VOL −
Ambient temperature Ta
0.6
4.5
VCC=4.5 V
VOH
(V)
6
1.11 Input voltage VIN − Power supply voltage VCC
S-24S Series : STORE and RECALL
3
VIN
(V)
5
VCC (V)
VOL
(V)
4.0
VCC=4.5 V
0.4
0.2
3.5
−40
0
−40
85
0
85
Ta (°C)
Ta (°C)
Seiko Instruments Inc.
13
SERIAL NON-VOLATILE RAM
S-24 Series
2. AC Characteristics
2.1 SK pulse width tSK −
Ambient temperature Ta
2.2 SK pulse width tSK −
Power supply voltage VCC
1.0
1.0
Ta=85°C
VCC=4.5 V
tSK
(µs)
tSK
(µs)
0.5
0
−40
0
UC
T
0.5
0
85
Ta (°C)
5
OD
2.4 Input data hold time tDH −
Ambient temperature Ta
100
20
PR
VCC=4.5 V
tDH
(ns)
85
NU
E
0
D
50
0
−40
Ta (°C)
200
VCC=4.5 V
10
0
−40
0
85
Ta (°C)
2.6 Recall pulse width tRCP −
Ambient temperature Ta
ON
TI
2.5 SK data valid time tPD −
Ambient temperature Ta
100
VCC=4.5 V
tPD
(ns)
SC
100
0
−40
0
VCC=4.5 V
tRCP
(ns)
50
0
−40
85
0
DI
2.8 Store time tST −
Ambient temperature Ta
2.7 Recall cycle time tRCC −
Ambient temperature Ta
VCC=4.5 V
VCC=4.5 V
1.0
10
tRCC
(µs)
tST
(ms)
0.5
0−40
85
Ta (°C)
Ta (°C)
0
5
0
85
Ta (°C)
14
6
VCC (V)
2.3 Input data setup time tDS −
Ambient temperature Ta
tDS
(ns)
4
−40
0
85
Ta (°C)
Seiko Instruments Inc.
SERIAL NON-VOLATILE RAM
S-24 Series
3. Rewriting Characteristics
Ta=25°C
6
Minimum
store
voltage 4
(V)
10 102 103 104 105 106
SC
ON
TI
NU
E
D
PR
OD
Store cycle (times)
DI
0
UC
T
2
Seiko Instruments Inc.
15
8-pin SOP
FE008-B 990531
Dimensions
Unit:mm
5.0(5.15max)
5
1
4
0.15
+0.1
-0.05
NU
E
D
PR
OD
UC
T
8
0.35
DI
SC
ON
TI
1.27
+0.1
-0.05
DP00 -A 990531
8-pin DIP
Unit:mm
Dimensions
PR
OD
UC
T
9.3(9.6max)
1.5
7.62
ON
TI
NU
E
D
1.0
DI
SC
2.54
0.5±0.1
0.3
+0.1
-0.05
0°~15°
UC
T
OD
PR
D
NU
E
ON
TI
SC
•
•
DI
•
•
The information herein is subject to change without notice.
Seiko Instruments Inc. is not responsible for any problems caused by circuits or other diagrams
described herein whose industrial properties, patents or other rights belong to third parties. The
application circuit examples explain typical applications of the products, and do not guarantee any
mass-production design.
When the products described herein include Strategic Products (or Service) subject to regulations,
they should not be exported without authorization from the appropriate governmental authorities.
The products described herein cannot be used as part of any device or equipment which influences
the human body, such as physical exercise equipment, medical equipment, security system, gas
equipment, vehicle or airplane, without prior written permission of Seiko Instruments Inc.