Microprocessor Laboratory Asian Course on Advanced VLSI Design
Techniques using a Hardware Description Language
Manila, The Philippines
25 November – 13 December 2002
(Low Voltage) Analog Design
Manila, December 2002
Giovanni Anelli
CERN - European Organization for Nuclear Research
Experimental Physics Division
Microelectronics Group
CH-1211 Geneva 23 – Switzerland
Giovanni.Anelli@cern.ch
Instructions for use
This lecture deals with the basis of analog design.
I have decided to prepare the material in a rater “formal”
way, deriving almost all the necessary formulas.
This was done to try to give you some complete and
precise material for future reference.
We will not need to assimilate all the formulas today.
The important thing is that we recognize in each formula
which are the important parameters and trends.
Manila, December 2002
Giovanni Anelli, CERN
2
Analog design trade-offs
NOISE
LINEARITY
POWER
DISSIPATION
GAIN
ANALOG
DESIGN
OCTAGON
INPUT/OUTPUT
IMPEDANCE
SUPPLY
VOLTAGE
VOLTAGE
SWINGS
SPEED
Behzad Razavi, “CMOS Technology Characterization for Analog and RF Design", IEEE JSSC, vol. 34, no. 3, March 1999, p. 268.
Manila, December 2002
Giovanni Anelli, CERN
3
Outline
•
•
•
•
•
•
Single-stage amplifiers
The differential pair
The current mirror
Differential pair + active current mirror
Frequency analysis of an amplifier
Operational amplifier (op amp) design
B. Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill International Edition, 2001.
P.R. Gray, P.J. Hurst, S.H. Lewis, R.G. Meyer, Analysis and Design of Analog Integrated Circuits, J. Wiley & Sons, 4th edition, 2001.
R. Gregorian, Introduction to CMOS Op-Amps and Comparators, J. Wiley & Sons, 1999.
R.L. Geiger, P.E. Allen and N.R. Strader, VLSI Design Techniques for Analog and Digital Circuits, McGraw-Hill International Edition, 1990.
D.A. Johns and K. Martin, Analog Integrated Circuit Design, J. Wiley & Sons, 1997.
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4
Outline
• Single-stage amplifiers
¾
¾
¾
¾
¾
•
•
•
•
•
Common-source Stage
Common-drain Stage (Source Follower)
Common-gate Stage
Cascode Stage
Folded cascode Stage
The differential pair
The current mirror
Differential pair + active current mirror
Frequency analysis of an amplifier
Operational amplifier (op amp) design
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5
Common-Source Stage (CSS)
VDD
DC characteristic
RD
Small signal gain G
Vout
Vin
VDD R D
Vout
Small signal gain
(with channel length
modulation)
wVout
wVin
G
R D
E
( Vin VT )2
2n
E
( Vin VT )
n
gm r0 // R D gm
gmR D
r0R D
r0 R D
Small signal model in saturation
G
D
+
Vin
gmVGS
S
Manila, December 2002
Vout
RD
ro
Giovanni Anelli, CERN
The above results
could also have been
obtained directly from
the small signal model
6
CSS Simulation - DC
3
2.5E-02
2.5
1.5E-02
1.5
1.0E-02
1
Vout
Ids
gm
0.5
5.0E-03
0
IDS [ A ], g m [ S ]
2.0E-02
2
Vout [ V ]
W = 100 Pm
L = 0.5 Pm
R = 100 :
The maximum
small signal
gain is only
–1.8!!!
0.0E+00
0
0.5
1
1.5
2
2.5
Vin [ V ]
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CSS Simulation - DC
Increasing the value of the load resistor to 1 k: we have
3
1.2E-02
Vout
Ids
gm
1.0E-02
2
8.0E-03
1.5
6.0E-03
1
4.0E-03
0.5
2.0E-03
0
0.0E+00
0
0.5
1
1.5
2
IDS [ A ], g m [ S ]
Vout [ V ]
2.5
W = 100 Pm
L = 0.5 Pm
R = 1000 :
The maximum
small signal
gain is now
–9.6.
2.5
Vin [ V ]
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0.905
1.774
0.903
1.772
1.77
0.901
1.768
0.899
1.766
0.897
1.764
0.895
1.762
0
2
4
6
8
Ids [ mA ]
Vin [ V ]
CSS Simulation – Small Signal
10
0.905
0.738
0.903
0.736
0.734
0.901
0.732
0.899
0.73
0.897
0.728
0.895
0.726
0
2
4
6
8
gm = 9.6 mS
We inject at the input a
sinusoid with frequency 1 kHz,
peak to peak amplitude 1 mV
AND dc offset = 0.9 V.
The DC offset is important to
be in the right bias point.
V out [ V ]
Vin [ V ]
t [ ms ]
R = 1000 :
The input voltage is converted
in a current by the transistor
and then in a voltage again by
the resistor.
10
t [ ms ]
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Diode-connected transistor
A MOS transistor behaves as a small signal resistor when gate and
drain are shorted. A transistor in this configuration is referred to as
“diode-connected” transistor. The device is always in saturation.
To calculate the impedance of this device we use the small-signal
equivalent circuit and a test voltage generator (in red). The ratio
between the voltage vx applied and the current ix gives the impedance.
ix
G, D
ix
gm v x vx
r0
+
gmVGS
ro
vx
S
R
vx
ix
1
gm 1
r0
|
1
gm
The calculation show that the impedance is given by the parallel of two
resistors, 1/gm and r0.
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Diode-connected transistor
Impedance seen looking into the source.
VDD
G, D
ro
gmVGS
ix
S
+
vx
ix
gmbVBS
B
+
vx
ix
v
gm v x x gmb v x
r0
R
vx
ix
1
gm gmb 1
r0
|
1
gm gmb
In this case we have three resistances in parallel: 1/gm, 1/gmb and r0.
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Diode-connected transistor
Impedance seen looking into the drain with a resistor RS between the
source and ground.
G, D
ix
vx
ix
+
ro
gmVGS
gmbVBS
S
gm v x ixR S vx
B
RS
ix
+
RS
v x i xR S
gmbixR S
r0
R
vx
ix
§
1·
1 ¨¨ gm gmb ¸¸ ˜ R S
r0 ¹
1 gm gmb
©
|
˜ RS
1
g
g
m
m
gm r0
Without bulk effect (gmb) and the channel length modulation (r0) we
would see the series of 1/gm and RS. If RS = 0 we find again 1/gm.
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CSS with diode-connected load
VDD
Small signal gain
T2
G
Vout
Vin
T1
gm1 ˜
G
gm1 ˜ R out
1
gm2 gmb 2 1
1
r02 r01
|
gm1 ˜ (R D1 // R S 2 )
gm1
gm2
˜
gm2 gm2 gmb 2
For T1 and T2 in strong inversion G
1
˜
n2
1 gm1
˜
n2 gm2
W / L 1
W / L 2
The equations above can be obtained in three different ways:
• Using the results found for single transistors (as we have done)
• Starting from the DC equations and doing some mathematics (boring…)
• Using the small signal equivalent circuit (see next slide)
In an N-well CMOS process, the bulk contacts of all the NMOS are
connected together to ground (substrate). On the other hand, each bulk
contact of the PMOS (each well) can be connected to a desired signal.
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Small signal circuit
G2, D2
ro2
gm2VGS2
gmb2VBS2
v out
r01
i
gm1vin i
gm2 v out v out
gmb 2 v out
r02
S2, Vout
i
G1
D1
gm1vin
+
Vin
r01
gm1VGS1
S1
B1
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B2
G
v out
vin
Giovanni Anelli, CERN
§
1
1·
¸¸
v out ¨¨ gm2 gmb 2 r01 r02 ¹
©
gm1 ˜
1
gm2 gmb 2
1
1
r02 r01
14
CSS with diode-connected load
Substituting the NMOS load with a PMOS load, we get rid of the bulk effect.
VDD
Small signal gain
G
gm1 ˜
gm2
T2
Vout
Vin
In strong inversion, we have
T1
G
g
1
| m1
1
1
gm2
r02 r01
P n W / L 1
P p W / L 2
Drawbacks of this configuration:
• It is difficult to have high gain
• Vout_max = VDD – ~VGS2~.
• To have gain, (W/L)2 is made smaller than (W/L)1. This will limit the
maximum output voltage, since ~VGS2~will be quite higher than VT2.
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CSS with Current Source load
To increase the gain, we can use the output resistance of a transistor.
T2 provides the DC current bias to T1, and has a high output
impedance. The bias current is determined by Vb.
VDD
Vb
1
Small signal G g r // r g ˜
m1 01
02
m1
1
1
gain
r02
T2
Vout
Vin
T1
gm1 ˜
r01 ˜ r02
r01 r02
r01
This solution gives a much higher gain than the
other solutions and has a better DC output swing,
since Vout_max = VDD – ~VDS2_sat~ and Vout_min = VDS1_sat.
The output of the circuit shown is in an undefined state (highimpedance node). This circuit needs therefore an “external system” to
fix its output DC bias point (we need a feedback network!).
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CSS-CSL Simulation - DC
CSS-CSL = Common Source Stage with Current Source Load
Input Transistor
W1 = 100 Pm
L1 = 0.5 Pm
Load Transistor
3
1.2E-04
1.4E-03
2.5
1.0E-04
1.2E-03
2
8.0E-05
W2 = 800 Pm
L2 = 4 Pm
1
gm [ S ]
6.0E-05
1.5
IDS [ A ]
V out [ V ]
1.0E-03
8.0E-04
6.0E-04
4.0E-05
4.0E-04
Vout
0.5
2.0E-05
2.0E-04
Ids
0
0.0E+00
0
0.5
1
1.5
2
0.0E+00
2.5
0
Vin [ V ]
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0.5
1
1.5
2
2.5
Vin [ V ]
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17
CSS-CSL Simulation – Small Sign.
Small signal simulations
0.64
101
Vin [ V ]
100.8
0.636
100.7
0.634
100.6
0.632
100.5
0.63
100.4
0
2
4
6
8
Ids [ PA ]
100.9
0.638
0.638
1.5
1.4
0.636
1.3
0.634
1.2
0.632
1.1
0.63
1
0
2
4
6
8
V out [ V ]
Vin [ V ]
1.6
The DC offset is important to be in the
right bias point (especially for the
output!)
With a current of just 100 PA and the
same input transistor dimensions as in
the case of the CSS with load resistor,
we have a gain of –373.
10
t [ ms ]
0.64
We inject at the input a sinusoid with
frequency 1 kHz, peak to peak amplitude
1 mV and DC offset = 0.635 V.
N.B. The output current is smaller than
what it should be. The bias point is so
critical that the simulator has some
problems…
10
t [ ms ]
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CSS with Triode load
This circuit is the same as the CSS with Current Source load, but the
gate bias of transistor T2 is low enough to make sure that T2 works in
the linear region and therefore it behaves as a resistor.
VDD
Small signal gain
Vb
T2
Vout
Vin
G
T1
gm1 ˜
1
P PCox
W2
VDD Vb VTP L2
To have T2 in the linear region, we must have
Vb < Vout – VTP (where VTP is a positive number). If we
can not take Vb < 0 V, we can take it = 0 V. In this
case we must have Vout > VTP.
The principal drawback of this circuit is that the small-signal gain
depends on many parameters.
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CSS with Source Degeneration
VDD
RD
Vout
Vin
RS
In some applications, the square-law dependence of the
drain current upon the gate overdrive voltage
introduces excessive non linearity. RS “smoothes” this
effect since it takes a portion of the gate overdrive
voltage. At the limit, for RS >> 1/gm, the small signal
gain does not depend on gm (and therefore on IDS)
anymore.
It is interesting to note that the approximated small
signal gain (which can be easily calculated with the
small signal equivalent circuit) can also be calculated
as if RS and 1/gm were two resistors in series.
Small signal gain
(approximation)
Manila, December 2002
G
gm
˜ RD
1 gmR S
Giovanni Anelli, CERN
RD
1
RS
gm
20
CSS with Source Degeneration
The approximated small signal voltage gain can also be seen as the product of
the small signal equivalent transconductance of the degenerated CS Stage
multiplied by the total resistance seen at the output (RD).
To calculate the exact small signal voltage gain we need the exact small signal
equivalent transconductance and the output resistance of the degenerated CS
Stage. Both these quantities can be calculated with the equivalent small signal
circuits.
VDD
RD
Small signal gain
(approximation)
G
gm
˜ RD
1 gmR S
gm _ eq ˜ R D
Vout
Vin
RS
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Exact small signal
equivalent
gm _ eq
transconductance
(with channel length
modulation and bulk effect)
Giovanni Anelli, CERN
gmr0
R S r0 gm gmb ˜ R S ˜ r0
DO IT YOURSELF
AS AN EXERCISE!
21
CSS with Source Degeneration
Calculation of the output resistance of the degenerated CS Stage.
G
ix
Vin
D
ix
+
ro
gmVGS
vx
+
vx
S
RS
B
ix
gm v s R out _ CSS _ deg
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gmbVBS
vx vs
gmb v s
r0
vx
ix
RS
vs
i xR S
r0 R S gm gmb ˜ r0R S
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22
CSS with Source Degeneration
Exact small signal gain of the degenerated CS Stage.
VDD
Approximated small
signal gain
Gappr .
gm
˜ RD
1 gmR S
gm _ eq ˜ R D
RD
Vout
Vin
Output resistance of the
degenerated CS Stage
R out _ CSS _ deg
R out
R out _ CSS _ Deg // R D
r0 R S gm gmb ˜ r0R S
RS
Exact small signal gain
gm _ eq
G
gm _ eq ˜ R out
gmr0
R S r0 gm gmb ˜ R S ˜ r0
Exercise: try to obtain the same equation with the complete small signal circuit
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Source Follower (SF)
The analysis of the Common Source Stage (CSS) with current source load
demonstrated that to have a high voltage gain we have to have a high load
impedance. If we want to use a CSS to drive a low impedance load, we
have to put a “buffer” between the CSS and the load. The simplest buffer
is the Source Follower (also called Common Drain Stage).
VDD
How do we obtain the small signal gain? We could
use the small signal equivalent circuit or we can be
clever and reuse what we have seen up to now!
Vin
G
Vout
RS
G
Vout
Vin
§
·
1
¸¸
gm ˜ ¨¨ R S //
gm gmb 1/ r0 ¹
©
gm
gm gmb 1
1
r0 R S
gm ˜ R S
1 gm gmb ˜ R S
The gain of our buffer is never one! It is, in the best case, 1/n
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Source Follower (SF)
The Source Follower with a resistor is highly non linear, since the drain
current in T1 is a strong function of the input DC level.
We can therefore replace the resistor with a current source.
GSF _ NMOS
VDD
Vin
T1
Vout
Vb
T2
§
·
1
¸¸
gm1 ˜ ¨¨ r02 //
gm1 gmb1 1/ r01 ¹
©
gm1
gm1 gmb1 1/ r01 1/ r02
The gain is in this case close to 1/n (still not 1…).
The circuit is still non linear due to the body effect
(non linear dependence of VT1 upon the source
potential). This can be solved using a PMOS
Source Follower, in which both the transistors
have the body (well) connected to the source. In
this case, we have:
GSF _ PMOS
§
·
1
¸¸
gm1 ˜ ¨¨ r02 //
gm1 1/ r01 ¹
©
gm1
gm1 1/ r01 1/ r02
The gain can be in this case very close to one!
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25
Source Follower drawbacks
G
§
·
1
¸¸
gm1 ˜ ¨¨ R L // r02 //
gm1 1/ r01 ¹
©
VDD
G|
Vb
T2
Vout
Vin
RL
T1
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gm1
gm1 1/ R L
gm1
gm1 1/ r01 1/ r02 1/ R L
RL
R L 1/ gm
If the source follower has to drive a low
impedance, we risk to have a gain which is
significantly smaller than one. Another
important drawback is that source followers
shift the signal by one VGS. This is a
drawbacks especially in low voltage circuit,
where this causes a limitation in the voltage
headroom. On the other hand, if the power
supply voltage is high enough, source
followers can be used as voltage level shifters.
Giovanni Anelli, CERN
26
Common-Gate Stage (CGS)
In Common-Source Stages and Source Followers the input signal is applied to
the gate. We can also apply it to the source, obtaining what is called a
Common-Gate Stage (CGS)
VDD
R out
RD
Vout
Vb
R in
1 R D / r0
gm gmb r0
G
Vin
R out _ CGS // R D
G
R out
R in _ R D
RD
R in
R out _ CGS
R D r0
1 gm gmb ˜ r0
r0
EXERCISE!
r0 // R D ˜ gm gmb 1/ r0 0
RD ˜
r0 ˜ gm gmb 1
| gm ˜ n ˜ R D
R D r0
The input impedance of a CGS is relatively low, but this only if the load
impedance in low. The gain is slightly higher to the one of a CSS, since we
apply the signal to the source. N.B. We have calculated the small signal gain
using 2 different methods (red and blue). The results are identical!
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27
Common-Gate Stage (CGS)
With the results obtained, it is now very easy to study the most “general” case,
which includes the impedance RS of the signal source, the channel modulation effect
and the bulk effect. Let’s call Rin the resistance seen by the ideal voltage source.
VDD
R in
RD
G
Vout
Vb
RS
RS v out
v in
R D r0
1 gm gmb ˜ r0
RD
R in
Vin
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v out
1 gm gmb ˜ r0
RD ˜
R S ˜ >1 gm gmb ˜ r0 @ R D r0
This result is very similar to the one of a Common Source
Stage with source degeneration. The gain here is still
slightly higher due to the body effect. It is now also easy
to calculate the resistance seen into the output.
R out
+
v in
˜ RD
R in
R out _ CSS _ deg
R D // R out _ CSS _ deg
r0 R S gm gmb ˜ r0R S
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28
Cascode Stage (CascS)
The “cascade” of a Common-Source Stage (V-I converter) and of a
Common-Gate Stage is called a “Cascode”.
VDD
v out
RD
r01
v in ˜ gm1 ˜
˜ RD
R D r02
r01 1 gm2 gmb 2 ˜ r02
REMINDER
I
Vout
Vb
Vin
R1
T2
G
T1
gm1 ˜
r01
˜ R D | gm1R D
R D r02
r01 1 gm2 gmb 2 ˜ r02
I1
The gain is practically the same as in the
case of a Common-Source Stage.
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R2
R2
˜I
R1 R 2
29
Cascode Stage Output Resistance
One nice property of the cascode stage can be discovered looking at the
resistance seen in the drain of T2. This is quickly done if we look at T2 as
a Common-Source Stage with a degeneration resistor = r01.
Rout
R out _ CSS _ deg
Vb
Vin
T2
T1
R out _ CascS
r0 R S gm gmb ˜ r0R S
r01 r02 gm2 gmb 2 ˜ r01r02 | gm2 gmb2 ˜ r01r02
Compared to a CSS, the output impedance is
“boosted” by a factor (gm2 + gmb2) r02.
The disadvantage of the cascode configuration is that the minimum
output voltage is now the sum of the saturation voltages of T1 and T2.
It must therefore be used with care in low voltage circuits.
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30
CascS with current source load
To fully profit of the high output impedance of the cascode stage, it
seems natural to load it with a high impedance load, like a current source.
R out _ CascS
VDD
Vb1
R out
T3
Vout
Vb2
Vin
r01 r02 gm2 gmb2 ˜ r01r02
R out _ CascS // r03
G | gm1R out
T2
T1
If r03 is not high enough, we can use the cascode
principle to boost the output impedance of the
current source as well.
N.B. Remember that the DC output level here is not
well defined, and that we will need a feedback loop.
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31
Folded Cascode Stage (FCascS)
VDD
Vin
VDD
RD
T1
Ib
Vout
T2
Vb
Vin
T1
Vb
T2
Vout
Ib
RD
This solution is has a lower output impedance than the standard CascS
and consumes more current for the same performance.
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32
Outline
• Single-stage amplifiers
• The differential pair
¾ Differential signal advantages
¾ The differential pair
–
–
–
–
Common Mode Analysis
Large Signal Analysis
Small Signal Analysis
Common Mode Rejection Ratio (CMMR)
¾ Differential pair with MOS loads
¾ Differential Pair Mismatch
•
•
•
•
The current mirror
Differential pair + active current mirror
Frequency analysis of an amplifier
Operational amplifier (op amp) design
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33
Single-Ended vs Differential
A single-ended signal is defined as a signal measured with respect to a
fixed potential (usually, ground).
A differential signal is defined as a signal measured between two nodes
which have equal and opposite signal excursions. The “center” level in
differential signals is called the Common-Mode (CM) level.
The most important advantage of differential signals over single-ended
signals is the much higher immunity to “environmental” noise.
As an example, let’s suppose to have a disturbance on the power supply.
VDD
VDD
RD
Vout_SE
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RD
Vout +
Giovanni Anelli, CERN
RD
Vout -
34
Single-Ended vs Differential
The Common-Mode disturbances disappear in the differential output.
Vdd
Vout_SE = Vout +
Vout Vout_diff
Vout _ diff
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Vout Vout 35
Differential Pair (DP)
VDD
Vin1
RD
Vin,CM
RD
Vout1
Vin2
Vout2
Vout2
Vin1
Vin2
ISS
Vout,CM
Vout1
t
The current source has a very important function,
since it makes the sum of the currents in the two
v out ,CM
branches (I1 + I2= ISS) independent from the input
common mode voltage.
The output common mode voltage is then given by:
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Giovanni Anelli, CERN
VDD R D ˜
ISS
2
36
Differential Pair
VDD
VDD
Vout1
RD
Vout2
RD
Vout1
Vout2
Vin1
VDD - RD ISS
Vin1 - Vin2
Vin2
Vout1 - Vout2
RD ISS
ISS
N.B. The small signal gain is
the slope of this plot
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Giovanni Anelli, CERN
Vin1 - Vin2
- RD ISS
37
DP – Common mode analysis
To better understand what can be the maximum voltage excursion of the
input, we substitute the ideal current source with a real one.
VDD
vin,CM _ min
RD
VGS1 ( VGS3 VT 3 )
RD
vin,CM _ max
Vout1
Vin1
Vout2
T1
Vb
T2
T3
Vin2
ISS
§
·
VT 1 , VDD ¸
min ¨ VDD R D
2
©
¹
And what can be the maximum
excursion of the output?
v out _ min
VDS _ SAT1 VDS _ SAT 3
v out _ max
Manila, December 2002
VGS1 VDS _ SAT 3
Giovanni Anelli, CERN
VDD
38
DP - Large signal analysis
With the basic transistor equations, some patience and some mathematics we can
obtain the equation for the plot shown.
Vout1 - Vout2
vlim
RD ISS
Vlim
v out1 v out 2
2ISS
E /n
vin1 vin2
ID1 ID2
'Vin
'I
Vin1 - Vin2
- Vlim
'v out
- RD ISS
'I
For 'Vin vlim
For vlim 'Vin vlim
'I
Giovanni Anelli, CERN
R D ˜ 'I
ISS
E
4ISS
2
'Vin
'Vin
2n
E/n
'I
For 'Vin ! vlim
Manila, December 2002
'Vout
ISS
39
Differential pair transconductance
Deriving the current difference as a function of the input voltage
difference we obtain the transconductance Gm of the differential pair.
'I
Gm
ISS
- Vlim
Gm
Vlim
w'I
w'Vin
Manila, December 2002
'Vin
4ISS
2
2'Vin
E E /n
2n 4ISS
2
'Vin
E /n
'Vin
Vlim
- Vlim
'vin = 0
Giovanni Anelli, CERN
Gm
2E ISS
n 2
40
DP small signal gain
From the transconductance Gm of the differential pair when the differential
stage is balanced ('vin = 0), we obtain the small signal gain G.
Gm
2E ISS
n 2
'v out
G
'v out
'vin
R D ˜ 'I
R D ˜ Gm ˜ 'vin
2E ISS
RD ˜
n 2
The term circled in red looks suspiciously familiar to us…
It is the transconductance in strong inversion of a transistor carrying
a current ISS/2 ! So we can write
G
Manila, December 2002
R D ˜ gm
Giovanni Anelli, CERN
41
DP small signal gain
Now that we know it, is is quite obvious to recognize it looking again at
the circuit schematic.
VDD
RD
RD
Vout1
Vin1
Vout2
T1
Vb
T2
P
Vin2
We can see the circuit as two
common source stages with
degenerated resistor, and
superimpose the effects.
Or, even better, we can realize that
the point P is (ideally) AC grounded.
T3
v out1
gm ˜ R D ˜ vin1
v out 2
gm ˜ R D ˜ vin2
v out1 v out 2
Manila, December 2002
Giovanni Anelli, CERN
gm ˜ R D ˜ vin1 vin2 42
DP Common Mode gain
We have seen that ideally in a differential pair the output voltage does not depend
on the common mode input voltage. But in fact the non infinite output impedance
r03 of the current source has an influence, since the point P do not behave as an
AC ground anymore. The symmetry in this circuit suggests that we can see it as
two identical half circuits in parallel. This makes the analysis much easier.
VDD
VDD
RD
RD
Vout1
Vin1
RD
Vout2
T1
Vb
Manila, December 2002
T2
P
What do we have here?
A CSS with source
degeneration. Easy…
Vin2
Vout
Vin,CM
T1
GCM
v out
vin,CM
RD
1/ gm 2r0
2r03
T3
Giovanni Anelli, CERN
43
Common Mode Rejection Ratio
The variation of the common mode output voltage with the common mode input
voltage is generally small and not so worrying. MUCH MORE concerning is when
we have a differential output as a consequence of a common mode variation at
the input! This can happen if the circuit is not fully symmetric (mismatch!).
Let’s call GCM-DM the gain of this common-mode to differential-mode conversion.
A difference in the transconductances of the two transistors, for example, would
give:
'gm ˜ R D
GCMDM
gm1 gm2 r03 1
We see that it is essential to have a good current source (very high r03).
To make possible a meaningful comparison between different differential circuit,
we want to compare the undesirable differential output given by a common mode
input variation and the wanted differential output given by a differential input.
We define the Common Mode Rejection Ratio (CMRR) as:
CMRR
G
GCMDM
Taking into account ONLY the
g
transconductance mismatch, we obtain CMRR | m (1 2gmr03 )
'gm
Manila, December 2002
Giovanni Anelli, CERN
44
Differential Pair with MOS loads
To analyze the two circuits we can now make use of the half-circuit
concept and profit from all the results obtained up to now.
G
§ 1
·
g
gmN ¨¨
// r0N // r0P ¸¸ | mN
gmP
© gmP
¹
G
VDD
T3
VDD
T4
Vb
T1
T2
Vin2
Vin1
ISS
Manila, December 2002
T3
T4
Vb
Vout2
Vout1
Vout2
Vout1
Vin1
gmN r0N // r0P T1
T2
Vin2
ISS
Giovanni Anelli, CERN
45
Cascode Differential Pair
And, of course, the gain can be boosted using common-gate stages.
VDD
Vb3
T7
T8
Vb3
Vb2
T5
T6
Vb2
Vout1
Vb1
Vin1
T3
T4
T1
T2
G | gm1 gm3r03r01 // gm5r05r07 Vout2
Cascode stages were used a
lot in the past, when the
supply voltages were
relatively high (few volts).
Vin2
In deep submicron
technologies they are used
with more care.
Vb1
ISS
Manila, December 2002
Giovanni Anelli, CERN
46
Differential pair mismatch
The two transistors have the same drain current
9GS
V
2
'Vth
§ I
·
¨
¨
V 'E / E ¸¸
© gm
¹
2
22
'VGS
[mV ] 20
18
E /E
16
14
'VT
1 .4 %
4.5 mV
12
10
8
6
2I
'VT
4
2
0
1.E-02
1.E-01
1.E+00
1.E+01
1.E+02
1.E+03
I.C.
Manila, December 2002
Giovanni Anelli, CERN
47
Outline
• Single-stage amplifiers
• The differential pair
• The current mirror
¾
¾
¾
¾
¾
Standard Current Mirror
Cascode Current Mirror
Low-voltage Cascode Current Mirror
Current Mirror Output Impedance
Current Mirror Mismatch
• Differential pair + active current mirror
• Frequency analysis of an amplifier
• Operational amplifier (op amp) design
Manila, December 2002
Giovanni Anelli, CERN
48
Current mirror (CM)
We suppose that all the transistors have the same P, Cox and VT.
O is the same if the transistors have the same L
VDD
IREF
I1
I2
I1
WR
LR
W1
L1
W2
L2
W1
1 O 1VDS1 L
IREF ˜ 1
WR
1 O R VDSR LR
GND
To have an exact replica of the reference current, we have to make the
transistor identical AND they must have the same VDS. When this is not
possible, choosing long devices reduces the effect of O.
Precise current ratios can be obtained playing with the ratio between
the transistor widths (not the lengths!).
Manila, December 2002
Giovanni Anelli, CERN
49
Current mirror simulation
0.25 Pm technology, VDD = 2.5 V, IREF = 100 PA, WR = W1 = 100 Pm, LR = L1
0.12
@ VDS1 = 2.5 V
0.1
I1 [ mA ]
0.08
VDS1 _ min_ SI
2I1
PCoxn( W1 / L1 )
0.06
4nI t
VDS1 _ min_ WI
0.04
L = 10 um
L = 0.5 um
0.02
0
0
0.5
1
1.5
2
2.5
T1
L = 0.5
[Pm]
L = 10
[Pm]
ID [PA]
106
100.3
E [mA/V2]
60.54
2.488
gm [mS]
1.77
0.594
VT [mV]
635.7
635.6
VGS [mV]
636.7
943
VDS_sat [mV]
70.76
269.7
Rout [M:]
0.866
14.5
VDS1 [ V ]
Manila, December 2002
Giovanni Anelli, CERN
50
Cascode current mirror (CCM)
VG3 must be fixed so that VD1 = VD2.
I3
VDD
IREF
VD3
W3
L3
VG3
VD1
VD2
W1
L1
W2
L2
Making L1 = L2 and therefore having O1 = O2, we
obtain that the current I3 practically does not
depend on the voltage VD3. Of course, all the
devices must be in saturation (the circuit is
not suitable for low voltage applications).
I3
'VD2 |
W2 / L 2
IREF ˜
W1 / L1
gm3
'VP
gmb 3 ˜ r03
GND
Important: L3 can be different from L1 and L2.
How do we fix VG3 so that VD1 = VD2 ?
Manila, December 2002
Giovanni Anelli, CERN
51
Cascode current mirror (CCM)
VDD
Transistor 4 does the job here!
Transistors 1 & 2 decide the current ratio.
IREF
I3
Transistors 3 & 4 fix the bias VD1 = VD2.
VD3
W4
L4
W3
L3
VD1
VD2
W1
L1
W2
L2
GND
These results are valid even if transistors 3 &
4 suffer from body effect.
I3
W2 / L 2
IREF ˜
W1 / L1
W2 / L 2
W1 / L1
W3 / L 3
W4 / L 4
The problem of this current mirror is that VD3 > VDS3 + VGS2.
Manila, December 2002
Giovanni Anelli, CERN
52
Cascode current mirror simulation
0.25 Pm technology, VDD = 2.5 V, IREF = 100 PA
0.12
@ VD3 = 2.5 V
T2
T3
ID [PA]
100
100
0.08
E [mA/V2]
60.54
13.08
0.06
gm [mS]
1.676
1.211
VT [mV]
635.7
852
VGS [mV]
636.7
962.4
VDS_sat [mV]
70.75
128.7
Rout [M:]
0.108
1.037
I3 [ mA ]
0.1
W1 = W2 = 100 Pm
L1 = L2 = 0.5 Pm
W3 = W4 = 50 Pm
L3 = L4 = 1 Pm
0.04
0.02
0
0
0.5
1
1.5
2
2.5
VD3 [ V ]
Manila, December 2002
Giovanni Anelli, CERN
53
Low Voltage CCM (LVCCM)
VDD
IREF
I3
VD3
W4
VB
L4
VD1
W3
L3
VD2
W1
L1
GND
The main difference of this current mirror
compared to the standard cascode current
mirror is that here we can lower the voltages
VD1 and VD2 to the limit of the saturation of
transistors T1 and T2.
W2
L2
I3
W2 / L 2
IREF ˜
W1 / L1
W2 / L 2
W1 / L1
W3 / L 3
W4 / L 4
The minimum output voltage (VD3) here is just two saturation voltages.
Manila, December 2002
Giovanni Anelli, CERN
54
Low Voltage CCM simulation (1)
0.25 Pm technology, VDD = 2.5 V, IREF = 100 PA
@ VD3 = 2.5 V
0.12
T2
T3
ID [PA]
100
100
0.08
E [mA/V2]
60.5
13.57
0.06
gm [mS]
1.641
1.208
VT [mV]
635.7
692.4
VGS [mV]
642.5
798.3
VDS_sat [mV]
72.87
123.6
Rout [M:]
0.021
1.6
I3 [ mA ]
0.1
W1 = W2 = 100 Pm
L1 = L2 = 0.5 Pm
W3 = W4 = 50 Pm
L3 = L4 = 1 Pm
0.04
0.02
0
0
0.5
1
1.5
2
2.5
VD3 [ V ]
Manila, December 2002
Giovanni Anelli, CERN
55
Low Voltage CCM simulation (2)
0.12
VDD
0.1
IREF
I3 [ mA ]
0.08
I3
VD3
0.06
W4
VB
This plot shows that we
can lower the voltage
VB until it reaches the
limit VGS3 + VDS2_sat
0.04
0.02
L4
VD1
VD2
W1
L1
0
0.4
0.6
0.8
1
1.2
1.4
W3
L3
W2
L2
GND
VB [ V ]
Manila, December 2002
Giovanni Anelli, CERN
56
Current mirrors: comparison
0.12
IOUT [ mA ]
0.1
Vout_min
Precision
CM
VDS1_sat
Poor (unless large L)
CCM
VGS2 + VDS3_sat
Good
LVCCM
VDS2_sat + VDS3_sat
Good
0.08
0.06
0.04
CM - L = 1 um
0.02
LVCCM
CCM
0
0
0.5
1
1.5
2
2.5
VOUT [ V ]
Manila, December 2002
Giovanni Anelli, CERN
57
Current mirror output impedance
CCM
Standard CM
VDD
VDD
LVCCM
Vout
WR
LR
W1
L1
GND
rout
Manila, December 2002
W4
L4
W3
L3
W1
L1
W2
L2
GND
r01
Iout
Iout
Vout
Iout
Vout
IREF
IREF
IREF
VDD
rout
W4
L4
Vb
W1
L1
W3
L3
W2
L2
GND
r02 r03 gm3 gmb 3 ˜ r02r03
Giovanni Anelli, CERN
58
Current mirror mismatch
The two transistors have the same gate voltage
,,
,,
[%]
V
2
'E / E
·
§ gm
¨
V 'Vth ¸
¹
© I
14
12
E /E
10
I
2
'VT
1.4 %
4.5 mV
8
6
4
2
'E / E
0
1.E-02
1.E-01
1.E+00
1.E+01
1.E+02
1.E+03
I.C.
Manila, December 2002
Giovanni Anelli, CERN
59
Outline
•
•
•
•
Single-stage amplifiers
The differential pair
The current mirror
Differential pair + active current mirror
¾ Common mode, small signal and large signal analysis
¾ Noise
¾ Offset
• Frequency analysis of an amplifier
• Operational amplifier (op amp) design
Manila, December 2002
Giovanni Anelli, CERN
60
Differential Pair + Active CM
Current mirrors can also process a signal, and they can therefore be used
as active elements. A differential pair with an active current mirror is also
called a differential pair with active load. The current mirror here has also
the important role to make a differential to single-end conversion!
VDD
Common Mode Analysis
T3
T4
vin,CM _ min
Vout
T2
T1
Vin
vin,CM _ max
min VDD VGS3 VT 1 , VDD Maximum output excursion
v out _ min
Vb
VDS _ SAT 2 VDS _ SAT 5
T5
v out _ max
Manila, December 2002
VGS1 VDS _ SAT 5
Giovanni Anelli, CERN
VDD VDS _ SAT 4
61
Differential Pair + Active CM
Let’s now calculate the small-signal behavior, neglecting the bulk effect for
simplicity. The circuit is NOT symmetric, and therefore we can not use the halfcircuit principle here. As a first approximation, we can consider the common
sources of the input transistors as a virtual ground. The small-signal gain G can
be seen as the product of the total transconductance of the stage and of the
output resistance.
G Gm ˜ R out
VDD
v
v
iout gm1 in gm2 in gm1,2 ˜ vin
T3
T4
2
2
iout
iout
V
G
gm1,2
out
+
m
vin
vin
2
T1
T2
vin
2
G
ISS
Manila, December 2002
R out
Giovanni Anelli, CERN
r02 // r04
gm1,2 r02 // r04 62
Differential Pair + Active CM
In reality, the current source is not ideal, and this has an effect on the gain we
have just calculated. This effect is in general negligible. What is not negligible is
the effect of r05 on the common mode gain. For a common mode input signal the
circuit can be seen symmetric! It can be shown that even for a perfectly
symmetric circuit (no mismatch) a CM signal at the input ('vin,CM) generates an
unwanted signal at the output ('vout).
VDD
T3
Common Mode Gain (neglecting
bulk effect and r01,2)
T4
Vout
Vin,CM
T2
T1
Vb
Manila, December 2002
GCM
T5
'Vout
'Vin,CM
r03 ,4
1
//
2gm3,4
2
1
r05
2gm1,2
gm1,2
1
1 2gm1,2r05 gm3,4
Giovanni Anelli, CERN
63
Noise in a DP + Active CM
VDD
VDD
2I
2I
vin2
vin2
v 2tot
i2out
2
v load
2
v load
v 2tot
Manila, December 2002
i2out
2
· 2
§
g
m _ load
2
¸ ˜ v load
2 ˜ v in 2 ˜ ¨ 2
¸
¨ g
m
_
in
¹
©
Giovanni Anelli, CERN
64
Noise in a DP + Active CM
VDD
v
2
tot _ 1 / f
K a _ load ˜ P load ˜ L2in ·
1 §¨
¸ ˜ 'f
2˜ 2
˜ ˜ 1
2
¨
Cox WinLin f ©
K a _ in ˜ P in ˜ Lload ¸¹
K a _ in
2I
v
2
tot
Make WinLin big and Lload ! Lin
v 2tot _ th
§
§W·
¨
P load ¨ ¸
2
¨
© L ¹load
4kTn J ˜
˜ ¨1
§W·
Win ¨
P
¸
2P inC ox
I ¨
in ¨
L
© ¹in
Lin ©
·
¸
¸
¸ ˜ 'f
¸
¸
¹
§W·
§W·
Make ¨ ¸ ! ¨ ¸
© L ¹in © L ¹load
Manila, December 2002
Giovanni Anelli, CERN
65
Offset of a DP + Active CM
RANDOM OFFSET (WORST CASE)
VDD
v off
'VT 1,2 2I
I
gm1,2
§ 'E1,2 'E 3 ,4 gm3 , 4
·
¨
¸
'
V
T 3 ,4 ¸
¨ E
E 3 ,4
I
© 1,2
¹
SYSTEMATIC OFFSET
v off
Vin
T1
T2
Vout
T3
The difference in the drain voltages
of T1 and T2 gives origin a difference
in the DC currents in the two
branches.
T4
“COMMON MODE” OFFSET
As we have already seen, a common
mode signal at the input gives a non
zero output voltage signal.
Manila, December 2002
Giovanni Anelli, CERN
66
List of Acronyms
• CSS:
Common-Source Stage
• CSS-CSL:
Common-Source Stage with Current Source Load
• SF:
Source Follower (also called Common-Drain Stage)
• CGS:
Common-Gate Stage
• CascS:
Cascode Stage = CSS + CGS
• FCascS:
Folded Cascode Stage
• DP:
Differential Pair
• CM:
Current Mirror
• CCM:
Cascode Current Mirror
• LVCCM:
Low-Voltage Cascode Current Mirror
• CMRR:
Common Mode Rejection Ratio
Manila, December 2002
Giovanni Anelli, CERN
sorry… 67
Outline
•
•
•
•
•
Single-stage amplifiers
The differential pair
The current mirror
Differential pair + active current mirror
Frequency analysis of an amplifier
¾
¾
¾
¾
¾
¾
Low pass filter analysis
Bode diagrams
Miller’s Theorem
Frequency response of a Common Source Stage
Feedback
Stability issues in an amplifier
• Operational amplifier (op amp) design
Manila, December 2002
Giovanni Anelli, CERN
68
Low-pass filter – time domain
R
Vout (t)
Vin (t)
+
1V
t
0
v out (t )
1 R ˜ i( t )
i (t)
C
Vin (t)
v out (t )
1 RC ˜
dv out (t )
dt
REMINDER:
FOR A CAPACITOR
C WE HAVE THAT
i( t )
RC ˜
C
dv( t )
dt
dv out (t )
v out ( t )
dt
1
We can integrate the differential equation with the initial condition that
the capacitor is not charged for t = 0 s (i.e. V out(0+) = 0). We obtain:
v out ( t )
1 e
t
RC
For more complex circuits, the equations become difficult to manage…
Manila, December 2002
Giovanni Anelli, CERN
69
Low-pass filter – time domain
1.2
v out ( t ) |
t
when t RC
RC
V out (t) [ V ]
1
0.8
0.6
0.4
After t = 5 RC
vout has reached
99.32 % of its
final value
R = 1 k:
C = 1 PF
RC = 1 ms
0.2
0
0.E+00 1.E-03 2.E-03 3.E-03 4.E-03 5.E-03 6.E-03 7.E-03 8.E-03
Time [ s ]
Manila, December 2002
Giovanni Anelli, CERN
70
Low-pass filter – frequency domain
In the frequency domain (s), the resistor has an impedance R and the
capacitor has an impedance 1/sC. This allows calculating very easily
the transfer function H(s) from input to output.
R
Vout
+
Vin
i (s)
v out (s)
1
sC
H(s)
v in (s) 1
˜
1 sC
R
sC
v in (s)
v out ( s)
vin ( s)
1 sRC
1
1 sRC
1
1
s
Zp
At this point, we can use the Laplace transformation to have the
frequency representation of the input signal. This, multiplied by the
transfer function, gives the output signal (as a function of the
frequency). Anti-transforming by Laplace gives the output signal as a
function of the time.
Manila, December 2002
Giovanni Anelli, CERN
71
Complex numbers
A complex number has the form s = a + j·b, where j
1
We can associate a sinusoid of a given frequency to a complex number
Imaginary axis
2 A sin(Z t I)
y(t )
P=a+jb
b
2A
A
Real axis
I
2
4
6
8
10
12
t
a
A
a
A ˜ cos I
b
A ˜ sin I
I
b
arctan
a
s
a b
Manila, December 2002
2
I
e jx
2
a j˜b
cos x j ˜ sin x
A ˜ cos I j ˜ A ˜ sin I
Giovanni Anelli, CERN
A ˜ e jI
73
Fourier Transformation
A signal f(t) can be obtained superposing sinusoids and cosinusoids of
different frequencies (harmonic components of the signal). We can
therefore write:
f
f (t )
1
jZ t
f
(
Z
)
e
dZ
³
2S f
f (Z )
f
1
j( Z t T Z )
U
e
dZ
Z
³
2S f
f
jZ t
f
(
t
)
e
dt
³
f
f(Z) is the Fourier Transformation of the signal f(t). It describes the
harmonic composition (spectrum) of the signal.
UZdZ/2S is the amplitude of the wave of frequency Z, TZ is the phase.
The Fourier Transformation is limited to the class of signals for which
the above integral exists. Many signals useful in our field do not satisfy
this requirement!
Manila, December 2002
Giovanni Anelli, CERN
74
Laplace Transformation
Instead of using sinusoids of constant amplitude (e-jZt) as spectral
components of the signal, we can use “generalized” sinusoids
(e-st = e-Dt e-jZt), which have an amplitude which varies with time. This
help the integral which appears in the Fourier Transformation to
converge. We obtain in this way the Laplace Transformation.
f
f (t )
0
5
10
15
20
25
30
35
1
st
f
(
s
)
e
ds
³
2Sj f
40
f
f ( s)
st
f
(
t
)
e
dt
³
f
Manila, December 2002
Giovanni Anelli, CERN
75
Laplace Transformation properties
Property [ t ]
Time Function
Transformation
Property [ s ]
Linearity
c1 ˜ f1( t ) c 2 ˜ f2 ( t )
c1 ˜ f1( s) c 2 ˜ f2 ( s)
Linearity
Derivation
df ( t )
dt
s ˜ f ( s)
Integration
³ f (t )dt
Multiplication by t
t ˜ f (t )
1
˜ f ( s)
s
df (s)
ds
Translation in time
f (t T )
Convolution
Manila, December 2002
f (t ) g(t )
e
sT
˜ f ( s)
f (s) ˜ g( s)
Giovanni Anelli, CERN
Multiplication by s
Division by s
Derivation
Multiplication by an
exponential
Multiplication
76
Laplace Transformation examples
f (t )
Graphical representation in
the time domain
G( t )
1( t )
t
e
˜ 1(t )
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t
t
1
s2
t
1
s 1/ W
1
Giovanni Anelli, CERN
1
1
s
1
t ˜ 1( t )
t / W
f ( s)
77
Low-pass filter response
Vin (t)
H(t ) vin (t )
v out (t )
v out (t )
1V
t
0
L
vin (s)
1
s
v out (t )
³
f
f
H(W)vin (t W)dW
To follow the “red path” is in
general much more difficult
than to follow the blue one!
H( s)
1
1 sRC
LOW PASS FILTER
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Giovanni Anelli, CERN
t
§
·
1( t ) ˜ ¨¨ 1 e RC ¸¸
©
¹
-1
L
1
1
v out (s)
˜
s 1 sRC
1
1
s 1 s / RC
79
Bode diagrams
Many interesting properties of the frequency behavior of a given circuit can be
obtained plotting the module and the phase of the Transfer Function as a
function of the frequency. These plots are called Bode diagrams. In the general
case, a transfer function is given by the ratio between two polynomials. The
roots of the numerator polynomial are called zeros, the roots of the
denominator polynomials are called poles. In the case of the already analyzed
low-pass filter with RC = 1 ms, the Bode diagrams look like:
20
0
Phase [degrees]
20log 10 |H(s)| [dB]
-10
0
-20
-40
-20
-30
-40
-50
-60
-70
-80
-60
1.E+00
-90
1.E+01
1.E+02
1.E+03
1.E+04
1.E+05
1.E+06
1.E+00
1.E+02
1.E+03
1.E+04
1.E+05
1.E+06
Frequency [rad/s]
Frequency [rad/s]
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1.E+01
Giovanni Anelli, CERN
80
Low pass filter simulation
0.56
0.6
0.52
Vin
0.4
0.48
Vout
0.44
0.4
Vin
0.2
Vout
0.36
1.0E-02 1.2E-02 1.4E-02 1.6E-02 1.8E-02 2.0E-02 2.2E-02
0
A the input we have
the superposition of
two sinusoids with
frequencies 100 rad/s
and 10 krad/s and
peak-to-peak
amplitudes 1 V and
100 mV respectively
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-0.2
-0.4
-0.6
0.E+00
2.E-02
4.E-02
6.E-02
8.E-02
1.E-01
Time [ s ]
Giovanni Anelli, CERN
81
Bode diagrams
An IMMENSE advantage of the Laplace transformation is that the total transfer function
of a given circuit made up by several blocks in series can be obtained as the product of
the transfer functions of each single block.
H1 (s)
1
1 sW 1
H2 ( s)
1 sW 3
0
-20
Phase [degrees]
20log 10 |H(s)| [dB]
H3 ( s)
H1( s) ˜ H2 (s) ˜ H3 (s)
H( s)
20
0
-20
-40
-60
-80
-100
-120
-140
-160
-180
-200
-220
-240
-260
-280
1.E+00
1
1 sW 2
1
W3
1
W1
1
W2
-40
-60
-80
-100
-120
-140
-160
1.E+02
1.E+04
1.E+06
1.E+08
1.E+10
1.E+12
-180
1.E+00
1.E+04
1.E+06
1.E+08
1.E+10
1.E+12
Frequency [rad/s]
Frequency [rad/s]
Manila, December 2002
1.E+02
Giovanni Anelli, CERN
82
Miller’s theorem
(a)
X
X
Z
(b)
Y
Y
Z1
Z2
IF the circuit (a) can be converted to the circuit (b), then we can write:
Z1
Z
1 G
Z2
Z
1
1
G
G
VY
VX
It is not trivial to find out beforehand if the conversion can be done or
not. What it is interesting for us is that Miller’s theorem is valid when the
impedance Z is in parallel with the main signal. This will always be the
case in our examples.
Manila, December 2002
Giovanni Anelli, CERN
83
Frequency response of a CSS
VDD
To analyze this circuit we
have two possibilities:
RD
• Use the equivalent circuit,
mathematics and patience
(and obtain the exact result)
CGD
Vout
RS
• Use the Miller’s theorem and
make some approximations.
CDB
+
CGS
Vin
With the small signal equivalent circuit we have:
v out (s)
v in (s)
CGD
s
gm
C GDCDB )s 2 [R S (1 gmR D )C GD R SCGS R D (C GD CDB )]s 1
1
gmR D
R SR D (C GSCGD C GSCDB
And here is quite difficult to conclude something about the frequency
behavior of a common-source stage!
Manila, December 2002
Giovanni Anelli, CERN
84
Frequency response of a CSS
Using the Miller’s theorem, CGD can be split in two capacitances, one put
at the input multiplied by (1-G) and one at the output multiplied by (1-1/G).
It is quite easy now to see two poles, one at the input and one at the
output.
VDD
Win
RD
RS
+
R S [ CGS (1 gmR D )CGD ]
W out
Vout
CGD + CDB
Vin
H( s) approx .
CGS + (1+gmRD)CGD
Manila, December 2002
R D [ CGD CDB ]
Giovanni Anelli, CERN
gmR D
(1 sW1 )(1 sW 2 )
85
Frequency response of a CSS
From the exact expression of the transfer function we can find the two poles
(zeros of the denominator). It is possible to show that the two poles obtained with
Miller’s theorem are a good approximation. The main difference between the exact
and the approximated H(s) is the zero!
A zero in a transfer function means that at the frequency of the zero H(sz) = 0, and
therefore Vout(sz) = 0 (for a given input). Moreover, the currents in the capacitor
CGD and in the transistor must be equal and opposite. This allows to calculate the
frequency of the zero.
V
DD
CGD
v GS
1
s z CGD
i1
RD
i2
gm v GS
Vout
i1
i2
i1
i2 gives s z
VGS
Manila, December 2002
Giovanni Anelli, CERN
gm
CGD
86
Frequency response of a DP+CM
VDD
T3
T4
CM
T1
T2
Vout
W mirror
gm3
|
CM
CL
Vin
W out | CL (r02 // r04 )
ISS
Manila, December 2002
Giovanni Anelli, CERN
87
Feedback
Vin
+
H
Vout
A(s)
G(s)
v out (s)
v in ( s)
A ( s)
1 A( s)F( s)
A ( s)
1 Gloop ( s)
F(s)
• A(s) is the open loop transfer function
• F(s) is the feedback network transfer function
• G(s) is the closed loop transfer function
• A(s)F(s) is the loop gain
• If the feedback is negative, the loop gain is negative
• For |Gloop(s)| >> 1, we have that
Manila, December 2002
G( s)
Giovanni Anelli, CERN
1
F( s)
88
Properties of negative feedback
Negative feedback reduces substantially the gain of a circuit, but it
improves several other characteristics:
• Gain desensitization: the open loop transfer function is generally
dependent on many varying quantities, given by the active components
in the circuit. Using a passive feedback network, we can reduce the
dependence of the gain variation on the variations of the open loop
transfer function.
dG dA
1
G
A 1 Gloop
• Reduction of nonlinear distortion
• Reduction or increase (depending on the feedback topology) of the
input and output impedances by a factor 1-Gloop.
• Increase of the bandwidth
Manila, December 2002
Giovanni Anelli, CERN
89
Bandwidth increase with feedback
|G(s)|
Vin
+
A(s)
Vout
A ( s)
A0
A0
s
1
Z0
A0
1
|
1 fA 0 f
-f
Z
Z
Z(1+fA0)
GBWP
G( s)
A( s)
1 f ˜ A ( s)
A0
1 fA 0
s
1
(1 fA 0 )Z 0
The gain-bandwidth product does not change with feedback!
Manila, December 2002
Giovanni Anelli, CERN
90
Stability Criteria
Vin
+
Vout
A(s)
|fA(s)|
GREEN: STABLE
RED: UNSTABLE
-f
G( s)
A ( s)
1 f ˜ A ( s)
1 f ˜ A (s)
Z1
|fA(jZ1)| = 1
Z
‘ fA(s)
0
Barkhausen’s Criteria
Z1
Z
- 90q
- 180q
‘ fA(jZ1) = - 180q
Manila, December 2002
Giovanni Anelli, CERN
91
Phase Margin
We have seen that to ensure stability |fA(s)| must be smaller than 1 before
‘ fA(s) reaches - 180q. But, in fact, to avoid oscillation and ringing, we
must have a bit more margin.
We define phase margin (PM) the quantity 180q + ‘ fA(Z), where Z is the
gain crossover frequency. It can be shown that, to have a stable system
with no ringing (for small signals) we must have PM > 60q. If we want to
have an amplifier which responds to a large input step without ringing,
PM must be even higher.
|fA(s)|
‘ fA(s)
Z1
|fA(s)|
Z
SMALL PM
Z
‘ fA(s)
- 180q
Manila, December 2002
Z1
Z
LARGE PM
Z
- 180q
Giovanni Anelli, CERN
92
Frequency Compensation
Single-pole op-amps would always be stable (the phase does not go
below - 90q). But a typical op-amp circuit always contains several poles
(and zeros!). These op-amps can easily be unstable, and they need
therefore to be compensated. This is generally done lowering the
frequency of the dominant pole.
To do so, we must add a capacitor, which is some cases can be quite
large. One way of compensating a two-stage op amps is to add a
capacitance across the second stage. This capacitance is multiplied by
the Miller effect, and therefore it does not need to be too large!
The Miller compensation capacitor has also the nice property to move
the non dominant pole to higher frequencies.
This effect is called pole splitting.
Miller compensation also introduces a zero which contributes a phase
shift of - 90q. This can be a serious issue, and it must be taken into
account compensating the circuit.
Manila, December 2002
Giovanni Anelli, CERN
93
Outline
•
•
•
•
•
•
Single-stage amplifiers
The differential pair
The current mirror
Differential pair + active current mirror
Frequency analysis of an amplifier
Operational amplifier (op amp) design
¾
¾
¾
¾
Single-stage op amps
Two-stage op amps
One simple design example
Low voltage issues
Manila, December 2002
Giovanni Anelli, CERN
94
Op-amp application examples
NONINVERTING
CONFIGURATION
INVERTING
CONFIGURATION
R2
Vin
Vout
Vin
Vout
R1
BUFFER
R2
R1
Vin
G
Vout = Vin
R
1 2
R1
G
G
R2
R1
1
The above equations are valid only if the gain of the op-amp is very high!
Manila, December 2002
Giovanni Anelli, CERN
95
Single-stage Op Amp
VDD
T7
Vb2
T8
T5
T6
Vb2
Vout
Vb1
T3
T4
T1
T2
Vb1
Several different solutions can be
adopted to make a Single-stage
amplifier. If high gains are needed, we
can use, for example, cascode
structures.
With single-stage amplifiers it is difficult
to obtain at the same time high gain and
voltage excursion, especially when
other characteristics are also required,
such as speed and/or precision.
Two-stage configurations in this sense
are better, since they decouple the gain
and voltage swing requirements.
Vin
ISS
Manila, December 2002
Giovanni Anelli, CERN
96
Two-stage Op Amp
G
gm1,2 (r01,2 // r03 , 4 ) ˜ gm5 ,6 (r05 ,6 // r07 ,8 )
The second stage
is very often a CSS,
since this allows
the maximum
voltage swing.
VDD
T3
T4
T5
Vb1
T1
T6
The output voltage
swing in this case
is VDD - |2VDS_SAT|
T2
Vin
Vout1
Vout2
ISS
Vb2
T7
Manila, December 2002
T8
Giovanni Anelli, CERN
97
Two-stage Op Amp
G
^ g >(g
m1,2
m3,4
gmb 3,4 )r03 ,4r01,2 )@ // >(gm5 ,6 gmb 5 ,6 )r05 ,6r07 ,8 )@ `˜ gm9 ,10 r09 ,10 // r011,12 VDD
Vb3
T7
T8
Vb3
Vb2
T5
T6
Vb2
To increase the
gain, we can again
make use, in the
first stage, of
cascode structures.
T9
T10
Vb1
Vout1
T3
T4
T1
T2
Vb1
Vout2
Vin
Vb4
T11
Manila, December 2002
ISS
T12
Giovanni Anelli, CERN
Vb4
98
Two-stage Op Amp
G
gm1,2 (r01,2 // r03 , 4 ) ˜ gm6 (r06 // r08 )
Two-stage op amps can
also have a single-ended
output. In this case, we
kept the differential
behavior of the first
stage, and is the current
mirror T7-T8 which does
the differential-to-single
ended conversion.
VDD
T3
T4
T5
Vb
T1
T6
T2
Vin
Vout
ISS
T7
Manila, December 2002
T8
Giovanni Anelli, CERN
99
Design Example
OTA Miller – Two stage op-amp with Miller compensation
G
VDD
T6
T7
G
T8
Vout
Vin -
T1
T2
Vin +
CL
Cc
Rb
T5
T3
T4
gm2 (r02 // r04 ) ˜ gm5rout
ZD
gm2r024 ˜ gm5rout
BW |
1
gm5rout C cr024
Z ND |
gm 5
C out
gm 5
ZZ |
Cc
GBWP |
Manila, December 2002
Giovanni Anelli, CERN
gm 2
Cc
100
Design Example Performance
Conditions: Ibias = 120 PA, CL = 20 pF
• Power consumption = 3.5 mW
• Rise time = 10.5 ns
• Slew rate = 34 V/Ps
• Gain Bandwidth Product = 22 MHz
• Phase Margin = 70q
Manila, December 2002
Giovanni Anelli, CERN
101
Design Example Layout
122 Pm
90.4 Pm
Manila, December 2002
Giovanni Anelli, CERN
102
Low voltage issues
• Use rail-to-rail input stages
• Low VDS_SAT Æ Big transistors Æ Low speed
• Use low-VT or 0-VT transistors
• Use multi-gain systems to have high dynamic range
• Use devices in W.I. (low VDS_SAT and high gm/ID)
• Use current-mode architectures
• Use bulk-driven MOS
• If very low-power is needed, this can also be obtained at
the system level
Manila, December 2002
Giovanni Anelli, CERN
103
Rail-to-rail input stage
In all the solutions that we have seen up to now, the common-mode input voltage
range is about VDD - VGS – VDS_SAT. This can cause some problems, especially if
we want to use the op amp as a buffer or if the power supply voltage is quite low.
VDD
This solution has the
drawback of having a variable
total transconductance
IP
Vin1
T1N
gm
T2N
T1P
Vin2
T2P
gmP
gmN
gmN+gmP
IN
VDD
Manila, December 2002
Giovanni Anelli, CERN
VinCM
104