Altera SoC Embedded Design Suite Release Notes
2016.05.09
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These release notes cover version 16.0 of the system on chip (SoC) Embedded Design Suite (EDS)
software.
Related Information
SoC Embedded Design Suite Support Page
© 2016 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are
trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance
of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,
product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.
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SoC Embedded Design Suite Revision History
2016.05.09
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Enhancements to the SoC Embedded Design Suite
Enhancements for Version 16.0
The following enhancements are for version 16.0:
• ARM® Development Studio 5™ Altera® Edition (DS-5 AE)
• Includes ARM DS-5™ AE version 5.23.1
• Bootloader Generator and U-Boot
• Cyclone V SoC U-Boot
• Full SDRAM ECC init enforced when SDRAM ECC is enabled
• Support for the GCC5 toolchain is enabled
• Arria 10 SoC U-Boot
• SDRAM ECC support enabled
• OCRAM ECC initialization for those regions uninitialized by boot ROM enabled
• Power up ethernet PHY if powered down
• Error interrupt in Arria 10 SDRAM ECC enabled
• Secure Boot
• Help menu usage statement for alt-secure-boot updated to the executable tool name
• Quartus™ Programmer supporting programming secure boot fuses added
• Golden Hardware Reference Design (GHRD)
• Supports the Rev C Development Kit with production silicon
• Revision label in SystemID updated
• F2SDRAM ports 0 and 2 are enabled
• Hardware Libraries (HWLIBs)
• Supports Arria 10
• SDRAM API doxygen headers fixed
• Toolchains
• Toolchain upgraded to gcc v5.2. (1)
(1)
Customers MUST use -mno-unaligned-access compiler flag to compile if alignment fault checking enabled
(SCTLR.A = 1).
© 2016 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are
trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance
of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,
product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.
www.altera.com
101 Innovation Drive, San Jose, CA 95134
ISO
9001:2008
Registered
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Enhancements to the SoC Embedded Design Suite
Enhancements for Version 15.1.1
• ARM Development Studio 5 Altera Edition (DS-5 AE)
• Includes ARM DS-5 AE version 5.23
• Bootloader Generator and Uboot
• Arria® 10 SoC Uboot
• Enable DesignWare SPI driver support
• Enhancement on Uboot driver to support QSPI/NAND RBF address loading from DTB
• Cyclone® V SoC Uboot
• Enabling SDRAM ECC Initialization support for 2 GB SDRAM
• Arria 10 BSP Editor:
• Quad SPI Load Address for RBF as a parameter added
• Golden Hardware Reference Design (GHRD)
• Updated On-Chip Memory data width to 128 bits to optimize logic usage from PCIe to OCM
• General
• Signing software updated
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Bug Fixes for the SoC Embedded Design Suite
3
Bug Fixes for the SoC Embedded Design Suite
Bug Fixes for Version 16.0
• Bootloader Generator and Uboot
• Cyclone V SoC Preloader
• SDRAM content clearing after a warm reset fixed
• Build error using the default configuration fixed
• Arria 10 SoC U-Boot
• Incorrect timer frequency fixed
• Incorrect emif_reset request code fixed
• fpgabr command failure handling enhanced
• NOC timeout disabled
• NOC idle status check issue fixed
• L4 Watchdog reset fixed to support secure clock for boot_clk
• Linux Device Tree Generator (DTG)
• PCIe support in Sopc2dts enabled
• Golden Hardware Reference Design (GHRD)
• Arria 10 PCIe Gen2 RP—Performance counter and MSI IP clock info derivation issue during
device tree generation fixed
• PCIe Hardware Design build fixed
• Hardware Libraries (HWLIBs)
•
•
•
•
•
•
•
•
The Clock Manager's debug clock's frequency is no longer reported incorrectly
QSPI part that comes with the Arria 10 Dev Kit is enabled
Arria 10 HWLIBs SPI clock setup method issue fixed
Arria 10 reset masks OSC1TMR0 and OSC1TMR1 in alt_timers.c updated
Arria 10 skip to clean microcode buffer in the DMA fixed
Copyright header in the SDRAM fixed
HWLIBs Timer Example GUI missing files issue fixed
SDRAM API fixed
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Upgrading the SoC Embedded Design Suite
Bug Fixes for Version 15.1.1
• Linux Device Tree Generator (DTG)
• DTG incorrectly limiting SD Card to 25 MHz fixed
• Bootloader Generator and Uboot
• Secure Boot
• Missing -pubkeyout option for secure boot in makefile fixed
• GHRD
•
•
•
•
•
•
•
•
Arria 10 GHRD for EMAC MDIO ports constrain included
Examples hardware changed from F2SDRAM2 to F2SDRAM0
Arria 10 ES2 Part ID in GHRD supported
Critical warnings removed
F2SDRAM port 0 disabled because of Quartus Prime issue
Arria 10 transceiver reset controller settings improved
Setting Rx clock assignments to unused channels critical warnings fixed
On-Chip Memory data width bug that occurred when the user selected boot from the FPGA option
is fixed
• Hardware Libraries (HWLIBs)
• Compilation issues for Arria 10 HWLIB examples on the ARMCC fixed
• Cyclone V examples updated to use 4.9.12 GCC
• Arria 10 LEDs and Timer HWLIBs example fixed
• General
• Gb ethernet issue with the RGMII Micrel PHY fixed
Upgrading the SoC Embedded Design Suite
Upgrades from Version 15.1.1 to 16.0
• Golden Hardware Reference Design (GHRD)
• Arria 10 SoC
• Arria 10 SoC GHRD in SoC EDS 16.0 targets Rev C Development Kit with production silicon.(2)
• Hardware Libraries (HWLIBs)
• Support is similar to 15.1.1 except for the following:
• The Timer example supports Arria 10 as well as Arria V and Cyclone V.
• Bare-metal developers are able to access features of the chip through a new SDRAM API that
was added.(3)(4)
(2)
(3)
(4)
Any FPGA design migrated from a Rev B1 Development Kit must be recompiled.
The functionality is different between Arria V/ Cyclone V and Arria 10.
Only the API is available.
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Known Issues for the SoC Embedded Design Suite
5
Upgrades from Version 15.1 to 15.1.1
• SoCEDS 15.1.1 supports the Rev B1 Development Kit which has a different device family for the
Arria10 SoC.(5)
• Upgrade the Uboot software and Linux image to include recent fixes to make the Ethernet PHY more
reliable with a wide range of Ethernet switches.
• Upgrade the Uboot device tree from the recompiled FPGA design because there have been some clock
and pin configurations for the GHRD.
Known Issues for the SoC Embedded Design Suite
Known Issues for Version 16.0
Cyclone V SoC Uboot Fatwrite Small File Failure
Description
The Cyclone V SoC Uboot is having intermittent failure when using fatwrite to write a small file
(1kB).
Workaround
You can use the mainstream Uboot which has patches for FAT handling.
Known Issues for Version 15.1.1
Enable Boot from FPGA Signals Needed to Support Public Key in FPGA
Description
In order for the BootROM to fetch the public-key from the FPGA (in the case where the root key is
stored in the FPGA during secure boot for authentication), the BootROM must bring the H2F bridge
out of reset. One of the signals that the BootROM checks when attempting this is driven by the FPGA
and tells the BootROM that it is safe to read from the HPS-FPGA bridge. If this signal is not driven
from the FPGA properly, the BootROM cannot fetch the root key from the FPGA and the secure boot
fails.
Workaround
You must set up the system for this use case by selecting the "Enable boot from FPGA signals" option
from the HPS IP component in QSYS. When that option is selected, the FPGA drives the required
signals and the BootROM can successfully fetch the root key from the FPGA for authentication.
DS-5 Plugins are not Loaded by Eclipse
Description
Eclipse™ can start without loading the "Altera Baremetal GCC" plugin or the ARM-specific plugins
which give it the DS-5 identity. In this case, the results are that the baremetal toolchain or all DS-5
features are unavailable. Switching between versions of DS-5 can often trigger this error.
Workaround
(5)
Any FPGA design migrated from a Rev A Development Kit must be recompiled.
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Known Issues for the SoC Embedded Design Suite
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Launch Eclipse with the '-clean' option. For example, "eclipse -clean". This clears cached Eclipse
data and forces a rescan of the available plugins. This is a common Eclipse framework workaround.
For more information, refer to the Stack Overflow Question and Answer page.
Related Information
Stack Overflow Question and Answer
How to run eclipse in clean mode? and what happens if we do so?
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Document Revision History
2016.05.09
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Table 1: Document Revision History
Date
Version
Changes
May 2016
2016.05.09
Maintenance release documenting what's
new in the 16.0 release.
January 2016
2016.01.22
Maintenance release documenting what's
new in the 15.1.1 release.
November 2015
2015.11.02
Maintenance release documenting what's
new in the 15.1 release.
June 2015
2015.06.05
Maintenance release documenting what's
new in the 15.0.1 release.
May 2015
2015.05.01
Maintenance release documenting what's
new in the 15.0 release.
© 2016 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are
trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance
of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,
product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.
www.altera.com
101 Innovation Drive, San Jose, CA 95134
ISO
9001:2008
Registered