52
CHAPTER 3
IMPLEMENTATION OF AMPLITUDE MODULATED
TRIANGULAR CARRIER PWM FOR SINGLE PAHSE VSI
3.1
INTRODUCTION
Traditional natural sampling techniques rely on analog circuits,
where a fixed triangular carrier waveform is compared to a variable
magnitude and frequency sinusoidal reference waveform. The intersection
point determines the switching waveform. The Amplitude Modulated
Triangular Carrier Pulse Width Modulation method (AMTCPWM) is a
natural sampled PWM method which can extend the linearity of the
sinusoidal PWM (SPWM) to full range of the pulse dropping region and
increase the dynamic range of the SPWM control. Thus it eliminates the need
for over-modulation in the pulse dropping region to reach the square wave
boundary. Any PWM theory with a specific performance target requires either
a reference or a carrier modification. To achieve the targeted performance,
there should be a lot of flexibility in the design. This is possible with their
digital implementation and accurate imitation of the theory.
3.2
SINGLE PHASE VSI
A switching sequence for the basic single-phase full-bridge
inverter, shown in Figure 3.1, which consists of two switching poles, S1/S2
and S3/S4, there are 24=16 different possible combinations of switching. Of
these, only four are useful for obtaining the PWM pattern across the inverter
53
output as shown in Table 3.1. PWM schemes presented here are assumed to
be synchronous PWM.
Figure 3.1 Single-phase voltage source inverter
Table 3.1 Switching combinations
3.3
Conducting Switches
Output Voltage
S1 , S4
+Vdc
S3 , S2
-Vdc
S1 , S3
0
S2 , S4
0
SINUSOIDAL PWM TECHNIQUE
Single-pulse modulation, Multiple-pulse modulation and Sinusoidal
Pulse Width Modulation (SPWM) are the basic types of analog PWM
techniques. Of these, the most advanced analog PWM method is the SPWM
or also called Carrier Based Pulse Width Modulation (CB-PWM) as pointed
out by Bowes (1975). The operating principle of this method is based on
54
comparison of sinusoidal signal (Reference Signal) with the triangular carrier
signal. Result of this operation is a train of rectangular pulses with variable
width as illustrated in Figure 3.2. Widths of the pulses are proportional to
average value of the sinusoidal signal. Output pulses of this operation can be
directly delivered to the switching devices of the Inverter.
Figure 3.2 Principle of SPWM
3.3.1
Switching Concept of Sinusoidal PWM
The unipolar PWM pulse generation with resulting pattern is
represented in Figure 3.3. With PWM, the relative amplitudes of the
harmonics change with the modulation index (Ma). The modulation index is
the ratio between the amplitudes of triangular signal (Vtri) and sine reference
(Vsin) and it is given by the equation (3.1). The frequency ratio (Mf) is the
ratio between the carrier frequency (fc) and the reference wave frequency (fo).
As pointed out by Jeevanantham et al (2005), it is generally accepted that the
performance of an inverter with any switching strategy can assess by the
harmonic content of its output voltage. A precise value of the switching angle
and hence duty cycle can be obtained from the equations for the triangular
55
(carrier) and the sinusoidal (reference) waveform equations. The intersection
between these waveforms gives the switching angles (p1, p2, p3…pi) as shown
in Figure 3.3.
Figure 3.3 SPWM pulse modulation pattern
The PWM control signal is obtained by comparing a high
frequency triangular carrier of frequency fc and amplitude 1 (per unit) and a
low frequency sine wave of frequency fm and amplitude Ma (per unit).
Equations for sinusoidal reference and triangular carrier are given by (3.2)
and (3.3) respectively.
56
Where, x is the switching angle and takes the values corresponding
to p1, p2… pi and r is equal to 1 for the first pair of triangular sections, 3 for
the second pair; 5 for the third pair and so on. The equations describing the
natural sampled switching angles are transcendental and have the general
distinct solutions for odd and even meeting points. The condition for any ith
switching angles, p i is given in (3.4) and (3.5) respectively for odd and even
switching angles.
The duty cycle can be calculated by simply adding the width of the
individual pulses in one half period of the reference wave divided by the half
period.. The width of any pulse can be found from subtracting one odd
meeting point from immediate even successor.
3.3.2
Performance Analysis
The performance of Sinusoidal PWM method has been verified by
using the Matlab software tool. Fig.3.4 represents the output voltage and
corresponding spectrum for SPWM at Ma=0.8, Mf=15 and Vdc=300V. The
fundamental output component is 80% of input and confirms the linearity in
gain.
57
Figure 3.4 Output voltage and frequency spectrum of SPWM
3.3.3
Performance Characteristics of SPWM
In the SPWM switching strategies, increase with fundamental
component of the output with finite DC link voltage demands an increase in
width of pulses in the regions around the center of the reference i.e. a
reduction in number of commutation by pulse dropping. According to Holtz
(1992), the reference output voltage relationship is linear until the reference
voltage magnitude exceeds the modulator linearity limit and the condition is
called over-modulation. When the DC link voltage of a PWM scheme has a
finite value, the voltage linearity of a modulator is confined to a limited
voltage range, as the higher voltage values are to be obtained by increasing
the inverter gain. The system loses the linearity over the fundamental as
indicated in Figure 3.5 and introduces many more harmonics in the side bands
as compared to the linear range. When the modulation index is greater than
unity, the gain reduces sharply in a nonlinear manner. As the modulation
index approaches very large values (
), the gain approaches zero. In this
58
mode the SPWM output voltage saturates at its theoretical maximum i.e. the
output of square operation, [(4/ )*Vdc]. This value is 1.273 times the
maximum possible output of linearity limit.
The SPWM output voltage
(normalized for Vdc) is plotted against (Ma) as in Figure 3.6 with ideal
characteristics.
Figure 3.5
Output voltage fundamental component versus modulation
index
Figure 3.6 Comparison-Ideal and SPWM characteristics
59
Retaining the linearity until the square wave output limit is the
ideal characteristics and also, it is the demand for the feedback controllers.
Vikram (1996) stated that, due to the transition region’s nonlinearity (overmodulation), solution for the problem is very complex; few of them demand
nonlinear inverse gain calculation and results in considerable amount of error.
There is no simple PWM algorithm which ensures linearity with full
utilization of dc input for single-phase inverter system.
3.4
AMTC-PWM METHOD
The transition from PWM to square wave mode operation was an
unresolved problem limiting the performance of ac drive systems. To
overcome the problem mentioned in above section, the Modified regular
sampled SPWM scheme named as Amplitude Modulated Triangular Carrier
PWM (AMTCPWM) has been developed by Ramkumar et al. (2009) to
achieve the single mode operation of SPWM inverter; by linearly hopping to
square wave region. It also offers linear gain characteristics compared to the
conventional SPWM without involving complex computations and significant
changes in device losses.
3.4.1
Concept of AMTC-PWM Method
In the AMTCPWM method, the conventional sine wave remains as
a reference signal while the carrier is amplitude modulated triangular signal as
shown in Figure 3.7. The carrier is the basically a high frequency triangular,
which is (amplitude) modulated by a sinusoidal modulating signal of
reference frequency.
60
Figure 3.7 AMTCPWM pulse pattern (unipolar)
For the AMTCPWM pulse pattern, the switching angles can be
calculated in a similar way as the SPWM scheme through analytical relations.
The basic definition of modulation index (Ma) is not valid in the AMTCPWM
method since the triangular carrier is not a constant; it is the function of the
modulating sine wave. But to aid the analytical characterization, the
modulation index, Ma is defined as ratio between magnitude of reference and
magnitude of modulating wave. The output pulse pattern (q1, q2, q3……qi) is
the resultant of intersections between the modulated triangular carrier of
modulating signal and the sinusoidal reference waveform.
61
3.4.2
Performance Analysis of AMTC-PWM
The performance of AMTC-PWM method has been thoroughly
analyzed using the tool Matlab 7.9 version. The Simulink model of AMTCPWM driven single phase inverter with resistive load is shown in Figure 3.8.
The typical output voltage and corresponding frequency spectrum of
AMTCPWM at Ma=0.8, Mf =15 and Vdc= 200V is shown in Figure 3.9.
Figure 3.8 Simulink model of AMTC-PWM driven Single phase VSI
62
Figure 3.9 Output voltage and frequency spectrum - AMTCPWM
3.5
PROPOSED DIGITAL ARCHITECTURE OF AMTC-PWM
The reprogrammable architecture capable of imitating the
AMTCPWM with perfect reproduction has been developed as shown in the
Figure 3.10. It consists of four processing units namely; Sine Data
Manipulation (SDM) unit, Amplitude Modulated Carrier Generation (AMCG)
unit, Reference Wave Scaling (RWS) unit and Comparator and Pulse
Separation (CPS) unit.
63
64
The SDM unit generates the address in sequence for fetching the
sine data. The sine data for the first quarter is kept in the Look-up-table
(LUT) and the data for the consequent three quarter sections can be derived
through an intelligent way. Thus, the SDM unit obtains the sine data
continuously for the complete cycle. The manipulated sine data is used for
both reference wave and the amplitude modulation envelop. The quarter
selection is supported by the multiplexer. Based on the timed samples of the
sine data, the amplitude modulation of the up/down counted triangular carrier
is guided by the AMCG unit. The amplitude modulated triangular carrier
wave is generated by the AMCG Unit. VHDL coding for the carrier wave
generation is given in appendix A2.2. The Reference Wave Scaling Unit
(RWSU) is to modulate the generated sine wave. Here the modulation index
ranges from 0 to 1.2 and its higher value enhances the modulating voltage.
(i.e. Modulation Index = Amplitude of Modulating wave/ Amplitude of
Carrier wave). This unit also generates a flag used to generate positive and
negative carrier wave. The CPS unit compares carrier and reference waves,
and produces the gating pulses for positive and negative group of devices
separately. The total architecture is designed using the VHDL language. Since
the language describes the behavior of hardware logic it can be used both for
simulation models and design composition. It can describe a digital system at
several different levels such as Behavioral, Dataflow and Structural. Further
capabilities of the VHDL are given in appendix A2.1. The parallel mode
execution
Figure 3.11.
of
the
AMTC-PWM
architecture
is
well
detailed
in
65
66
3.5.1
Fetching Sine Datum
Fetching the sine data from LUT consists of address counter,
Decoder, address modifier, sign changer and encoder. Address counter
generate the address from 0 to 199. This address can be modified according to
number of sine samples are available in look up table by using address
modifier. Formulating data for the sine wave through sampling process is
illustrated in Figure 3.12. Technique for deriving the sample interval is
given by;
Sample Interval =
Figure 3.12 Formulation of first quarter sine wave datum
To form the first quarter sine wave (i.e. 0 o to 90o), 50 samples are
needed. Thus, the sample interval is 1.8o (i.e. 90o/50). The second quarter
data can be fetched by reverse counting of the first quarter. The Sign Changer
is used to generate third and fourth quarter cycle datum.
67
Totally 200 samples are there for one cycle of sine wave. The Sine
LUT collects all the modified address from address modifier and provides all
sine samples to Encoder. Encoder will accumulate all the samples into a sine
wave. The table 3.2 describes the comprehensive digitization and
approximation procedures involved in sine LUT.
Table 3.2 Sampled first quarter sine datum for LUT
Actual Data
Degree
3.5.2
[Sin(degree x 180/ )]
Scaled-up
value for 210
(Rounded
Value)
Binary Value
0
0
0
00000000000
1.8
0.031423398
32
00000100000
5.4
0.09414608
96
00001100000
9
0.156496911
160
00010100000
34.2
0.56228207
575
01000111111
41.4
0.661529994
677
01010100101
45
0.707330278
724
01011010100
84.6
0.995617718
1019
01111111011
90
0.9999998
1023
01111111111
Algorithm for triangle wave generation from the sine envelope
step 1.
Start
step 2.
Calculate one quarter cycle sine data, and store it in a
look up table.
step 3.
Fix the output ac voltage frequency of the inverter.
step 4.
Initialize the initial Address value=0 for Sine Look up
table.
68
step 5.
Derive the fetching rate clock (10 KHz) from the board
clock .
step 6.
Fix the carrier frequency (3 KHz).
step 7.
Fix the initial value of the counter and step value for
Amplitude Modulated Triangle generation.
step 8.
Get the sample from sine memory based on present
address.
step 9.
Fix this present sine sample value as peak value of
carrier wave.
step 10.
Calculate the step value to generate the constant
frequency triangular wave.
step 11.
Increment the counter by step value.
step 12.
Check whether counter reaches sampled sine data.
step 13.
If reaches, and decrement the counter.
step 14.
Check whether counter reaches base value of triangular
wave.
step 15.
If reaches the counter value, increment the sine sample
address and go to step 8.
step 16.
Check for 50th sample address then decrement sine
sample address
step 17.
Check for 1st sample address then increment sine sample
address
step 18.
Then go to step 8.
69
3.5.3
Fetching Clock rate
Fetching the clock rate is determined from the number of samples
used for sine wave wrapper. It is formulated as;
Clock Rate =
For 50 Hz sine wave, Clock Rate =
= .1 x 10-3seconds.
Thus the fetched clock rate, known as design clock is 10 KHz. This
is derived from the internal clock (100 MHz) of SPARTAN-6 FPGA device
which can be achieved through the clock division method as illustrated in
Figure 3.13.
Figure 3.13 Formulation of design clock
3.6
SIMULATION AND SYNTHESIS
The proposed AMTC-PWM architecture is designed using the
VHDL language as in appendix A2.1. The functional simulation of the
architecture is carried out using the tool Modelsim 6.3. The Register Transfer
70
Level (RTL) level verification and implementation are done using the
synthesize tool Xilinx ISE 13.2. Then the designed architecture has been
configured to the SPARTAN-6 FPGA (XC6SLX45) device using the
programming software.
3.6.1
Functional Simulation
The timing and functionality verification based on ModelSim
Simulator output is presented in Figure 3.14
Figure 3.14 Modelsim output AMTC-PWM
3.6.2
Synthesis and implementation
The designed architecture is optimized using the synthesis tool, as
in appendix A1.1. The RTL schematic of the AMTC-PWM design is
generated during the synthesis process as shown in Figure 3.15. Thus the
design circuit can be verified virtually. A synthesis report is produced after
the process, which contains the overall device utilization summary for the
designed architecture as presented in Figure 3.16.
71
Figure 3.15 RTL schematic view of the AMTC-PWM design
Figure 3.16 Device utilization summary
During the implementation process, the complete timing analysis of
the design is done. The pin Utilization in the architecture can be verified by
using the Plan Ahead tool in Xilinx Project Navigator as shown in Figure3.17.
the logic implemented area for the design is shown in Figure 3.18.
72
Figure 3.17 Pin allocation for the design
Figure 3.18 Logic implemented area for AMTC-PWM architecture
3.6.3
Power Analysis
The power estimation for the designed architecture has been done
using the Xilinx power estimator tool (X-power Estimator-14.1), as illustrated
in Figure 3.19. The temperature dependency of the power is also estimated
using this tool as shown in Figure 3.20.
73
Figure 3.19 Power estimation for the design
Figure 3.20 Temperature dependency of power consumption
74
3.7
HARDWARE IMPLEMENTATION AND RESULTS
The synthesized design of AMTC-PWM architecture has been
downloaded to the FPGA Spartan 6 device (XC6SLX45) as in appendix A3.1,
with the help of device programming software “DIGILENT ADEPT” as in
appendix A1.3. The positive and Negative group pulses generated from FPGA
is shown in Figure. 3.21. The configured FPGA device with proposed
architecture has been tested with a prototype of single phase VSI which is
made by IRF840 MOSFET devices with a resistor load (R=150 ).The input
dc source is attained by using single-phase diode (6A4 MIC) rectifiers and the
output is filtered through a filter capacitance of 3000µF. The Vdc is set to
300V.The rectified output is given as the inverter input. The inverter is
realized by IRF840 MOSFET devices. The gate control signals (AMTCPWM) for the MOSFET switches are provided from the FPGA device. The
load performance of the FPGA driven VSI is analyzed through proper
measurements using Digital Storage Oscilloscope (DSO) and compared with
the traditional Sinusoidal PWM. The typical output voltage and corresponding
spectrum of AMTCPWM at Ma=0.8, Mf=15 with a Vdc of 300Vare show in
the Figures 3.22 and 3.23 respectively.
Figure 3.21 FPGA Generated pulses - AMTCPWM
75
Figure 3.22 Output voltage waveform- AMTCPWM (Ma =0.8, Mf=15)
Figure 3.23 Harmonic spectrum - AMTCPWM (Ma =0.8, Mf=15)
76
In case of SPWM, particularly with over-modulation, the
harmonics in the linear range may not be dominant. Even in linear modulation
ranges, from the output voltage spectrums, it is seen that Ma=0.8 shows the
dominant lower sideband frequencies while Ma=1 exhibits higher side band as
dominant. AMTCPWM shows proportionate variation of harmonic profile
and hence easy/unique filter design.
400
350
300
250
200
150
100
S PW M
50
AMTCPW M
0
0
0.1
0.2
0.3
0.4
0.5
0.6 0.7 0.8 0.9
Modulation Index(Ma)
1
1.1
1.2
1.3
1.4
1.5
Figure 3.24 Fundamental voltage–characteristics with respect to Ma
From the graph it is clear that the AMTCPWM scheme operates
with maximum-linear gain and reaches the square wave boundary while the
SPWM scheme exhibits drop in the gain after 300V. Figure3.24 shows the
variation of output fundamental voltage with modulation index. From the
graph it is clear that the AMTCPWM scheme operates with maximum-linear
gain and reaches the square wave boundary while the SPWM scheme exhibits
drop in the gain after 300V. Figure3.25 shows the THD values for the entire
range of output voltage and the AMTCPWM exhibits lower values of THD
for the modulation index values of 0.4 to 1.0.Table 3.3 gives the values of
modulation index, THD and lower order (sub-carrier) harmonics at the output
77
voltage (peak) level of 240V in both SPWM and AMTCPWM methods with
300V input and Mf =15. From the table, it is understood that all the lower
order harmonics are increased considerably in case of AMTCPWM method.
250
AMTCPWM
SPWM
200
150
100
50
0
0
0.2
0.4
0.6
0.8
Modulation Index(Ma)
1
1.2
Figure 3.25 Fundamental voltage VS THD –AMTCPWM
Table 3.3 Comparison of SPWM and AMTCPWM methods
SPWM
Modulation
Index (Ma)
Fundamental
Voltage
AMTCPWM
THD
(%)
(V)
Fundamental
Voltage
THD
(%)
(V)
0.8
247.8
70.34
305
69.39
1.0
300
52
378.24
52.01
78
3.8
SUMMARY
The heart of any inverter topology is the switching strategy used to
generate the switching edges of the PWM voltage waveforms. The voltage
linearity, harmonic distortion, and maximum obtainable output voltage are the
prime expectation from any PWM strategy. The proposed FPGA based
AMTC-PWM technique provides full utilization without any pulse dropping
and mode changing with good accuracy in a reprogrammable digital platform.