CMOS Process Flow
• See supplementary power point file for animated CMOS
process flow (see class ece410 website). The file should
be viewed as a slide show-- it is not designed for printing.
ECE 410, Prof. F. Salem/ Prof. A. Mason notes with updates
Lecture Notes Page 5.1
1
Layout CAD Tools
• Layout Editor
– draw multi-vertices polygons which represent physical design layers
– Manhattan geometries, only 90º angles
• Manhattan routing: run each interconnect layer perpendicular to each other
• Design Rules Check (DRC)
– checks rules for each layer (size, separation, overlap)
– must pass DRC or will fail in fabrication
• Parameter Extraction
– create netlist of devices (tx, R, C) and connections
– extract parasitic Rs and Cs, lump values at each line (R) / node (C)
• Layout Vs. Schematic (LVS)
– compare layout to schematic
– check devices, connections, power routing
• can verify device sizes also
– ensures layout matches schematic exactly
– passing LVS is final step in layout
ECE 410, Prof. F. Salem/ Prof. A. Mason notes with updates
Lecture Notes Page 5.2
2
CMOS Layout Layers
• Mask layers for 1 poly, 2 metal, n-well CMOS process
–
–
–
–
–
–
–
–
–
–
–
–
Background: p-substrate
nWell
Active
Poly
pSelect
nSelect
Active Contact
Poly Contact
Metal1
Via
Metal2
Overglass
ECE 410, Prof. F. Salem/ Prof. A. Mason notes with updates
Lecture Notes Page 5.3
3
Design Rules: Intro
• Why have Design Rules
– fabrication process has minimum/maximum feature sizes that can be
produced for each layer
– alignment between layers requires adequate separation (if layers
unconnected) or overlap (if layers connected)
– proper device operation requires adequate separation
• “Lambda” Design Rules
– lambda, λ, = 1/2 minimum feature size, e.g., 0. 6μm process -> λ =0.3μm
– can define design rules in terms of lambdas
• allows for “scalable” design using same rules
• Basic Rules
– minimum layer size/width
– minimum layer separation
– minimum layer overlap
ECE 410, Prof. F. Salem/ Prof. A. Mason notes with updates
Lecture Notes Page 5.4
4
Design Rules: 1
• n-well
MOSIS SCMOS rules; λ =0.3μm for AMI C5N
– required everywhere pMOS is needed
– rules
•
•
•
•
minimum
minimum
minimum
minimum
10λ
width
separation to self
separation to nMOS Active
overlap of pMOS Active
6λ
5λ
• Active
– required everywhere a transistor is needed
– any non-Active region is FOX
– rules
• minimum width
3λ
• minimum separation to other Active
ECE 410, Prof. F. Salem/ Prof. A. Mason notes with updates
3λ
Lecture Notes Page 5.5
5
Design Rules: 2
• n/p Select
–
–
–
–
defines regions to be doped n+ and p+
tx S/D = Active AND Select NOT Poly
tx gate = Active AND Select AND Poly
rules
2λ
• minimum overlap of Active
– same for pMOS and nMOS
• Poly
• several more complex rules available
– high resistance conductor (can be used for short routing)
2λ
– primarily used for tx gates
gate =
– rules
2λ
•
•
•
•
minimum
minimum
minimum
minimum
size
space to self
overlap of gate
space to Active
ECE 410, Prof. F. Salem/ Prof. A. Mason notes with updates
Active-Poly-Select
1λ
2λ
Lecture Notes Page 5.6
6
Design Rules: 3
• Contacts
– Contacts to Metal1, from Active or Poly
note: due to contact size
and overlap rules, min.
active size at contact will
be 2+1.5+1.5=5λ
• use same layer and rules for both
– must be SQUARE and MINIMUM SIZED
– rules
•
•
•
•
exact size
minimum overlap by Active/Poly
minimum space to Contact
minimum space to gate
1.5λ
2λ
5λ
2λ
2λ
2λ
• Metal1
– low resistance conductor used for routing
– rules
• minimum size
• minimum space to self
• minimum overlap of Contact
3λ
4λ
if wide
ECE 410, Prof. F. Salem/ Prof. A. Mason notes with updates
2λ
1λ
Lecture Notes Page 5.7
7
Design Rules: 4
• Vias
– Connects Metal1 to Metal2
– must be SQUARE and MINIMUM SIZED
– rules
•
•
•
•
•
exact size 2λ
space to self 3λ
minimum overlap by Metal1/Metal2 1λ
minimum space to Contact 2λ
minimum space to Poly/Active edge 2λ
see MOSIS site
for illustrations
http://www.mosis.org
• Metal2
– low resistance conductor used for routing
– rules
• minimum size
• minimum space to self
• minimum overlap of Via
3λ
6λ
if wide
ECE 410, Prof. F. Salem/ Prof. A. Mason notes with updates
3λ
1λ
Lecture Notes Page 5.8
8
Physical Realization of a MOSFET
• nMOS Layout
– gate is intersection of Active, Poly, and nSelect
– S/D formed by Active with Contact to Metal1
– bulk connection formed by p+ tap to substrate
• pMOS Layout
– gate is intersection of Active, Poly, and pSelect
– S/D formed by Active with Contact to Metal1
– bulk connection formed by n+ tap to nWell
Gate
Bulk
S
D
Ground
VDD
D
Gate
• Effective Gate Size
S
Bulk
– S/D will diffuse under the gate
• effective channel length is less than drawn
• Leff = L(drawn) - 2LD
– FOX will undercut active region
• effective channel width is less than drawn
• Weff = W(drawn) - ΔW
– LD and Δ W defined by fab. process
– generally taken care of by SPICE
ECE 410, Prof. F. Salem/ Prof. A. Mason notes with updates
L(drawn)
Leff
LD
Lecture Notes Page 5.9
9
Substrate/well Contacts
• Substrate and nWells must be
connected to the power supply
within each cell
n+plug
to VDD
– use many connections to reduce
resistance
– generally place
• ~ 1 substrate contact per nMOS tx
• ~ 1 nWell contact per pMOS tx
–
–
–
–
this connection is called a tap, or plug
often done on top of VDD/Ground rails
need p+ plug to Ground at substrate
need n+ plug to VDD in nWell
p+plug
to Ground
ECE 410, Prof. F. Salem/ Prof. A. Mason notes with updates
Lecture Notes Page 5.10
10
Latch-Up
• Latch-up is a very real, very important factor in circuit design that
must be accounted for
• Due to (relatively) large current in substrate or n-well
– create voltage drops across the resistive substrate/well
• most common during large power/ground current spikes
– turns on parasitic BJT devices, effectively shorting power & ground
• often results in device failure with fused-open wire bonds or interconnects
– hot carrier effects can also result in latch-up
• latch-up very important for short channel devices
• Avoid latch-up by
– including as many substrate/well contacts as possible
• rule of thumb: one “plug” each time a tx connects to the power rail
– limiting the maximum supply current on the chip
ECE 410, Prof. F. Salem/ Prof. A. Mason notes with updates
Lecture Notes Page 5.11
11
Multiple Contacts
• Each contact has a characteristic resistance, Rc
• Contact resistances are much higher than the resistance
of most interconnect layers
• Multiple contacts can be used to reduce resistance
– Rc,eff = Rc / N, N=number of contacts
N=6
• Generally use as many contacts as space allows
use several
Contacts
in wide txs
ECE 410, Prof. F. Salem/ Prof. A. Mason notes with updates
add Vias
if room
allows
Lecture Notes Page 5.12
12
Cell Hierarchy and Instancing
• Hierarchical Design
–
–
–
–
transistors used to build gates
gates used to build logic functions
logic functions used in larger blocks
build up in this manner to final chip level
transistor-level
cell
gate-level cell
function
higher level function
• Each physical design file is called a “cell”
final chip
– basic cells can be used to create a “cell library”
• elements of the cell library used to create all higher level cells
– lower level cell is called an “instance”
– construct functions by “instancing” cells into higher level cells
• details of the cell is left inside the lower level cell file
• information is not copied, but referenced
ECE 410, Prof. F. Salem/ Prof. A. Mason notes with updates
Lecture Notes Page 5.13
13
Cell Concept
• Instancing
– construct all blocks using instances of lower level cells
• tx-level cells are called “primitives” (lowest level cells)
– allow layout optimization within each cell
– eases layout effort at higher level
• higher level layout deal with interconnects rather than tx layout
• Cell View
– see only I/O ports (including power), typically in Metal1
– can’t see internal layer polygons of the primitive
Cell-level view of INV, NAND, and NOR primitives
ECE 410, Prof. F. Salem/ Prof. A. Mason notes with updates
Lecture Notes Page 5.14
14
Instancing
• Ports
– all signals that connect to higher level cells
– physical locations of the layout cell, typically in Metal1 or Metal2
• Metal1 vs Metal2 ports
– best to keep ports in Metal1 for primitives
– always try to use only the lowest level metals you can
• Building Functions from Primitives
– instantiate one or more lower-level cells to from higher-level function
– Example: f = a b
new cell has ports a, b, f (output), VDD, Gnd
NOT a
NAND
NOT
ECE 410, Prof. F. Salem/ Prof. A. Mason notes with updates
Lecture Notes Page 5.15
15
Cell Pitch
• Pitch = cell height
– Official Definition
• from middle of VDD rail
to middle of Gnd rail
– Our Definition
• from top of VDD
to bottom of Gnd
– Considerations to set pitch
• fix height for pMOS tx, nMOS tx, and some internal routing
• fix height to match height of more complex cell (e.g., flip flop)
• Transistor Orientation
– Horizontal (tx W run vertically)
• pitch sets max tx W
• cells taller & narrow
– Vertical (tx W runs horizontally)
• can increase tx W with fixed pitch
• cells short & wide
ECE 410, Prof. F. Salem/ Prof. A. Mason notes with updates
Lecture Notes Page 5.16
16
Cell Routing
• Metal1 routing strategy
☻ – very flexible
☻ – requires fewer metal layers
/ – demands much chip area for routing
Should use lowest metal for local connectivity,
and highest for “longer distances”
• High-level metal routing strategy
☻ – allows high density tx packing
☻ – minimum chip area for routing
/ – demands several metal layers
• Inter-cell routing
–
“flipped”
always use lowest level interconnect possible
ECE 410, Prof. F. Salem/ Prof. A. Mason notes with updates
Lecture Notes Page 5.17
17
Transistor Sizing
• Channel Resistance (from Chapter 3)
“ON” resistance of transistors
– Rn = 1/(μnCox (W/L) (VGS-Vtn) )
Rn
Rp
– Rp = 1/(μpCox (W/L) (VSG-|Vtp|) )
• Cox = εox/tox [F/cm2], process constant
• Channel Resistance Analysis
Vtn
VDD-|Vtp|
VG
– R ∝ 1/W (increasing W decreases R & increases Current)
– R varies with Gate Voltage, see plot above
– If Wn = Wp, then Rn < Rp
• since μn > μp
• assuming Vtn ~ |Vtp|
– to match resistance, Rn = Rp
• adjust Wn/Wp to balance for μn > μp
ECE 410, Prof. F. Salem/ Prof. A. Mason notes with updates
Lecture Notes Page 5.18
18
Transistor Sizing
• Channel Resistances
– Rn = 1/(μnCox (W/L) (VG-Vtn) )
– Rp = 1/(μpCox (W/L) (VG-|Vtp|) )
– Rn/Rp = μp/μn
• if Vtn = |Vtp|, (W/L)n = (W/L)p
• Matching Channel Resistance
– there are performance advantage to setting Rn = Rp
• discussed in Chapter 7
– to set Rn = Rp
• define mobility ratio, r = μn/μp
• (W/L)p = r (W/L)n
– pMOS must be larger than nMOS for same resistance/current
• Negative Impact
– ⇒ CGp = r CGn larger gate = higher capacitance
ECE 410, Prof. F. Salem/ Prof. A. Mason notes with updates
Lecture Notes Page 5.19
19
Transistor Matching and Scaling
• Channel Resistance Matching
– increase Wp so that Rn = Rp
– pMOS larger than nMOS
– pMOS current drive = nMOS
current drive
• Scaling ratio, S
– scaling W to increase current capabilities
– typically in unit steps, 1x, 2x, 4x, etc.
– generally L kept at
minimum value
ECE 410, Prof. F. Salem/ Prof. A. Mason notes with updates
Lecture Notes Page 5.20
20
Inverter Layout Options
• Layout with Horizontal Tx
– pitch sets max tx size
• Layout with Vertical Tx
horizontal
– allows scaling without changing
pitch
• Vertical Tx with 2x scaling
• Vertical Tx with Rn=Rp scaling
vertical
matched, Rn=Rp
ECE 410, Prof. F. Salem/ Prof. A. Mason notes with updates
Lecture Notes Page 5.21
21
Layout Alternatives
•
•
•
•
Figure 5.44
Figure 5.45
Figure 5.46
Figure 5.47
ECE 410, Prof. F. Salem/ Prof. A. Mason notes with updates
Lecture Notes Page 5.22
22
Figure 5.44 (p. 182)
Layout for an electrically symmetric NOT gate.
ECE 410, Prof. F. Salem/ Prof. A. Mason notes with updates
Lecture Notes Page 5.23
23
Figure 5.45 (p. 182)
A NAND2 and NOR2 layouts using vertical FETs.
ECE 410, Prof. F. Salem/ Prof. A. Mason notes with updates
Lecture Notes Page 5.24
24
Figure 5.46 (p. 183)
Alternate NAND2 and NOR2 cells.
ECE 410, Prof. F. Salem/ Prof. A. Mason notes with updates
Lecture Notes Page 5.25
25
Figure 5.47 (p. 184)
Complex logic gate example.
ECE 410, Prof. F. Salem/ Prof. A. Mason notes with updates
Lecture Notes Page 5.26
26
Hierarchical Cell Design
•
•
•
•
Figure 5.48
Figure 5.49
Figure 5.50
Figure 5.51
ECE 410, Prof. F. Salem/ Prof. A. Mason notes with updates
Lecture Notes Page 5.27
27
Figure 5.48 (p. 185)
Primitive polygon-level library entries.
ECE 410, Prof. F. Salem/ Prof. A. Mason notes with updates
Lecture Notes Page 5.28
28
Figure 5.49 (p. 186)
Expanding the library with more complex cells.
ECE 410, Prof. F. Salem/ Prof. A. Mason notes with updates
Lecture Notes Page 5.29
29
Figure 5.50 (p. 186)
Cell hierarchy.
ECE 410, Prof. F. Salem/ Prof. A. Mason notes with updates
Lecture Notes Page 5.30
30
Figure 5.51 (p. 187)
Effect of the flatten operation.
ECE 410, Prof. F. Salem/ Prof. A. Mason notes with updates
Lecture Notes Page 5.31
31
Figure 5.51 (p. 187)
Effect of the flatten operation.
ECE 410, Prof. F. Salem/ Prof. A. Mason notes with updates
Lecture Notes Page 5.32
32
CMOS Process Flow
• See supplementary power point file for animated CMOS
process flow (see class ece410 website and/or*
http://www.multimedia.vt.edu/ee5545/):
– This file should be viewed as a slide show
– It is not designed for printing
*Thanks to John Christiansen [mailto:christ24@pilot.msu.edu]
ECE 410, Prof. F. Salem/ Prof. A. Mason notes with updates
Lecture Notes Page 5.33
33