HCF40103B
8-STAGE PRESETTABLE SYNCHRONOUS
8 BIT BINARY DOWN COUNTERS
■
■
■
■
■
■
■
■
SYNCHRONOUS OR ASYNCHRONOUS
PRESET
MEDIUM -SPEED OPERATION :
fCL =3.6MHz (Typ.) at VDD = 10V
CASCADABLE
QUIESCENT CURRENT SPECIF. UP TO 20V
5V, 10V AND 15V PARAMETRIC RATINGS
INPUT LEAKAGE CURRENT
II = 100nA (MAX) AT VDD = 18V TA = 25°C
100% TESTED FOR QUIESCENT CURRENT
MEETS ALL REQUIREMENTS OF JEDEC
JESD13B "STANDARD SPECIFICATIONS
FOR DESCRIPTION OF B SERIES CMOS
DEVICES"
DESCRIPTION
HCF40103B is a monolithic integrated circuit
fabricated in Metal Oxide Semiconductor
technology available in DIP and SOP packages.
HCF40103B consists of an 8-stage synchronous
down counter with a single output that is active
when the internal count is zero. This device
contains a single 8-bit binary counter. It has
control inputs for enabling or disabling the clock,
for clearing the counter to its maximum count, and
for presetting the counter either synchronously or
asynchronously. All control inputs and the
CARRY-OUT/ZERO
DETECT
output
are
active-low logics. In normal operation, the counter
is decremented by one count on each positive
transition of the CLOCK. Counting is inhibited
when the CARRY-IN/COUNTER ENABLE (CI/
)
(s
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)
s
(
ct
DIP
SOP
PACKAGE
TUBE
t
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o
DIP
SOP
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P
e
ORDER CODES
HCF40103BEY
HCF40103BM1
T&R
HCF40103M013TR
CE) input is high. The CARRY-OUT/ZERO
DETECT (CO/ZD) output goes low when the
count reaches zero if the CI/CE input is low, and
remains low for one full clock period. When the
SYNCHRONOUS PRESET ENABLE (SPE) input
is low, data at the JAM input is clocked into the
counter on the next positive clock transition
regardless of the state of the CI/CE input. When
the ASYNCHRONOUS PRESET ENABLE (APE)
input is low, data at the JAM inputs is
asynchronously forced into the counter regardless
of the state of the SPE, CI/CE, or CLOCK inputs.
JAM inputs J0-J7 represent a single 8 bit binary
word. When the CLEAR (CLR) input is low, the
counter is asynchronously cleared to its maximum
count (25510) regardless of the state of any other
input. The precedent relationship between control
input is indicated in the truth table. If all control
s
b
O
PIN CONNECTION
September 2002
1/14
HCF40103B
inputs are high at the time of zero count, the
counters will jump to the maximum count, giving a
counting sequence of 256 clock pulses long.
HCF40103B may be cascaded using the CI/CE
input and the CO/ZD output, in either a
synchronous or ripple mode.
IINPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION
PIN No
SYMBOL
1
CLOCK
2
CLEAR
3
4, 5, 6, 7, 10,
11, 12, 13
CI/CE
J0 to J7
9
APE
14
CO/ZD
SPE
let
16
o
s
b
FUNCTIONAL DIAGRAM
)
s
(
ct
Jam Inputs
Asynchronous Preset
Enable Inputs(Active Low)
Terminal Count Output
(Active Low)
Synchronous Preset
Enable Input (Active Low)
u
d
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r
P
e
15
8
NAME AND FUNCTION
Clock Input (LOW to
HIGH edge triggered)
Asynchronous Master
Reset Input (Active Low)
Terminal Enable Input
VSS
Negative Supply Voltage
VDD
Positive Supply Voltage
O
)
s
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t
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P
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s
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TRUTH TABLES
CONTROL INPUTS
PRESET MODE
CLR
APE
SPE
CI/CE
H
H
H
H
L
H
H
H
L
X
H
H
L
X
X
H
L
X
X
X
Synchronous
Asynchronous
X : Don’t Care
Clock connected to Clock input
Synchronous Operation : changes occur on negative to positive clock transitions.
2/14
ACTION
Inhibit Counter
Count Down
Preset on Next Positive Clock Transition
Preset Asynchronously
Clear to Maximum Count
HCF40103B
LOGIC DIAGRAM
)
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P
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)
(s
LOGIC DIAGRAM FOR FLIP-FLOPS, FF0-FF7
s
b
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t
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s
b
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3/14
HCF40103B
TIMING CHART
)
s
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ct
u
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t
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ABSOLUTE MAXIMUM RATINGS
Symbol
VDD
od
Pr
Supply Voltage
)
(s
Parameter
s
b
O
Value
Unit
-0.5 to +22
V
VI
DC Input Voltage
-0.5 to VDD + 0.5
V
II
DC Input Current
± 10
mA
200
100
mW
mW
Top
Power Dissipation per Package
Power Dissipation per Output Transistor
Operating Temperature
-55 to +125
°C
Tstg
Storage Temperature
-65 to +150
°C
e
t
e
ol
PD
s
b
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Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied.
All voltage values are referred to VSS pin voltage.
RECOMMENDED OPERATING CONDITIONS
Symbol
VDD
4/14
Parameter
Supply Voltage
VI
Input Voltage
Top
Operating Temperature
Value
Unit
3 to 20
V
0 to VDD
V
-55 to 125
°C
HCF40103B
DC SPECIFICATIONS
Test Condition
Symbol
IL
Parameter
Quiescent Current
0/5
0/10
0/15
0/20
0/5
0/10
0/15
5/0
10/0
15/0
High Level Output
Voltage
VOH
Low Level Output
Voltage
VOL
High Level Input
Voltage
VIH
Low Level Input
Voltage
VIL
Output Drive
Current
IOH
Output Sink
Current
IOL
Input Leakage
Current
Input Capacitance
II
CI
VO
(V)
VI
(V)
0/5
0/5
0/10
0/15
0/5
0/10
0/15
0.5/4.5
1/9
1.5/13.5
4.5/0.5
9/1
13.5/1.5
2.5
4.6
9.5
13.5
0.4
0.5
1.5
r
P
e
|IO| VDD
(µA) (V)
<1
<1
<1
<1
<1
<1
<1
<1
<1
<1
<1
<1
<1
<1
<1
<1
<1
<1
<1
)
s
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ct
u
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0/18
Value
Any Input
Any Input
5
10
15
20
5
10
15
5
10
15
5
10
15
5
10
15
5
5
10
15
5
10
15
TA = 25°C
Min.
Max.
0.04
0.04
0.04
0.08
5
10
20
100
4.95
9.95
14.95
-55 to 125°C
Min.
Min.
Max.
150
300
600
3000
4.95
9.95
14.95
3.5
7
11
e
t
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s
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-1.36
-0.44
-1.1
-3.0
0.44
1.1
3.0
150
300
600
3000
1.5
3
4
-3.2
-1
-2.6
-6.8
1
2.6
6.8
u
d
o
Pr
±10-5
±0.1
5
7.5
0.05
0.05
0.05
3.5
7
11
1.5
3
4
-1.1
-0.36
-0.9
-2.4
0.36
0.9
2.4
µA
)
s
(
ct
0.05
0.05
0.05
3.5
7
11
Unit
Max.
4.95
9.95
14.95
0.05
0.05
0.05
-O
18
Typ.
-40 to 85°C
V
V
1.5
3
4
-1.1
-0.36
-0.9
-2.4
0.36
0.9
2.4
±1
V
V
mA
mA
±1
µA
pF
The Noise Margin for both "1" and "0" level is: 1V min. with VDD =5V, 2V min. with VDD=10V, 2.5V min. with VDD=15V
t
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5/14
HCF40103B
DYNAMIC ELECTRICAL CHARACTERISTICS (Tamb = 25°C, CL = 50pF, RL = 200KΩ, tr = tf = 20 ns)
Test Condition
Symbol
Parameter
VDD (V)
tPHL tPLH Propagation Delay Time
Clock To Out
tPHL tPLH Propagation Delay Time
Carry In/counter Enable To
Output
tPHL tPLH Propagation Delay Time
Asynchronous Preset
Enable To Output
tPHL tPLH Propagation Delay Time
Clear To Output
tTHL tTLH Transition Time
Clock Pulse Width
tW
Clear Pulse Width
tW
APE Pulse Width
tW
tsetup
b
O
JAM Setup Time
e
t
e
l
so
fCL
Pr
Maximum Clock Input
Frequency
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
)
(s
ct
u
d
o
SPE Setup Time
tsetup
(*) Typical temperature coefficient for all VDD value is 0.3 %/°C.
6/14
Value (*)
Min.
Unit
Typ.
Max.
300
130
95
200
90
65
650
300
200
375
180
100
100
50
40
150
90
40
160
80
50
180
80
60
140
70
50
100
40
30
1.4
3.6
4.8
600
260
190
400
180
130
1300
600
400
750
360
200
200
100
80
P
e
s
b
O
t
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300
180
80
320
160
100
360
160
120
280
140
100
200
80
60
0.7
1.8
2.4
ns
(s)
t
c
u
d
o
r
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
HCF40103B
TYPICAL APPLICATIONS
SYNCHRONOUS CASCADING
DIVIDE BY "N" COUNTER
)
s
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ct
MICROPROCESSOR INTERRUPT TIMER
u
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P
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SYNCHRONOUS CASCADING
t
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)
(s
s
b
O
t
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MICROPROCESSOR INTERRUPT TIMER
s
b
O
* An Output spike (160ns at VDD = 5V) occurs whenever two or
more devices are cascaded in the parallel clocked mode because
the clock-to-carry out delay is greater than the carry-in-to-carry-out
delay. This spike is eliminated by gating the output of the last device
with the clock as shown.
7/14
HCF40103B
TEST CIRCUIT
)
s
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CL = 50pF or equivalent (includes jig and probe capacitance)
RL = 200KΩ
t
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RT = ZOUT of pulse generator (typically 50Ω)
WAVEFORM 1 : PROPAGATION DELAY TIME (f=1MHz; 50% duty cycle)
)
(s
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8/14
s
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HCF40103B
WAVEFORM 2 : PROPAGATION DELAY, MINIMUM PULSE WIDTH AND REMOVAL TIME (f=1MHz;
50% duty cycle)
)
s
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)
(s
s
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WAVEFORM 3 : PROPAGATION DELAY, MINIMUM PULSE WIDTH AND REMOVAL TIME (f=1MHz;
50% duty cycle)
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9/14
HCF40103B
WAVEFORM 4 : PROPAGATION DELAY TIME (f=1MHz; 50% duty cycle)
)
s
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ct
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P
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s
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WAVEFORM 5 : MINIMUM SETUP TIME (f=1MHz; 50% duty cycle)
)
(s
t
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s
b
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10/14
HCF40103B
WAVEFORM 6 : MINIMUM SETUP TIME (f=1MHz; 50% duty cycle)
)
s
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ct
u
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P
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t
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)
(s
s
b
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t
c
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11/14
HCF40103B
Plastic DIP-16 (0.25) MECHANICAL DATA
mm.
inch
DIM.
MIN.
a1
0.51
B
0.77
TYP
MAX.
MIN.
TYP.
MAX.
0.020
1.65
0.030
0.065
b
0.5
0.020
b1
0.25
0.010
D
)
s
(
ct
20
E
8.5
e
2.54
e3
17.78
u
d
o
0.335
7.1
I
5.1
s
(
t
c
1.27
e
t
e
ol
bs
O
)
3.3
Z
Pr
0.100
F
L
0.787
0.700
0.280
0.201
0.130
0.050
u
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o
r
P
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t
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s
b
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P001C
12/14
HCF40103B
SO-16 MECHANICAL DATA
mm.
DIM.
MIN.
TYP
A
inch
MAX.
MIN.
TYP.
a1
1.75
MAX.
0.1
0.068
0.2
a2
0.003
0.007
1.65
0.064
b
0.35
0.46
0.013
0.018
b1
0.19
0.25
0.007
0.010
C
0.5
c1
45˚ (typ.)
D
9.8
E
5.8
)
s
(
ct
0.019
e
1.27
e3
8.89
10
0.385
6.2
0.228
4.0
G
4.6
L
0.5
s
b
O
5.3
1.27
)
(s
ete
ol
3.8
S
Pr
0.393
0.244
0.050
F
M
u
d
o
0.62
0.350
0.149
0.157
0.181
0.208
0.019
0.050
0.024
8 ˚ (max.)
t
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PO13H
13/14
HCF40103B
)
s
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(s
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from
its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications
mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information
previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or
systems without express written approval of STMicroelectronics.
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14/14