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IEEE TOPOLOGY REVIEW OF DC/DC CONVERTERS Louis Diana - MGTS 1 IEEE TOPOLOGY REVIEW Buck converter theory of operation Discontinuous vs. Continuous mode of operation Voltage mode feedback and Current mode feedback Design considerations Boost converter theory of operation Design considerations Flyback converter theory of operation Design considerations SEPIC Converter theory of operation Design considerations 2 Synchronous Buck Synchronous Rectifier DC Input SW Node Averaging Circuit Switch Output Z VCC SR Z COMP + PWM GND Control Circuit Z 3 Synchronous Buck Waveforms Continuous Conduction Mode Verror amp CLK RAMP FET SOURCE PWM FET CURRENT RECT. CURRENT Inductor current I OUT 4 Synchronous Buck Waveforms Continuous Conduction Mode As the load current goes down the converter becomes less continuous but D is still equal to Vout /Vin Verror amp CLK RAMP FET SOURCE FET CURRENT RECT. CURRENT I I OUT IND CURRENT I OUT 0A Verror amp CLK RAMP FET SOURCE FET CURRENT RECT. CURRENT I IND CURRENT I OUT 0A 5 Synchronous Buck Waveforms Discontinuous Conduction Mode The load current has gone down the the point where the converter becomes discontinuous D no longer equals Vout /Vin Verror amp CLK RAMP FET SOURCE FET CURRENT RECT. CURRENT I I OUT IND CURRENT I OUT 0A 6 Basic Relationships Continuous Conduction Mode (CCM) t on V out = D = Ts V in (V in − V out ) ⋅ D ⋅ Ts ∆I out = L Discontinuous Conduction Mode (DCM) D = 2L ⋅ I O V out ⋅ Ts V in 2 − V in ⋅ V out 7 Inductor Considerations Benefits of low L values Lower DCR Higher Isat Higher di/dt B := Vrms ⋅ 10 8 4.44 ⋅ Ae ⋅ N ⋅ f Transient response improves Less output capacitance required for given transient performance Benefits of high L values Lower ripple current Lower AC losses (skin effect, hysteresis) Lower RMS current in FETs Lower RMS capacitor current (mainly output) Continuous inductor current over broader load range Less C required for equivalent output ripple 8 General Inductor Guidelines Size for ∆IL to be 10% to 30% of full load current Winding losses usually dominate 2 2 2 PLAVG = ILRMS ⋅ RL where ILRMS = Iout + ∆ILpp 2 12 9 Inductor and FETs Normalized Switch and SR Power Loss (W) 1.25 1.20 1.15 1.10 1.05 1.00 0.95 0.90 0.85 0.80 0 10 20 30 40 50 60 70 80 90 100 IRIPPLE/ILOAD (%) Increasing ripple increases losses Similar effect for capacitor ESR loss 10 MOSFETs Both main switch and synchronous rectifier should be N-type for best efficiency Many interrelated issues Output capacitance vs. switching loss Gate capacitance vs. switching speed Gate capacitance vs. driver power loss Primary Tradeoffs Package Power loss Cost 11 Switch FET Losses vs. Frequency 0.35 Losses 0.30 Conduction Gate Switch Losses (W) 0.25 Switching 0.20 Output 0.15 0.10 0.05 0.00 100 k 10 M fSW - Switching Frequency - Hz Data for Si4866DY switch, Si4836DY rectifier, 2A ripple current and 10A load 12 Rectifier FET Losses vs. Frequency 0.35 Losses 0.30 Channel Conduction Gate Diode Conduction Switch Losses (W) 0.25 0.20 0.15 0.10 0.05 0.00 100 k 10 M fSW - Switching Frequency - Hz Note rise in diode conduction loss as Fs rises. Data assumes 20-ns of diode conduction time per SW edge 13 FET Selection Compare different FETs in both positions In general higher F and higher input voltage mean Higher switching losses therefore use lower Qg switch FET to cut switching losses For rectifier FET, low RDS(on) is most important, but don’t ignore gate power 14 SW Node Ringing Bottom Gate (1 V/div) SW (1 V/div) Can affect converter operation Worst on rising edge of SW (highest di/dt transition) Caused by parasitic L and C dV/dt Bump L in the FET from the SW node to Vin or GND C from SW node to GND High layout dependence t - Time - 50 ns/div 15 SW Node Ringing Remedies Improve layout Minimize loop areas Minimize trace inductance Keep SW node area low (secondary effect, conflicts with cooling rectifier FET) Slow down SW node edge transitions Series gate resistor in switch FET gate lead Add a snubber 16 Power Capacitors Selection Considerations Power Dissipation ESR Ripple Performance ESR Transient Performance ESR Capacitance ESL Cost Size Reliability 17 Relative Capacitors Characteristics Standard Al Electrolytic High ESR Low cost Low current capability Not really suited to DC/DC converters OSCON Low ESR Medium cost High current capability 18 Relative Capacitors Characteristics Solid Polymer Low ESR Very high cost Medium current capability POSCAP Low ESR High cost Medium current capability 19 Relative Capacitors Characteristics Tantalum Medium ESR Medium cost Medium low current capability Ceramic Very low ESR Very high cost High current capability in bulk 20 Capacitor Impedance 10 µF Ceramic 180 µF Solid Polymer 470 µF Tantalum 1000 µF OSCON 10 RCAP - Impedance - Ω 1 0.1 0.01 0.001 0.1 1 10 100 1000 10000 f - Frequency - kHz 21 Choosing Capacitor Size Input Filter Sized for AC current handling Output Filter Transient events on load Output voltage ripple 22 Input Capacitor Current Ic (sw OFF) Isw = Ic + Iin Ic (sw ON) Iin SW1 Lout + Io ∆ISWpp Cin Io Iload SW2 Cout 2 Pcap = I cap RMS ⋅ ESR cap I cap RMS 2 ∆I SW 2 pp 2 = (ISW pk − I in avg ) + ⋅ D + I in avg ⋅ (1 − D ) 12 23 Input Ripple Voltage Switch current Cin current Cin Ripple Voltage ESR Voltage C ESL Voltage Usually a secondary consideration Contribution from ESR, ESL and capacitance value 24 Output Capacitor Criteria Selection Considerations Transient performance Bulk capacitance ESR ESL Output Ripple ESR Bulk value ESL has minor effect 25 Transient Performance Iload Iinductor Output Currents Vout AC Coupled 0A ESR ESL ESL ESR Cout & ESR Cout & ESR 26 Output Capacitor Selection Considerations 2A to 10A load step @ 15A/µs Use 470µF SP: 15mΩ, 3nH To help reduce spikes, add two 10µF ceramics Yields 24.5mV undershoot 39mV overshoot 8mV spikes 21mV of ripple 27 AC VMC Model for Buck Converter VIN COMP VDD RTN KFBKEA FB VREF + VOUT XLC HDRV PVCC DIFFO VOUT KPWM VREG VC SW PWM and Drivers + VOUT SW BOOT GSNS C RLOAD RTN LDRV Oscillator Ramp Generator PGND VIN VREF + - KEA VC KPWM SW XLC VOUT TV(s) KFB 28 AC CMC Model for Buck Converter Peak CMC PWM is the result of a comparison between a control signal, a signal proportional to the inductor current, and a fixed saw tooth (for slope compensation) Whether it is: Current feedback and sawtooth vs. control signal Current feedback and control signal vs. sawtooth Control signal and sawtooth vs. current feedback From a small signal standpoint, the resulting modulation is the same! Control + Modulator Output Current Sawtooth 29 AC CMC Model for Buck Converter CS- Rs Cs VIN CS+ COMP VDD RTN KPWM KFBKE VREF FB + VC VREG + A KCS PVCC +Vout L SW VOUT GSNS XLC HDRV DIFFO + + PWM and Drivers SW Vout C Rload BOOT Oscillator Ramp Generator RTN LDRV PGND •V•IN •V•REF •+ •- •V•C •K•EA •SW •+ •K•PWM ••H•e•(s) •V•OUT •I•L •T•I•(s) •K•CS •X•LC •X•I •T•V•(s) •K•FB 30 DC/DC Boost Converter TPS40210 controller operating ~700 kHz 9- to 18-V input (12-V nominal) 24-V output with 1-A capability 31 Assumptions in Steady-State Operation 1. V•s balance across the inductor Energy “in” during a period equals energy “out” during the same period Net change of charge in a period is zero 2. Charge balance in the output capacitor Energy “in” during a period equals energy “out” during the same period Net change of charge in a period is zero 3. Ripple voltage across the capacitor is small compared to the output DC voltage 32 Basics of Operation Input No switching: VOUT ~ VIN L + D - Current Output - + SW COUT Load SW turns ON: Voltage across the inductor approaches ~ VIN Energy is stored as function of input voltage, L, tON D is biased OFF, blocking discharge of the output capacitor SW turns OFF: Stored energy is released through D to the output Non-pulsating input current – Pulsating output current Level of ripple determined by CCM or DCM operation…… 33 Basics of Operation Current Input No Switching: VOUT ~ VIN SW turns ON: L - D + Output + SW COUT Load Voltage across the inductor approaches ~ VIN Energy is stored as function of input voltage, L, tON D is biased OFF, blocking discharge of the output capacitor SW turns OFF: Stored energy is released through D to the output Non-pulsating input current – Pulsating output current Level of ripple determined by CCM or DCM operation…… 34 Right-Half-Plane Zero L Input D Output COUT SW Phase LHP Zero 20 Load 100 0 Phase RHP Zero 10 –100 Gain Phase (Degrees) Gain ( dB) The effect of any control action during the ON time is delayed until the switch is turned OFF Output response is initially in the opposite direction of the desired 40 correction 30 ⇒ RHP Zero 0 10 100 1k Frequency (Hz) 10 k 100 k 35 Continuous-Conduction Mode (CCM) Switching cycle is composed of two intervals 1. 2. When the switch is ON, stored energy builds in the inductor When the switch turns OFF, energy transfers to the output through the rectifier ♦ Inductor current ON-time slope: m IL(ON) ≈ VIN L ♦ The inductor current OFF-time slope: m IL(OFF) V − VOUT ≈ IN L ♦ The switch duty cycle: DCCM(ideal) = 1 − VIN VOUT SwitchNode Voltage VOUT ∆IL(ON) Switch Current Rectifier Current ∆IL(OFF) I OUT_AVG m IL(ON) Inductor Current m IL(OFF) Switch On Switch Off 36 Loss Elements in CCM ON Losses “ON” losses Input Voltage Inductor DCR MOSFET RDS(ON) Current sense resistor L RL RDS(ON) DCCM = 1 − D1 COUT Output Voltage Load RISENSE “OFF” losses OFF Losses Rectifier voltage drop Inductor DCR VIN + I OUT × (R DS(ON) + R ISENSE ) + Reduces to VIN + IOUT × (RDS(ON) + RISENSE ) 2 − 4I OUT × (R L + R DS(ON) + R ISENSE ) × (VOUT + Vd ) 2(VOUT + Vd ) DCCM(ideal) = 1 − VIN VOUT If losses => zero 37 Discontinuous Conduction Mode (DCM) Switching cycle is composed of three intervals 1. 2. 3. Energy is stored in the inductor during the ON time of the switch When the switch turns OFF, energy transfers to the output through the rectifier A third interval during which the energy in the inductor is zero There is essentially no current flowing in the power stage during the third interval SwitchNode Voltage VOUT VIN Switch Current ∆I L(ON) Idle period Rectifier Current ∆I L(OFF) I OUT_AVG m IL(ON) m IL(OFF) Inductor Current Switch On Switch Off t fall 38 Designing for CCM or DCM Given fixed-frequency operation, the only parameter to adjust is the inductance I OUT _ DCM = VIN × Ts × DCCM × (1 − DCCM ) 2L For a given L, this is the CCM/DCM boundary current IOUT_DCM (A) 0.15 CCM Operation 0.12 0.09 DCM Operation 0.06 0.03 0 5 10 15 VIN (V) 20 25 39 Current in CCM D COUT Load Continuous current flow in inductor Some “pedestal” in diode and switch current Diode switching and recovery losses significant in CCM Inductor Current (A) SW Output Diode Current (A) L Switch Current (A) Input 6 CCM IInductor CCM RMS = 2.1 A CCM IDiode CCM AVG = 1.0 A 4 2 0 6 4 2 0 CCM ISwitch 6 CCM RMS = 1.5 A 4 2 0 0 2 4 6 Time (µs) 40 Current in DCM D COUT Load Large peaks in all currents RMS current is higher No reverse recovery losses in the rectifier Inductor Current (A) SW Output Diode Current (A) L Switch Current (A) Input 6 DCM IInductor DCM RMS = 3.0 A DCM IDiode DCM AVG = 1.0 A 4 2 0 6 4 2 0 DCM ISwitch 6 DCM RMS = 2.2 A 4 2 0 0 2 4 6 Time (µs) 41 CCM/DCM - Differences in Current D COUT Load Peak and RMS currents are larger in DCM Conduction losses will be higher Diode-switching and recovery losses will be higher in CCM MOSFET turn-OFF losses higher in DCM For the diode rectifier, the average current is the same Inductor Current (A) SW Output Diode Current (A) L Switch Current (A) Input 6 DCM IInductor CCM IInductor DCM RMS = 3.0 A CCM RMS = 2.1 A DCM IDiode CCM IDiode DCM AVG = 1.0 A CCM AVG = 1.0 A 4 2 0 6 4 2 0 CCM ISwitch DCM ISwitch 6 4 DCM RMS = 2.2 A CCM RMS = 1.5 A 2 0 0 2 4 6 Time (µs) 42 VMC CCM Small-Signal Model Simplified small-signal block diagram VREF VIN + KEA VC – Fm D Gvd(s) VOUT Tv(s) KFB Modulator gain, Fm Control Voltage Oscillator Sawtooth 1 Fm = m a × Ts + – Oscillator Sawtooth PWM ma Control Voltage Resulting PWM 43 Peak-Current-Mode Control VIN Modulator gain VREF + KEA VC + – D Fm Gvd(s) VOUT – ACS × RISENSE TI(s) He(s) 1 Fm = m n × Ts Gid(s) Tv(s) KFB Where m n = m IL(ON) × R ISENSE × A CS VIN Error Amplifier + Switch Current Control Voltage + – A CS PWM – R ISENSE Control Voltage Switch Current mn Resulting PWM Ts 44 FLYBACK CONVERTER + + 45 FLYBACK CONVERTER Discontinuous Waveforms Verror amp CLK RAMP FET SOURCE PRIMARY CURRENT SECONDARY CURRENT 46 FLYBACK CONVERTER CONTINUOUS WAVEFORMS Verror amp CLK RAMP FET DRAIN PWM PRIMARY CURRENT SECONDARY CURRENT 47 FLYBACK CONVERTER A ring appears on the drain that is caused by the leakage inductance resonating with the Coss of the switch FET the other ring is caused by the dead time when the transformer is reset and waiting for the next on time . FET DRAIN PRIMARY CURRENT SECONDARY CURRENT 48 FLYBACK CONVERTER Discontinuous Continuous Volt seconds in equals volt seconds out ( Vout tonmax + 1 ) ( Tr ) ⋅ .9 ⋅ T − 1 ) + ( Vout ( Vinmin L⋅ V Volt seconds in equals volt seconds out + 1 ) ⋅ Tr L⋅ V Vl ⋅ Ton dI Lp ( Vinmin ) 2.5 ⋅ T ⋅ Pomax ⋅ tonmax Vinmin Ipri_p Lp 1 Pin ⋅ tonmax 2 ⋅ Lp ⋅ Ip 2 + 1 ) ⋅ Tr dI dT Vl ⋅ Ton dI L − 1 ) + ( Vout ( Vinmin dI dT + 1 ) ( Tr ) ⋅ T ( Vout tonmax L 2 Lp − 1 ) ⋅ Vinmin ( Vinmin 2.5 ⋅ Polow ⋅T Lp Pin Icpr Vinmin T 2 ⋅ tonmax Vinmin Ipri_ramp ⋅ tonmax ⋅ ton Tmax Ipri_peak .5 ⋅ Ipri_ramp Ipri_step Ipri_peak + Icpr − Ipri_ramp 49 SEPIC CONVERTER 50 SEPIC CONVERTER 51 SEPIC CONVERTER 52 SEPIC CONVERTER Design Equations Duty := Vout Vout + Vin IL1pk1 := IL1avg1 + IL1avg1 := Vout⋅ Ioutmax η⋅ Vinmin Vinmin ⋅ d max 2⋅ Lact1⋅ fs To find an inductor which will keep the converter in the continuous conduction mode this value is used for both inductors L> Vin⋅ D fs ⋅ Io⋅ Vo Vin + 1 53 4 SWITCH BUCK BOOST Boost Gate Drive Buck Gate Drive PWM Ramp Waveform Vin Max Buck Vin = Vout Boost Vin Min 54
