Glueck / Yu 2003 Mesa Preparation
Mesa preparation of Schottky-structures and pn-diodes using different
procedures for I-(V)-, C-(V)- and DLTS-measurements 1
Glück, B. K. and Xuengong Yu,
FH-Lausitz University of Applied Sciences, Senftenberg / IHP/BTU Joint Lab, Cottbus.
Abstract: Schottky-structures and pn-diodes for electrical diagnostics at Silicon with junctions
near the surface are made as Mesa structures in two ways without using lithographic mask
procedures, once covered with a thermal deposited Acetophenone (Picein) and others with
evaporated Au through a mask on the top. Both methods supplies test structures without
additional influences of temperature and radiation like it is possible with traditional lithographic
and plasma enhanced mask and etch processes. With knowledge of the etch rate, the reduction
of the dot area as a result of the undercut can be considered. The mask procedures are applied
to prepare junctions near the surface for I-(V)-, C-(V)- and DLTS-measurements for material
diagnostics.
Key Words: Acetophenone, Au, Diode, DLTS-, I(V)-, C(V)-measurements, lithography, mask, material
diagnostic, Mesa, Picein, pn-junction, preparation, Schottky-contact, self-aligning, Silicon, surface, test
structure, wet etch.
Introduction:
Mesa structures and its preparation are historical known in semiconductor technologies and also to
prepare micro electrical mechanical structures (MEMS) [1]. The manufacturing of embossed and fenced
off test structures for e. g. I(V)-, C(V)- and DLTS-measurements is also possible with these method. The
structures can be made once applying the standard photo lithographic procedures with dry or wet etch
procedures. The mainly advantage of these method is the extreme lithographic reproducibility of the dot
areas comparing to mechanical evaporation mask, but resist coating, annealing and bake procedures to
fabricate the photo resist could influence the experimental results, the development of special photo
masks needs resources and the complete preparation needs additional time. Also dry etch steps with
CF4/O2 plasma with Cr/Au dot are very comfortable [2] but not simple and radiation induced effects and
its influence to measuring results are possible and known.
Otherwise the experimental structures like pn- or Schottky junction diodes should be made without any
influence to the test device. So preparation methods are useful and efficient, which have a low degree of
physical influences e.g. radiation and temperature and can get without lithographic mask in a short time.
Two different methods - with self-aligning mask and mask free processes - were applied and compared
here in the following.
Procedure a): Silicon probes or pieces were cleaned with Piranha [3] or SC1 / SC2 [4] procedure,
followed by drying with 150 °C to remove the water layer from the surface. For metal contacts e.g. the
samples were evaporated by a electron-beam unit with W / Ti and Al on the entirely area. The following
filament evaporation with an Au layer was made though a dot mask with diameter of approximately 1000
µm. In the wet etch procedure after these the deposited Au is used as surface protection against
oxidation of the contact material and as a self aligning mask now. The Al / W was wet etched in
Phosphorous acid ( 90%, 50°C) and the Silicon was wet etched in HNO3:HF:CH2CHOOH = 2:1:1
solution, 25°C, 17 +/- 2 µm/min.
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Glueck / Yu 2003 Mesa Preparation
p-Si
Au masked samples
Au dot
Al
Ti
Implant
n-Si
CVD-Epi
3,5µm
p-Si
n-Si
Bulk
Fig. 1: Principle stack of p-type and n-type Silicon with Au-dot mask.
Procedure b): After cleaning and drying procedure analogous a) the metal (Al) was evaporated with a
filament over the hole area. Picein (4-0-ß-D-glucopyranosylacetophenon, 4'-(b-D-glucopyranosyloxy)
acetophenon) was deposited (210 °C) from hot spots with a diameter between 0,5 to 1 mm to mask the
Al dot and the Silicon below (Fig. 2).
Sample-No.
Picein
D = 500 µm
Mark Top / Left for Pos. 1
24-2
4 5
~10 mm
Dot-No.
1 2 3
6 7 8 n
Probe
Heater
Cooler
~12 mm
Fig. 2: Thermal-Resist deposition.
Picein masked sample
p-Si
Picein dot
Al
Implant
CVD-Epi
3,5µm
p-Si
Bulk
n-Si
n-Si
Fig. 3: p- and n-type samples with Picein mask before wet etching.
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Glueck / Yu 2003 Mesa Preparation
The Al and Silicon were wet etched in the same manner. The Picein mask was removed with organic
solution with transition to the wet - wet system Ethanol - DI water and drying finally as six-step
procedure:
1 - Toluol pre-clean, 30°C, 5'
2 - Toluol clean, 30°C, 10'
3 - Toluol / Isopropanol, 25°C, 5'
4 - Isopropanol / Ethanol, 25°C, 5'
5 - Ethanol / DI, 25°C, 5'
6 - DI rinse, 25°C, 10'
Results: The thermal dispensed Picein masked probes gives a typical resist behaviour such as a
perfect mask during the etch procedure. The mask adhesion on surface was without any problems. The
removing of the Picein with the six step procedure supplies a surface without films or residual layers on
the surface, showing in principle in fig. 4. In probes with Au mask it is shown a similar etch behaviour.
The opened, uncovered metal (Al / Ti) was etched firstly rapidly and subsequently was etched the Si. A
remove of the Au mask from the surface in the other case is not necessary. In opposite, it should be
helpful for long time experiments to cover the Al surface with Au. An etch rate for the Si etch R = 11,7
µm/min (25°C) was detected with similar probes.
Mesa-Etch
Al-Gate
P-Implant B-Implant
CVD-Epi, ca. 3,5µm
n-Si
p-Si
n-Si
Bulk
p-Si
n-Si
GaIn
Fig 4: Principle test structure from procedure b) after Mesa etch.
The Si-etch supplies a Mesa structured test sample. The etch per side ratio ru = D/u with approx. 1,
shown in Fig. 5 expanded, should be from interest because the field active area of the dot is reduced.
The difference of the areas, calculated with the Diameters d' and d is about 7,3 % for the given area and
etch depth. So the real active area for the measurement should be corrected with these percentage.
d
u
d’
D
p-Si
Fig 5: Situation of etch per side relation and reduction of the effective designed dot diameter d to d' by
the undercut u (left); the side etched metal covers the side slope in real (right).
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Glueck / Yu 2003 Mesa Preparation
A determination of the exact current area by using computer based rendering algorithms is one of the
possible alternatives.
140
Si Etch
120
Abrade Si [µm]
100
80
60
40
20
Rate = 11,7 µm/min
(HNO3:HF:CH2CHOOH = 2:1:3; 25°C)
0
0
2
4
6
8
10
Etch Time [min]
Fig. 6: Measured etch rate in equivalent Si probes left and a overview with a REM to the Mesa etched
dot areas of a probe, thermal structured with Picein analogous a). The reproducibility of the etched dot
areas is plainly.
Comparison of the preparation methods
Criteria
Differences of dot area
Mask preparation
Mask stability must given for:
Au etch
Dot metal / material etch
Mesa etch in Silicium
Mask removing procedures
Test structure quality
Advantages
Budget (in relation lower than photo
lithographic structured)
a) Picein structured
Procedure dependent, ca. 1%
Thermal resist apply
Dot metal + Silicium etch
Non
Mask stability given
Additional side etch
Picein remove necessary
Usable for laboratory test;
Supplies real contact surface of
the inspected system
Without additional metal and
faster preparation
Moderate, similar to b)
b) Au structured
< 1 %, dot mask
Au evaporation
Dot metal + Silicium etch
Not necessary
Mask stability given
Additional side etch
Without mask remove
Usable for laboratory test;
Additional Au - dot material
contact
Exact and oxidation free
dot area
Moderate, similar to a)
Table 1: Compare of the used methods a) and b) in relation for typical test criteria.
Comparing the methods supplies advantages and disadvantages depending the mask type a) or b). The
application should consider these arguments depending the diagnostic task. Also preparation equipment
and waste deposition and facilities should be considered.
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Glueck / Yu 2003 Mesa Preparation
Applications: Example of I-(V)-, C-(V)- and DLTS-curve of the same Mesa Dot
The measurements were carried out with the modified experimental measurement arrangement,
described in [5], were different methods with high resolution are possible. The data and curves obtained
are without any additional noise from surface relevant junction, brake down and spreading effects and in
the equal measurement relevant quality like lithographic structured probes.
70
Capacitance C (pF)
0,010
Current I (A)
0,008
0,006
0,004
0,002
60
50
40
30
20
0,000
-4
-2
0
10
2
0
5
Voltage V (Volt)
10
15
20
Voltage V (Volt)
Fig. 7: The I-(V)- (left) and C-(V)-curves (right) of the mesa-like pn diode [6].
0,00
DLTS-Signal ∆C [pF]
-0,05
Equipment & Setup: [5]
-0,10
-0,15
-1
Rate 50 sec
Ur = -4 V; Up = 3,5 V
-0,20
-0,25
100
120
140
160
180
200
220
240
260
280
300
Temperature T [K]
Fig. 8: Typical DLTS-Plot using Mesa structures made in digital mode.
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Glueck / Yu 2003 Mesa Preparation
Conclusions:
For preparations of Silicon samples, applying to electrical measurements like I-(V), C-(V) or (D)DLTS
ones, the both methods are possible. The difference is in using the mask type either Au or a thermal
resist. Test elements can be made efficient in time and budget as Mesa structures by wet etch as single
test dot from the probe with sufficient reproducibility of the dot areas.
Acknowledgement:
We have to thank the IHP/BTU Joint Lab team, leaded by H. Richter and M. Kittler which supported the
ideas, the application of the results and gives a partnership with competent and helpful discussions. We
thanks for the REM pictures were made by Mrs. Schicketanz from the FH Lausitz University of Appl.
Scs.
References:
[1] F. Völklein, T. Zetterer: "Praxiswissen Mikrosystemtechnik", 2. Aufl., Vieweg Verlag (2006).
[2] B. L. Stein, E. T. Yu, E. T. Croke, A. T. Hunter, T. Laursen, J. W. Mayer, C. C. Ahn: "Deep-level
transient spectroscopy of Si/Si1-x-yGexCy heterostructures"; J. Appl. Phys. Lett. 73, 647 (1998).
[3] L. Lester: "Safety and Training"; Nano-Systems Fab. Lab; Univ. of Manitoba, CAN; (2005).
[4] M. Köhler: "Ätzverfahren für die Mikrotechnik", Wiley-VCH, Weinheim (1998).
[5] K. Knobloch: "Analyse der elektronischen Eigenschaften von Versetzungen in Silicium ... ", Ph.D.
Thesis, Technische Universität Cottbus 1997.
[6] X. Yu, O.F. Vyvenko, M. Kittler, W. Seifert, T. Mchedlidze, T. Arguirov, M. Reiche, “Combined
CL/EBIC/DLTS Investigation of a Regular Dislocation Network Formed by Silicon Wafer Direct
Bonding”, “Beam Injection Assessment of Microstructures in Semiconductors - BIAMS 2006”, St.
Petersburg, June 2006, BIAMS Proceedings.
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