Non Linear wave shaping
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Unit- II
NON LINEAR WAVE SHAPING
Contents:

Diode clippers

Transistor clippers

Clipping at two independent levels

Clamping circuits

Clamping circuits taking source and Diode resistance

Clamping circuit Theorem

Practical Clamping circuits

Effects of diode characteristics on clamping voltage

Synchronized clamping

Comparators and applications
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NON LINEAR WAVE SHAPING
The process by which sinusoidal signal is altered by transmitting the signal
through a non-linear network is called Non-linear wave shaping.
The Non-linear networks are designed by using non-linear elements like junction diodes
or transistors.
Characteristics of junction Diodes:There is a potential barrier across the p-n junction and this be neutralized before
conduction through the junction.
The diode ready conducts when forward biased and the bias voltage is greater than the
cut-in voltage.
There is conduction through the device, when it is reverse biased.
The forward resistance of an ideal diode is zero (Rf=0) because in forward bias
maximum current flows and the reverse resistance is infinitely large (Rr=∞) because in
reverse bias no current flows.
Since a diode conducts when forward biased and blocks conduction when reverse
biased, it can be function as an electronic switch.
When the diode is conducting, it is in ON condition and the diode acts as a short circuit.
When the diode is not conducting, it is in OFF condition and the diode acts as a open
circuit.
In this we studied the clippers and clampers.
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CLIPPING CIRCUITS:A clipping circuit comprises of linear elements like resistors and nonlinear elements like junction diodes or transistors, but it does not contain energy storage
elements like capacitors.
Clipping circuits are used to select for transmission that part of an arbitrary waveform
which lies above or below some particular reference voltage level. Clipping circuits are
also referred to as voltage (or current) limiters amplitude
Selectors or slicers.
A clipper circuit can remove certain portion of an arbitrary wave form near the positive
or negative peaks.
Clipping may be achieved either at one level or at two levels.
DIODE CLIPPERS:The clippers that are designed by using diodes and resistors are diode clippers.
Diode clippers may be broadly classified into two types
(1)Shunt clippers and
(2) Series clippers.
(1) Shunt clippers:-
In shunt clippers the diode is connected in series with reference voltage across the
output terminal, shunt clippers are of two types,
(a) Clipping above the reference voltage (VR):-
The analyses of any clipper circuit have three stages
(i)A steady of working of the diode.
(ii) Formulation of the transfer characteristic equation and
(iii) Plotting of the transfer characteristic curve
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Depending upon whether a diode is ON or OFF, definite relationships obtain
between Vo and Vi in practical clipper circuits. The equation connecting (Vo / Vi ) is
termed as transfer characteristic equation.
D is the diode connected in series with battery VR and this series combination forms
a parallel path across the VR represents the reference voltage. When an input voltage Vi
is transmitted through the circuit.
Working of the diode:-
It is seen that
For Vi < VR+Vγ, the diode D is OFF fig (a), since it is reverse biased and hence does
not conduct. Since no current flows there is no voltage drop across R.
Vo=Vi for Vi < VR+Vγ.
For Vi > VR+Vγ, the diode D is ON fig (b). Since it is forward biased and the potential
barrier is overcome.
Let i denote the current.
Apply KVL to the circuit.
-Vi + iR + Vγ + iR +VR=0
i(R+Rf)=Vi-(VR+Vγ)
i= [Vi-(VR+Vγ)] /(R+Rf)
Outout voltage,Vo=Vi-iR
=Vi- [[Vi-(VR+Vγ)] /(R+Rf)] R
For forward bias Rf =0
Vo =Vi-[[Vi-(VR+Vγ)] /R] R
Vo =Vi-Vi+VR+Vγ =VR+Vγ
From the above the transfer characteristic equations are
Vo =Vi for Vi<VR+Vγ and
Vo =VR+Vγ for Vi>VR+Vγ
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Transfer Characteristic Curve:When Vo =Vi => Vo/Vi = 1 is slope = 1 and When Vo = VR+Vγ is Vo is constant
since both VR and Vγ are of fixed magnitude then Slope=0
When D is OFF, Vo=Vi,there is no clipping action and the input signal is transmitted
without any alteration of the wave shape.
However, when D is ON, it is seen that Vo is constant whatever the instantaneous
magnitude of Vi.Hence there is clipping action. The portion of the input signal greater
than (VR+Vγ) is not transmitted. This is shown in bellow fig (c).
(b) Clipping below the reference voltage VR:The clipper circuit is as shown in fig.
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Working of diode:For Vi < VR, diode is ON,
Since VR>Vi and the diode gets forward biased and the diode conducts fig (a). The
diode acts as short circuit and there is no voltage drop across it (Rf = 0). Maximum
voltage drops across R.
Let i denote the current.
Apply KVL to the circuit.
-Vi + iR - Vγ + iRf +VR=0
i(R+Rf)=Vi-VR+Vγ
i= [Vi-VR+Vγ] /(R+Rf)
Outout voltage,Vo=Vi-iR
=Vi- [[Vi-VR+Vγ] /(R+Rf)] R
For forward bias Rf =0
Vo =Vi-[[Vi-VR+Vγ] /R] R
Vo =Vi-Vi+VR-Vγ =VR-Vγ
Hence Vo= VR-Vγ.
For Vi >VR, diode D is OFF, since it gets reverse biased fig (b). There is no conduction
and no voltage drop across R.
Vo =Vi.
The transfer characteristic equations obtained are
Vo = VR-Vγ for Vi<VR
Vo = Vi
for Vi >VR
Transfer characteristic curve:When the diode is ON, clipping action readily takes place. Since the output
Vo =VR, the output voltage has the magnitude VR-Vγ. In other words, the portion of the
input voltage waveform below the reference voltage VR is readily clipped. When the
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diode is OFF, we have Vo =Vi and there is no clipping. Hence the portion of the input
signal waveform lying above the voltage VR-Vγ is readily transmitted without
attenuation.
(2) Series Clippers:In a series clipper, the diode forms a series path connecting the input and
output, and the resistor R comes in series with the reference voltage.
Series clippers are of two types
a) Clipping above the reference voltage:The circuit shown is a clipping circuit that clipping action occurs above the
reference voltage VR.
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Working of the diode:When Vi <VR the diode is forward biased and hence it conducts fig (a). Since it is
ON, it acts as short circuit, hence no voltage drop across diode because Rf=0.
Let i denote the current.
Apply KVL to the circuit.
-Vi + iR +VR=0
i(R)=Vi-VR
i= [Vi-VR] / R
Outout voltage,Vo = iR+ VR
Vo = [( Vi-VR) / R] R + VR
Vo = Vi - VR + VR
Vo = Vi
Therefore the output voltage Vo =input voltage (Vi) whatever the current.
When Vi > VR, the diode is reverse biased fig (b) and hence there is no conduction,
there is no voltage drop across R. Hence Vo = VR.
The Transfer characteristic equations are
Vo =Vi for Vi <VR and
Vo =VR for Vi>VR
Transfer Characteristic Curve:For Vi <VR, Vo=Vi :. Slope=Vo/Vi=1
For Vi >VR, Vo=VR since VR is of fixed magnitude: .slope=0
An input signal is transmitted without attenuation until Vi=VR for Vi>VR, clipping
occurs is the portion of the waveform above VR is clipped as shown in fig.
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Clipping below the reference voltage VR:The series clipper circuit is as shown in fig.
Working of the diode:
For Vi <VR it is evident that the diode D gets reverse biased. Hence it is OFF. The
diode acts as open circuit.
Hence Vo =VR.
For Vi >VR, the diode D is forward biased and hence it conducts. It acts as short
circuit. Hence no voltage drop across diode because Rf=0
Therefore Output voltage Vo = input voltage Vi whatever the current flowing.
The transfer characteristic equations are
Vo =VR for Vi < VR and
Vo =Vi for Vi > VR
Transfer Characteristic curve:For Vi < VR, Vo= VR, is some constant value with slope=0.
For Vi > VR, Vo =Vi is Vo/Vi=1 i.e slope=1.
From the above characteristic equations clipping occurs till Vi=VR, and the portion
of the input signal waveform above VR is transmitted without attenuation. This is shown
in fig.
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Some Single-ended clipping Circuits:
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In the clipping circuits, the diode may appear as a series or shunt element. The use of
diode as a series element has the disadvantage that when diode is off and is intended
that there be no transmission. But fast or high frequency waveforms may be transmitted
to the output through the diode capacitance.
The use of diode as a shunt element has the disadvantage that when diode is off
and is intended that there be transmission, Diode capacitance with all other capacitances
in shunt with the output terminals will round off the sharp edges of the input waveform
and attenuates the high frequency signals.
Clipping at two Independent levels:We studied how clipping can be achieved either above or below a certain
reference level, using shunt or series clipper. Diode clippers can also be used in pairs
to achieve clipping at two independent levels. The diodes may be arranged in parallel
or in series.
1) Diodes in parallel arrangement:Let D1 and D2be two ideal diodes arranged in parallel as shown.Let it be required to
clip the input signal Vi at two different levels VR1 and VR2 is below VR1 and above
VR2.Also ,let VR2>VR1.
Working of the diode:(i) For Vi<VR1,it is seen that the diode D1 gets forward biased, and diode D2 gets
reverse biased fig (a). Hence D1 is ON, short circuited and D2 is OFF, open circuited.
:. The output voltage Vo =VR1.
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(ii) For VR1< Vi<VR2, it is evident that both diodes get reverse biased fig (b). Hence D1
is OFF is open circuited and D2 is OFF is open circuited.
Finally the output voltage Vo =Vi.
(iii)Vi >VR2, it is seen that diode D2 gets forward biased and diode D1 gets reverse
biased. Hence D1 is OFF is open circuited and D2 is ON is short circuited.
The output voltage Vo = VR2.
Transfer characteristic equations:Vo =VR1 for Vi<VR1
Vo =Vi for VR1<Vi<VR2
Vo =VR2 for Vi>VR2
Transfer characteristic Curve:From the above transfer characteristic equations
The above circuit using two diode in parallel can be used for converting sine wave to
square wave.
Let VR1 and VR2 be the reference levels and VR1=-VR2. Also, the amplitude of the
input sine wave be large compared to the difference of the reference voltage levels.
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From there it appears that the transfer characteristic passes through the origin and the
input signal is clipped symmetrically at top and bottom.
The circuit is shown in fig.
Working of the diode:For Vi <-VR2, it is seen that the diode D1is reverse biased and D2 is forward biased.
Hence D1 is OFF is open circuited and D2 is ON is short circuited.
:. Output voltage, Vo= -VR2
For Vi >VR1, it is seen that diode D1 and D2 are reverse biased. Hence D1 and D2 are
OFF in both are open circuit.
:. Output voltage,Vo=Vi
For Vi >VR1, it is seen that diode D1 is forward biased and diode D2 is reverse biased.
Hence D1 is ON is short circuited and D2 is OFF is open circuited.
:. Output voltage,Vo=VR1.
Transfer characteristic equations:Vo = -VR2 for Vi<-VR2
Vo =Vi for -VR2<Vi<VR1
Vo =VR1 for Vi >VR1
Transfer characteristic curve:From the above transfer characteristic equations
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From the above waveform, the i/p sinusoidal voltage has been clipped at both top
and bottom symmetrically, if Vm >>VR+Vi it is obvious that the output waveform is
almost a square wave. Therefore the circuit is termed as squaring circuit clipping at two
levels may also be achieved by using two zener diodes.
2) Diodes in parallel:
Working:
i)
When Vi > VR1 , D1 is ON and D2 is OFF fig(a). Hence Vo = VR1
ii)
When –VR2<Vi<VR1, D1 is OFF and D2 is OFF fig (c) . Hence Vo=Vi
iii)
Vi< -VR2 , D1 is OFF and D2 is ON fig(b). Hence Vo= -VR2
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Transfer characteristics:
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Some double-ended clippers:
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Zener Diode Clipper circuit:The clipping at two levels using a pair of zener diodes is shown in fig.D1 and D2
are zener diodes which are joined in series opposing each other.
When the input signal becomes sufficiently positive, the zener diode D1conducts just
like ordinary diode which is forward biased, and the other diode D2 breaks down which
is reverse biased.
The output voltage Vo =Vγ1+VZ2, where Vγ1=cut in voltage of D1, VZ2 = breakdown
voltage of D2.
Since Vγ1 and VZ2 are both fixed, the output voltage is clipped at this level, whatever
the amplified of the input voltage Vi.
When Vi goes sufficiently negative, diode D2 gets forward biased and conducts
and diode D1 breaks down which is reverse biased.
The output voltage Vo= (Vγ2+VZ1), where VZ1=break down voltage of D1 and Vγ2=cut
in voltage of D2.
:. The output voltage Vo is clipped at this level.
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If the input signal is a sinusoidal wave and if the zener diodes D1 and D2 are
identical then the transfer characteristic curve input and output wave forms are shown
in fig.
TRASISTOR CLIPPER:The transistor has two pronounced nonlinearities which may be used for clipping
purposes. One occurs as the transistor crosses from cut in into the active region, and the
second occurs when the transistor crosses from the active region to saturation.
Therefore, if an input signal waveform makes excursions which carry the transistor
across the boundary between the active and saturation regions, a portion of the input
waveform which keeps the transistor in the active region shall appear at the output
without distortion.
The transistor clipper circuit is shown in fig(a)
fig(a)
The resistance R in the circuit represents either the source resistance Rs or the base
resistance Rb in the above lead. This resistance R must be large in comparison with the
input resistance of the transistor in its active region (hie).We also assume that the Cut
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in voltage of the transistor zero. Under these circumstances the input base current will
very nearly have the waveform of the input voltage
iB = (Vi-Vγ)/ R
, where Vγ is the base-to-emitter cut in voltage.
Vγ = 0.2V for Ge and Vγ = 0.6 for Si
Waveforms for the clippers are shown in fig(b) Consider that the input
signal Vi is a ramp which starts at a voltage below cut-off and carries the transistor into
saturation. The voltage scale for an n-p-n germanium transistor shown in fig(b).The
slope dVBE/dt of the base waveform is related to the slope dVi/dt of the input by
dVBE/d t= [hie/(R+hie)]dVi/dt
The input impedance hie decreases as the transistor goes further into the active region,
and consequently the slope of dVBE/dt decreases also. When the transistor enter into the
saturation, the input impedance drops to a low value. This abrupt lowering of the input
resistance results in a sharp limiting of the voltage VBE and the waveform remains
constant at the base-to-emitter voltage corresponding to saturation.
Now we will see the waveform of the base current.
The slope of the base current iB is given by
diB/dt = [1/(R+hie)] dvi/dt
The input impedance decreases as the transistor goes further into active region and
hence iB increases as the transistor goes further into the active region and eventually
into saturation.
In the active region, as shown in fig (b) the collector current will have the same form
as the base current. In saturation, the collector current will remain constant at
Ic= [(Vcc-VCE(sat)) / Rc] = Ics
The limiting occurs when iB > (Ics/hfe)
The slope of Ic is greater than iB because we know Ic = βiB.
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Fig (b)
The waveforms which result when a sinusoidal voltage Vi carries the transistor
from cut-off to saturation are shown in fig (c). The base circuit is biased so that cut in
occurs when VBE reaches the voltage V.
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Fig (c)
TRANSISTOR EMITTER-COUPLED CLIPPER:
The double ended emitter coupled clipper is shown in fig.
Qualitatively the operation of the circuit is as follows. Consider initially that
the input voltage Vi is negative enough to ensure that Q1 is in cut-off. We consider that
VBB2 has been adjusted that it biases the transistor Q2 to operate in the active region.
As Vi increases,Q1 will eventually come out of cut-off and it is conducting;Q2 is also
ON and is conducting. Both transistors carry currents, operating in the active region
and the amplified input signal appears at the output.
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As Vi continuous its excursion in the positive direction the common emitter will
follow the base of Q1.Since the base of Q2 is fixed, a point will be reached when the
rising emitter cuts-off Q2.
Thus the input signal is amplified but clipped twice, once due to the cut-off of Q1,
and a second time due to the cut-off of Q2.
Transfer Characteristic of the emitter coupled clipper:From the circuit emitter current is
I Re - VEE- VBB2 + V2= 0.
=> I= I1+I2 = (VBB2+VEE-V2 ) / Re ------------------ (1)
V2 is the base to emitter voltage, this changes by only 0.2v from cut into saturation.
Hence as long (VBB2+VEE) >>V2, I remains essentially constant.
From the circuit. IC2 = (Vcc-Vo) / Rc => Vo= Vcc-IC2Rc
The upper limited level is Vou=Vcc (:. IC2=0) and corresponds to I2=0 and I1=I.
The lower output limited level is VOL=Vcc-IC2.Rc and corresponding to I1=0 and I2=I.
and we know that I2 = IC2 + IB2
I2 = IC2 [1+ (1/hfe)]
=> I= IC2 [1+ (1/hfe)]
=> IC2 = I / [1+ (1/hfe)]
where I is obtained from equation (1)
Since the current varies exponentially with base to emitter voltage (V1 or V2) the
cut-off levels are approached asymptotically.
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Let us therefore define the upper input levels ViU to corresponds to I2=0.1I and
I1=0.9I. Similarly we define the lower input level ViL corresponds to I1=0.1I and
I2=0.9I.
From the circuit
-Vi +V1-V2+ VBB2 = 0
=> Vi =VBB2+V1-V2
----------------------
(2)
For finding Vi we will require base to emitter voltages (V1&V2).We know base to
emitter voltage is
VE = ηVT ln 1- [(IE + αI IC) / IEO ]
___________ ( 3)
We know IE = IC+ IB here IB is very less so neglected.
=> IE = IC
IEO = emitter junction reverse saturation current
VE = ηVT ln 1- [(IE + αI IE) / IEO ]
From (3)
In the above expression first term is very less compared to second term so we will
neglected.
VE = ηVT ln [- [(1 + αI) IE] / IEO]
Since V1= VE if I1= IE and V2 = VE if I2= IE
Then from equation (2)
Vi =VBB2 + ηVT ln [- [(1 + αI) I1] / IEO]
- ηVT ln [- [(1 + αI) I2] / IEO]
Vi =VBB2 + ηVT ln [I1/ I2 ]
Hence
Viu = VBB2 + ηVT ln [0.9I /0.1 I ] = VBB2 + ηVT ln 9
ViL = VBB2 + ηVT ln [0.1I /0.9 I ] = VBB2 - ηVT ln 9
The transfer characteristics are shown in fig.
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Series and Shunt Noise Clippers
Practically actual signals are mostly associated with unwanted noise signals. The
presence of noise may adversely affect sensitive circuits. So noise signals must be
eliminated to make the actual signal free from distortion and fluctuations.
Noise signals can be eliminated by employing noise clippers. These clippers use
two or more diodes depending upon whether the noise is small or large. Noise clippers
are of two types: i) series noise clippers ii) shunt noise clippers
i)
Series noise clippers:
This type of clippers are used when the noise amplitude is not greater than Vγ the
forward voltage drop of the diode and the signal voltage has amplitude larger than Vγ.
When the input signal along with noise (fig (a)) is applied at input of above circuit, D1
will conduct when amplitude exceeds Vγ, D2 conducts when amplitude falls bellow Vγ and no diode will conduct when - Vγ < Vi < +Vγ . Therefore the noise within the
limits of - Vγ and + Vγ is clipped and signal above Vγ during positive cycle and signal
bellow - Vγ during negative cycle will appear at output (fig b).
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Shunt noise clipper:
Compensation for Variation of Temperature
The forward voltage at which a semiconductor diode breaks and starts conducting
depends on its junction temperature. The break point decreases by 2mV/○C rise in
temperature. In an ideal diode the breakpoint occurs at zero voltage. Since practical
clipper circuits use semiconductor diodes, the exact point on the input signal at which
clipping occurs also depends on temperature.
Several techniques are adopted in practice to compensate for the effect of
temperature changes. A practical diode may be visualized as an ideal diode in series
with a voltage source as shown in fig (a). a series clipper using a practical diode is
shown in fig (b).
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The following are the techniques adapted for temperature compensation.
1. A diode D2 whose voltage source Vγ compensates for Vγ of diode D1 is
connected in series with D1 as shown in the fig (c). A voltage source V’ in
series with resistance R’ is connected in parallel with D2 in order to keep D2
conducting all the time for transmission of the signal to the output.
2. Another circuit which provides temperature compensation is shown in fig (d).
This arrangement avoids the use of V’. In this arrangement, the battery VR not
only acts as the reference voltage but it also keeps the diode D2 conducting if
Vi < VR
Vo = VR-Vγ2 if Vi<VR
Vo= Vi-Vγ1 if Vi>VR
3. Another alternative temperature compensated clipping circuit is shown in fig
(e)
When Vi < VR, D1 is off, D2 is on, Vo= VR-Vγ2
When Vi > VR, D1 is on, D2 is off, Vo= Vi-Vγ1
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CLAMPING CIRCUITS:A function that must frequently accomplished with a periodic waveform is the
establishment of the positive or negative extremity at some constant reference level
(VR), the circuits used to perform this operations are referred to as clamping circuits.
Whenever a circuit point becomes connected through a low impedance (as
through a conducting diode) to some reference voltage VR, we say that the point has
been clamped to VR.(since, in these applications, a voltage change in only one direction
is restrained, the circuits are called one-way clamps. Two diodes may be used to
established a two-way clamp)
We know that a capacitor blocks the passage of direct current. Hence when a nonsinusoidal, periodic signal is transmitted through a capacitive coupling circuit, it loses
its d.c. component. If it is necessary to restore the signal with its d.c. component at a
later stage, the signal needs to be passed through a clamping circuit.
Since the clamping circuit restores or reinserts the lost d.c. component, it is also
termed as d.c. restorer or d.c. inserter circuit.
A clamping circuit also finds use when the d.c. value of a signal is to be shifted
from one level to another level.
Classification of clamping circuits:Mainly clamps are two types
(i) Negative clamp (or positive peak clamper)
(ii) Positive clamp (or negative peak clamper)
Negative Clamp:This is also termed as positive peak clamper, since the circuit clamps the positive
peak of a signal to signal to zero level. This type of clamper introduces a negative d.c.
value. Hence the name negative clamp. The basic circuits are shown in fig.
D is an ideal diode.
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Let the input be a sinusoidal signal Vi =Vm sinωt
During the first quarter cycle of the input wave, when Vi goes positive, it
seen that the diode gets forward biased and hence conducts. The capacitor C gets
charged. At the end of with quarter cycle, Vi = Vm. The capacitor charges to Vm, with
polarity as shown in above fig.
Since Rf=0, there is no voltage drop across the (ideal) diode, with the result that V0=0.
As the instantaneous amplitude decreases during the quarter cycle, we expect
the capacitor to discharge. But this cannot happen, since there is no resistance through
which it can discharge. The voltage across capacitor remains Vm.
:. The output voltage is Vo=Vi-Vm.
During the negative half-cycle, the diode gets reverse biased and doesn’t conduct.
During the sub sequent positive half-cycles, the voltage across the capacitor remains
fixed at Vm, and when steady state is reached,
we have
Vo=Vi-Vm
The charged capacitor acts as a voltage source Vm.
:. For Vi=0, Vo = -Vm.
For Vi=Vm, Vo = 0
For Vi= -Vm, Vo = -2Vm
It can be seen that the positive extremities of the output voltage are clamped to zero
level. The output wave is also seen to be sinusoidal, thus there is no distortion of waveform. The steady state has been obtained by after one quarter cycle.
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Suppose that after the steady state has been attained, the amplitude of the input
signal is increased. Then there will be again be an interval of the one quarter cycle, at
most, during which the diode will conduct.
When the amplitude of the input signal decreases it is a required that the D-C voltage
across the capacitor decrease. But there is no path for capacitor to decrease. To permit
a decrease in capacitor voltage, it is necessary to shunt a resistor across C or
equivalently to shunt a resistor across the diode. A circuit with such a resistor R is
shown in fig and also output waveforms.
The first two complete cycles correspond to the steady state condition after
the large-amplitude signal had been applied for a long time. At the time t = t1, the
amplitude is abruptly reduced. Since the capacitor cannot discharge rapidly, the positive
peaks of the sinusoidal fall short of attaining 0V.The voltage across C falls
exponentially as a C discharges and after some cycles, the positive peaks again reach
zero. For now, even after the voltage across 'C' has dropped to the point where the
positive peaks reach zero voltage, the capacitor continuous to discharge through R and
the generator resistance. Therefore the diode must now supply to the capacitor, at the
time of this positive excursion of the signal. The charge lost by the capacitor when the
diode is not conducting.
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POSITIVE CLAMP:
This is also termed as negative peak clamper, since this circuit clamps the negative
peaks of a signal.The -Ve peak clamper introduces a +Ve d.c value, hence the name
+Ve clamp.
The basic circuit is as shown in fig.
Let the input signal be Vi =Vm sinwt. It is clear that the diode gets forward biased and
conducts, as Vi goes negative.
The capacitor charges to voltage Vm, with polarity shown in fig.
:. Under steady state conditions, the capacitor acts as a voltage source and output is
Vo=Vi-(-Vm) => Vo=Vi+Vm.
For Vi= 0, Vo = Vm
Vi=Vm, Vo= 2Vm
Vi= -Vm, Vo= 0
The output voltage waveforms are
When the input waveform amplitude decreases, the output will adjust to its new value
as shown in bellow fig:
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Non Linear wave shaping
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Biased Clamping :
If a voltage source of VR volts is connected in series with the diode of a clamping
circuit, the input waveform will be clamped with reference to VR. Some examples of
biased clamping is given bellow.
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Clamping circuit taking source and diode resistances into account:By taking the source and diode resistance into account the clamping circuit
becomes.
Fig.1
The source resistance may be negligible or may range up to many thousands of ohms
depending on the source, and we shall assume cut in voltage Vγ occurs at zero voltage.
When the input is positive, the diode is ON and the equivalent circuit is shown in fig
(2) for that R>>Rf
When the above condition is not valid (i.e R is not much greater than Rf (R≈ Rf)), then
Rf must replace by the parallel combination of R and Rf .
When the diode is not conducting the equivalent circuit is shown in fig (3) that
Rr >>R.
If the back resistance of the diode is not very large in comparison with R,
R must be replaced by the parallel combination of the two.
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The steady-state output wave form for a square wave input:Consider a square wave is applied to the clamping circuit of fig (1).The general
form of the output waveform is shown in fig (4) and is determined by the four voltages
V1,V1',V2 and V2'.
Consider conditions at t=0When Vs=V'' and Vo =V2'.
Since the diode is reverse biased at this time, fig(3) is applicable and the capacitor
voltage is
VC=V''- (R+Rs)V2' /R ------(1)
Fig. 4
At t=0+, the input signal jumps to V', the output to V1,the diode conducts and fig(2) is
applicable.
Since the voltage across the capacitor cannot change instantaneously, it remains
same as in eq (1),
From fig (2)
Vc=V'- [(Rf+Rs) V1 /Rf ]-----(2).
from (1)&(2), V''- [ (R+Rs)V2' /R ] = V'- [(Rf+Rs) V1 /Rf ]
Since the peak-to-peak input amplitude is V=V'-V''.
V= V'-V'' = [ (Rf+Rs)/Rf)
]
V1-
[ (R+Rs)/R)V2']
In a similar manner, by considering conditions at t =T1- & T1+
We obtain
V= [ (Rf+Rs)/Rf)
]
V1’-
[ (R+Rs)/R)V2]
Since in the interval T1 the diode is conducting, the output decays with a time
constant (Rf+Rs) C, hence
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V1'=V1 e[-T1/ (Rf+Rs)C]
During interval T2 the diode is reverse biased and the circuit time constant (R+Rs) C ,
V2'=V2 e[-T1/ (R+Rs)C]
so that
If the source resistance Rs is quite small and can be ignored than the above
expressions becomes
V=V1-V2'=V1'-V2.
:. The waveform of the output, in the steady-state is independent of the average level
of the input signal.
Clamping Circuit Theorem:This theorem states that "under steady conditions, the ratio of the area Af under
the output curve in the forward direction (when the diode conducts) to the area under
the output curve in the reverse direction Ar (when the diode does not conducts) is given
as
Af / AR = Rf /R
Proof:- Consider the simple negative clamp circuit as shown in fig 1. Equivalent
circuits are shown in fig 2 and fig 3 above. Square wave input and outputs are shown
in fig 4.
In the interval 0<t<T1 ,the input is at its upper level ,diode is on and the
equivalent ckt of fig2 results. If vf(t) is the output waveform in the forward direction
,then the capacitor charging current is
if(t)=vf(t)/Rf
therefore, the charge gained by the capacitor during forward interval is
𝑇1
𝑇1
Qg=∫0 if(t)dt = 1/Rf ∫0 𝑉𝑓(𝑡) 𝑑𝑡 = Af /Rf
In the fig3 shown the diode D is OFF during the interval from T1 to T1+T2.
Hence the capacitor C discharges.
ir(t)=vr(t)/R
Here ir = Vr / R where Vr is reverse output voltage.
Let ir denote the discharge current. The charge lost in the time interval T1 to T1+T2
𝑇1+𝑇2
is given Ql =∫𝑇1
𝑇1+𝑇2
𝑖𝑟 dt = 1/R ∫𝑇1
𝑉𝑟(𝑡) 𝑑𝑡 = Ar / R
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Under steady state condition the net charge acquired by the capacitor over one cycle
must be equal to zero. Therefore, the charge gained in the interval 0<t<T1, will be equal
to charge lost in the interval T1<t<T1+T2, i.e; Qg = Ql
𝐴𝑓
𝑅𝑓
=
𝐴𝑟
𝑅
𝐴𝑓
i.e; 𝐴𝑟 =
𝑅𝑓
𝑅
Practical Clamping Circuit
Perfect flatness of the positive and negative peaks of a square wave can be obtained
only if the capacitor C is arbitrarily large. Practically, in clamping circuits the capacitor
C is such that (Rf + Rs)C << T1, and (R+Rs)C >>T2. So a square wave after clamping
appears as shown in the figure (a).
Figure (a): output of practical clamping circuit for square wave input
This is because during the interval T2, when (R+Rs)C >>T2, the capacitor
discharges very slowly and hence there will be a small tilt Δr in the output.
Diring interval T1, when (Rf + Rs)C << T1, the capacitor charges very fast and hence
there will be small spike of magnitude Δf, at the beginning, and for the remaining
interval T1, the output will be zero. The overshoot Δf is smaller than the tilt Δr .
For the case shown in above figure the voltage values are
V1’ = 0, V2 = -V(R/R+Rs)
Where V is the amplitude of discontinuity in input.
V2’ = V2 𝑒 −𝑇2/(𝑅+𝑅𝑠)𝐶 , Δr = V2’- V2
𝑅𝑓
Δf = V1- V1’ =V1 = 𝑅𝑓+𝑅𝑠
𝑅
𝑅+𝑅𝑠
Δr
Even if we assume the capacitor C is arbitrarily large, unless the source resistance Rs
is zero, the part of the input signal which occurs when the diode is conducting appears
at the output multiplied by
𝑅𝑓
𝑅𝑓+𝑅𝑠
, and the signal which occurs when the diode is not
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conducting appears at the output multiplied by
𝑅
. Usually
𝑅+𝑅𝑠
𝑅
𝑅+𝑅𝑠
is much closer to
𝑅𝑓
unity than 𝑅𝑓+𝑅𝑠. Such selective attenuation flattens that part of the signal, which drives
the diode into conduction. This distortion is more easily observed in the case of signal
with a sharp peak such as the ramp fig(b). The output of practical clamping circuit for
Ramp input is shown in fig(c). It is not appear in the case of square wave because it has
flat top and bottom. Quite independent of the distortion, the clamping circuit theorem
Af/ Ar = Rf/R is valid.
Figure(b) : Ramp input
Figure (c): output of practical clamping circuit.
In the case of biased clamping, i.e when a reference voltage source VR is
connected in series with diode to clamp the signal positively or negatively with
reference to VR, for perfect circuit operation, the positive excursion of the signal with
reference to its average value must be larger than VR. if the diode break down voltage
Vγ is not negligible, the clamping circuit theorem for biased clamping is
𝐴𝑓−(𝑉𝑅+𝑉𝛾)𝑇1
𝐴𝑟
=
𝑅𝑓
𝑅
Where T1 is interval over which diode is forward biased and R>>Rf.
THE EFFECT OF DIODE CHARACTERISTICS ON THE
CLAMPING VOLTAGE
For the clamping circuit shown in fig (A), to obtain the steady-state response, the diode
is replaced by Rf when ON and Rr = ∞ when OFF. Though the positive peak of the
signal in the output is ideally required to be clamped to the zero level, in practice it is
clamped to a voltage Vcl = Vγ, where Vγ is the cut-in voltage of the diode. In a practical
diode, the current variation is non-linear in nature. Hence, we consider the influence of
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the diode characteristics on the clamping voltage, Vcl and show that the clamping
voltage (Vcl) changes with a change in the amplitude of the input signal.
Let us consider the clamping circuit described in Fig (A) and let its input be a
symmetric square wave as shown in Fig. (B).
Figure (A)
FIGURE (B) A symmetric square-wave input with peak-to-peak amplitude V
If C is large, irrespective of whether the diode is ON or OFF, the time constants are
large so that the output is also a square wave. The steady-state output has a general form
as shown in Fig. (C).
FIGURE (C) The steady-state output with a large C
In obtaining the steady-state response, we assumed that the diode is ideal with a
small Rf. In practice, however, an idealized diode, when ON, is represented as a switch
in series with a battery voltage of Vγ, a resistance Rf [see Figure (D)]; and biased by V′ as
shown in Fig. (B).
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We now consider the V–I characteristic of the practical diode to understand the
influence of the diode characteristics on the clamping voltage. The diode current is
given by the relation:
When the diode is ON, the positive peak of the signal is clamped to Vcl and the current
in the diode is Icl. Vcl is the voltage to which the positive peak is clamped.
FIGURE (D) The equivalent circuit of the forward-biased diode
The equivalent circuit when the diode is ON, when vs = V′ with RS = 0 is shown in Fig.
(E). From Fig.(E):
During the negative half-cycle of the square-wave input, vs = V″ and the diode is OFF.
The equivalent circuit is given in Fig. (F).
From Fig. (F):
And
Using Eqs. (4) and (5):
In practice, Vcl ≈ Vγ and V can be typically of the order of a few tens of volts.
Thus, V >> Vcl. From Eq. (6): neglecting Vcl,
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FIGURE (E) The equivalent circuit when the diode is ON
FIGURE (F) The equivalent circuit when the diode is OFF
As the net voltage across R is V, Ir the discharging current of C is given by the
relation:
Ir= V/R
(8)
As the input is a symmetric square wave, under steady-state, the charge gained by
C when the diode is ON should be equal to the charge lost by C when the diode is OFF.
Therefore,
Icl = Ir
(9)
From Eqs. (2) and (8):
Taking natural logarithms:
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Equation (11) gives the steady-state clamping voltage and Eq. (12) describes the
variation in the clamping voltage with a change in the amplitude of the input signal. For
a silicon diode used in a clamping circuit for which Vcl = Vγ = 0.5 V, η =2, V = 10 V
and dV = 1 V:
Equation (12) suggests that as V increases, the change in the clamping voltage, dVcl,
becomes smaller. Also, when the diode is ON, V is the forward-bias. Hence, to ensure
that the clamping voltage remains unaltered, the diode must be forward-biased by a
larger voltage. The circuit for this is represented in Fig. (P).
Let us now try to calculate dVcl for this circuit to verify whether this arrangement
really ensures negligible change in Vcl or not. Redrawing the circuit in Fig.(P) gives
Fig. (Q). The equivalent circuit when the diode is ON, i.e., when vs = V′, is shown in Fig.
(R).
FIGURE (P) A clamping circuit in which the diode is forward-biased by a large
voltage VYY
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FIGURE (Q) The modified circuit of Fig. (P)
From Eq. (2):
Icl = I0eVcl/ηVT
From Fig. (R):
as Vcl << VYY.
Writing the KCL equation at node A:
Also
When the input goes to V″, the diode is OFF and the equivalent circuit is as shown
in Fig. (S).
The discharging current Ir is:
FIGURE (R) The equivalent circuit of Fig. (Q) when the diode is forward-biased
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FIGURE (S) The equivalent circuit of Fig.(Q) when the diode is OFF
since R >> RS. Put Eq. (16) in (17):
But V′ − V″ = V. Therefore:
We know that V >> Vcl and RS << R. Therefore:
As the input is a symmetric square wave, If = Ir. Therefore, from Eqs. (15) and (18):
As RS << R:
From Eq. (2):
Taking logarithms to the natural base:
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If a ‘Si’ diode used in the clamping circuit, for which η = 2, VT = 26 mV, dV = 1
V, V = 10 V and VYY = 50 V:
On the contrary, dVcl (when VYY = 0) = 5.2 mV (calculated earlier).
We see from the above calculations that dVcl with large VYY (= 50 V) is approximately
one-tenth of dVcl with VYY = 0. Thus, the use of a biased diode improves the stability of
the clamping level. However, one major constraint in the circuit of Fig. (P) is that the
diode will remain ON continuously if the input signal (V) is small. The minimum peakto-peak value of the signal V can be determined as follows:
When the input magnitude is V′, D is ON, the voltage across the diode is Vγ so that
the current in R is [from Eq. (13)]:
When the input drops by V, the current IS through RS is, IS = −V/RS. If IR >> IS, then
the diode is continuously ON. Therefore, to make sure that diode switches OFF when
the input falls to V″, IR ≤ IS.
Hence, for the proper circuit operation, Eq. (22) has to be satisfied in the clamping
circuit of Fig. (P).
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SYNCHRONIZED CLAMPING
In the clamping circuits examined in this chapter, the duration for which clamping is
effective is controlled by the signal alone. The signal remains clamped as long as its
amplitude remains unaltered. However, in some applications it may become necessary
that the time of clamping be determined by the control or gating signal that occurs
synchronously with the signal. Two or more signals are said to be synchronized if they
arrive at a particular reference point in their cycles at the same time. The simultaneous
presence of the gating signal during the period of constant amplitude input enables the
two waveforms to be synchronized and the output to be referenced to VR. One typical
application could be in a CRO, where, for the spot to move vertically, the signal applied
to the X-deflecting plates of the CRT varies in both directions but returns to a reference
level VR, as shown in Fig.(a).
FIGURE (a) The signal that varies in both directions but is referenced to VR
Let the signal then be transmitted through a capacitive coupled network like a highpass network shown in Fig.(b).
For the duration 0 to T1, when the input is a ramp, the output varies exponentially
from point A with a time constant τ. At t = T1, both the input and the output fall by V,
giving rise to an under-shoot. During the interval T1 to T2, as the input remains constant,
the output decays exponentially to zero (point B). A similar variation takes place during
the period the signal is negative. The resultant output waveform vo is shown in Fig.(c).
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FIGURE (b) A high-pass RC circuit
FIGURE (c) The output of a capacitive coupling network (high-pass circuit)
This output is devoid of a dc component. To reintroduce the dc component, we apply
a signal referenced to the zero level [see Fig. (d)] as input to the circuit, as shown in Fig.
(e). The output waveform of this circuit is shown in Fig.(f).
FIGURE (d) The input signal
Figure (e) The switch S operates in sync with the signal to clamp the output to VR
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FIGURE (F) The output of the circuit in Fig.(e)
FIGURE (P-a) A synchronized clamping circuit
When the switch S closes, during the interval T2, vo = VR. When the switch S opens
during the intervalT1, C charges resulting in the waveform shown in Fig.(F). The small
spikes can be reduced to negligible values if the switch has a zero resistance in the ON
position.
The circuit in Fig. (e) can be implemented practically using diodes D1 and D2, and
two control signals v1 and v2, with a 180° phase shift, as shown in Figs. P(a), Q(a) and
Q(b). If the signal in Fig. Q(c) is referenced to the zero level; the output in Fig. Q(d) is
referenced to VR.
FIGURE P(b) The circuit when D1,D2 are ON; FIGURE P(c) the circuit when D1,D2 are
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OFF
FIGURE Q. The waveforms of a synchronized clamping circuit
Tc is the time duration of the control signals and Tn is the time period during which
the control signals are zero. The input to the clamping circuit is synchronized with the
control signals v1 and v2. Since the input vs is referenced to the zero level, the purpose
of this circuit is to introduce a dc voltage (VR) so that the output vo is now referenced
to VR instead of the zero level. From the circuit in Fig. P(a), it is evident, for the
given polarities of the control signals that the diodes D1 and D2 conduct during the
period Tc, resulting in the circuit of Fig. P(b). As v1 and v2 are of equal magnitudes but
of the opposite polarity, their net effect is zero at the output. The result is the output VR.
However, when the control signals are zero, diodes D1 and D2 are OFF, resulting in
the circuit of Fig. P(c). The input is transmitted to the output terminals with a slight
distortion in amplitude, as the capacitor charges exponentially. The output of this circuit
is now referenced to VR, meaning that a dc voltage VR is introduced by the clamping
circuit.
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COMPARATOR:A clipper circuit may also be used as a comparator. Basically a comparator is a
circuit which can be employed to mark the instant when an arbitrary waveform attains
a certain reference level.
The basic difference between a clipper and a comparator is that whereas in a
clipper circuit, a signal is clipped at the desired level and remaining input is reproduce,
in a comparator there is no such interest involved in reproducing any desired portion of
the signal. A simple diode comparator shown in fig.
Let the input signal be a ramp. The input signal Vi crosses the reference voltage
level VR at t=t1.
The output voltage Vo remains at VR until t=t1.Beyond t=t1, the output rises with the
input signal.
Comparators may be non-regenerative or regenerative. Clipping circuits fall into
category of non-regenerative comparators. In regenerative comparators, positive feedback is employed to obtain an infinite forward gain. Examples of regenerative
comparators are Schmitt trigger and blocking oscillator.
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Applications of Voltage Comparators:1. Accurate time Measurement:
A comparator may be used as a voltage-to-time converts, and time intervals
can be measured accurately. This mode of time measured is extensively adopted in
modern radar systems.
2. A comparator finds use as an Analog to digital converter.
3. A sine wave can be converted into a series of pulses, if a comparator is used with a
d.c. reference voltage, by reference voltage. This finds may applications in
communications.
4. A comparator can be used as a sine wave-to-square converts. By setting the
reference voltage to zero, a symmetrical square wave can be obtained.
5. A comparator can be used as a phase-meter and the phase angle between two
sinusoidal signals can be measured. This requires that the reference voltage be zero.
Each of then two sine waves is applied to the comparator, and the time interval between
the pulses obtained with the two waves is measured. This time interval is proportional
to the phase difference between the sine waves.
6. Pulse time modulation: if the reference voltage is modulated by a certain
information, and a periodic sweep voltage is applied to a comparator, a train of pulses
would result and relative spacing between the pulses indicates the modulated signals
containing the information. Thus the time modulation system can obtain.
7. Comparator can use as amplitude-distribution analyzer.
----- ***** -------Review Questions
1. What is ment by clamping? Discuss about different types clamping circuits.
State and prove clamping circuit theorem.
2. Determine Vo for the following circuite
3. Explain transfer characteristics of emitter coupled clipper and derive necessary
equations.
4. Draw basic ckt of positive peak clamping ckt and explain its operation.
5. Explain about synchronized clamping.
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6. What is clipping in wave shaping? Explain different types of clippers with
neat circuits and transfer characteristics.
7. Discuss the operation and applications of voltage comparator.
8. Briefly explain about transistor clipper
9. Explain the effect of diode characteristics on clamping voltage.
10. With neat circuit and waveforms explain the operation of double diode
clipping.
11. Explain the principle of clamping. What is the need of resistor R in parallel
with diode in basic clamping circuit.
12. Explain the response of clamping ckt when square wave is applied in study
state condition.
13. What is the effect of Rf and Rs in clamping operation?
14. The input voltage to the fig is varying linearly 0-80v. draw the output and
transfer characteristics.
15. The input voltage to the above fig is varying linearly 0-100v. draw the output
and transfer characteristics.
16. Explain two level transistor clipper and derive necessary equations for input
voltage swing.
17. For the ckt shown in fig., Vi is sine wave of peak 100v. assume ideal diodes
sketch one cycle of output voltage. Determine the max.diode current.
18. The input voltage to the fig is varying linearly 0-150v. draw the output and
transfer characteristics. Indicate each region which diodes are conducting.
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