MOS Gate Dielectrics
Prof. Krishna Saraswat
Department of Electrical Engineering
Stanford University
Stanford, CA 94305
saraswat@stanford.edu
araswat
tanford University
1
EE311 / Gate Dielectric
Outline
•Scaling issues
•Technology
•Reliability of SiO2
•Nitrided SiO2
•High k dielectrics
araswat
tanford University
2
EE311 / Gate Dielectric
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Scaling of MOS Gate Dielectric
ID ∝ Charge x velocity
∝ Cox (VGS - VT) x velocity
∝ Cox (VGS - VT) x velocity
Cox "
!
K
thickness
(Ref: S. A sai,
Microelectronics Engg., Sep t. 1996)
Gate SiO2 thickness is approaching < 20 Å to improve device performance
• How far can we push MOS gate dielectric thickness?
• How will we grow such a thin layer uniformly?
• How long will such a thin dielectric live under electrical stress?
• How can we improve the endurance of the dielectric?
araswat
tanford University
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EE311 / Gate Dielectric
Problems in Scaling of Gate Oxide
Polysilicon gate electrode
Dopant
penetration
Leakage current
gate oxide
Reliability due to
charge injection
Defects and
nonuniformity of film
Dielectric breakdown
Si substrate
• Below 20 Å problems with SiO2
– Gate leakage => circuit instability, power dissipation
– Performance degradation due to tox(electrical) > tox(physical)
• Carrier quantization in the channel and depletion in poly-Si gate
– Degradation and breakdown
– Dopant penetration through gate oxide
– Defects
araswat
tanford University
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EE311 / Gate Dielectric
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Leakage Current Contributions
VDD
poly gate
n+
IG
n+
ISUB
IGIDL
p-well
IJ
Source: Marcyk, Intel
Relative contributions of OFF-state leakage (but magnitude of total leakage
getting exponentially worse for deeper submicron nodes)
130nm
100nm
65nm
ISUB Subthreshold leakage from source
IGIDL Gate-induced drain leakage (GIDL)
IJ
Junction reverse-bias leakage
IG
Gate leakage (direct tunneling)
Source: Assenmacher, Infineon (2003)
araswat
tanford University
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EE311 / Gate Dielectric
Quantum Mechanical Effect under gate oxide
 Band bending under gate oxide creates a quantum well that splits
carrier energy band into subbands
 The spatial distribution of carriers is modified with the maxima in
the semiconductor
 This results in additional capacitance
Carrier Concentration - Classical
Electron energy
Carrier Concentration - Quantum Mechanical
Conduction Band
Depth Under Gate Oxide
Energy Band Split
Cox CQ
araswat
tanford University
CQ : additional capacitance from
quantum mechanical effect
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EE311 / Gate Dielectric
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Performance degradation due to
tox(electrical) > tox(physical)
reduced Cox
increase EOT
)
Electron Concentration (/cm
2.00E+20
3
2.5 nm gate oxide
.
1.50E+20
Quantum
mechanical
Classical
1.00E+20
5.00E+19
Quantum mechanical
Classical
0.00E+00
0
1
2
3
4
5
Depth (nm)
Ref: Buchanan et al., Proc. ECS Vol. PV 96-1, 1996
Ref: T.-Y. Oh PhD thsis, Stanford Univ. 2004
• The maximum of carrier concentration is located ~ 1nm under the gate oxide
• Corresponds > 20% of physical gate oxide thickness of current technology
• Effect of quantization is to increase effective tox and thus reduce Cox
araswat
tanford University
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EE311 / Gate Dielectric
Carrier depletion in poly-Si gate.
Gate depletion
Reduced Cox
increased EOT
tox(electrical)
tox(phy sical)
Gate
Oxide
Substrate
(B uchanan and Lo, Proc. ECS Vol. PV 96-1, 1996)
 High E - field due to a combination of higher supply voltage and thinner
gate oxide causes band bending even in heavily doped poly-Si gate
 This causes depletion in poly-Si gate, especially for boron doping
 Effect of depletion is to increase effective t ox and thus reduce Cox
araswat
tanford University
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EE311 / Gate Dielectric
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Combined Effects of Depletion and Quantization
Si surface charge
centroid few Å’s away
from oxide interface
Cox = εox / EOT
EOT = Equivalent Oxide Thickness
Poly-Si Gate
poly depletion (band
bending) results from
nonzero conductivity
gate charge centroid
few Å’s away from
oxide interface
n+ poly gate
p-well
VG
Depletion Region
CD.R.
Gate Dielectric
CG.D.
Q.M. Thickness
CQ.M.
Si Substrate
gate
oxide
EOTTOT = EOTD.R. + EOTG.D. + EOTQ.M.
• Combined effect of depletion and quantization is to
increase effective tox and thus reduce Cox
• A reduced Cox implies reduction in gm and thus ID(on)
araswat
tanford University
9
EE311 / Gate Dielectric
Outline
•Scaling issues
•Technology
•Reliability of SiO2
•Nitrided SiO2
•High k dielectrics
araswat
tanford University
10
EE311 / Gate Dielectric
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Resistance Heated Furnace
(or H20)
Si + O2 = SiO2
Si + 2H2O = SiO2 + 2H2
• Batch processing ⇒ low cost
• High thermal mass ⇒ long process times.
• Ideal for growing thick oxides.
• Multiprocessing for nitrided oxides not easy to do.
araswat
tanford University
11
EE311 / Gate Dielectric
Lamp Heated Rapid Thermal Oxidation
Control
System
Shroud
Quartz Window
Gas
out
Wafer
Gas In
Chamber
Acoustic
Temperature
sensor
Thermometer
• Single wafer processing ⇒ real time measurement and control
• Low thermal mass ⇒ short process times.
• Ideal for growing ultrathin gate oxides.
• Multiprocessing ideal for composite dielectrics, e.g., nitrided oxides.
• Rapid thermal CVD of ultrathin Si3 N 4
araswat
tanford University
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EE311 / Gate Dielectric
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Plasma CVD System
RF
~
Plasma
Chuck
Primarily used in low temperature applications, e.g., TFTs for displays
araswat
tanford University
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EE311 / Gate Dielectric
Atomic layer CVD (ALCVD)
Gas input
1) ZrCl4(g)
Showerhead
2) ZrCl4(ad)
Wafer
3) ZrCl4(ad) + 2H2O (g) →ZrO2 (ad) + 4HCl (g)
Heated Pedestal (>400oC)
4) ZrO2(ad)
• Deposition is done one monolayer at a time: excellent control
• Being investigated for high-k dielectrics like ZrO2, HfO2
araswat
tanford University
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EE311 / Gate Dielectric
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Microstructure of SiO2
Amorphous SiO2
Tetrahedra
O
O
O
O
O
Si
Si
O
O
O
Si
O
O
O
O
Si
O
O
Si
Si
O
O
O
Si
O
O
O
O
O
O
Si
Si
Si
Si
O
Si
O
O
Si
O
O
O
Si
O
O
O
O
O
Crystalline SiO2 consists of ordered networks of
corner-sharing SiO4 tetrahedra In the amorphous
SiO2, the basic structural unit is the SiO4
tetrahedron with each Si atom surrounded by four
O atoms. The angle of O-Si-O bonds is fixed at
109.5o. However, the Si-O-Si angle is rather
flexible. Each O atom bridges two neighboring
SiO4 tetrahedrons. The bond is relatively easy to
bend, stretch or rotate. The Si-O-Si bonds are
capable of accommodating large lattice distortion
O
Crystalline quartz
O
araswat
tanford University
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EE311 / Gate Dielectric
MOS Gate Dielectrics
Outline
•Scaling issues
•Technology
•Reliability of SiO2
•Nitrided SiO2
•High k dielectrics
araswat
tanford University
16
EE311 / Gate Dielectric
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Ideal MOS
Oxide
3.1 eV
Si
Si
1.1 eV
+
3.8 eV
• The microstructure gives rise to a band structure
with a large band gap of about 9 eV
• Large barriers between Si and SiO2
araswat
tanford University
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EE311 / Gate Dielectric
Conduction in Dielectrics: Tunneling
Fowler-Nordheim Tunneling
Oxides > 5 nm
!b
Direct Tunneling
Vox
e
Vox
!b
Oxides < 3 nm
e
n+ poly
n+ poly
sub
sub
(a)
J=
A=
AEo2 xe
q3m
8"hm ox # b
araswat
tanford University
(b)
$
V 3 '
"B %1" (1" ox ) 2 (
#b )
&
2
J = AE ox exp
E ox
B
"
E ox
B=
8" 2m o x # b
3
m is the mass of electron in vacuum
mox is the average electron mass in the oxide
2
3hq
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EE311 / Gate Dielectric
!
9
Conduction in Dielectrics: Leakage
Trap Assisted Tunneling
Traps
Traps
• Trap assisted tunneling resulting in leakage at low gate voltage
• An increase in traps will cause more leakage
• Traps are present in as grown dielectric
• Traps can be generated by electrical stress
araswat
tanford University
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EE311 / Gate Dielectric
Conduction in Thin Oxides
THIN OXIDE
Direct tunneling
P.E.
THICK OXIDE
FN tunneling
P.E.
Ref: Gup ta, et al., IEEE Electron Dev. Lett. Dec. 1997
Below ~35 Å direct tunneling causes excessive gate current
araswat
tanford University
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EE311 / Gate Dielectric
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Hot Carrier Generation due to High E-field
Channel
Source
Drain
• The E-field can be very high in the channel, especially near the drain
• The free carriers passing through the high-field can gain sufficient
energy
araswat
tanford University
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EE311 / Gate Dielectric
Hot Electrons and Holes
• At high electric fields the carriers are accelerated to high velocities
• These energetic carriers are termed as hot carriers
araswat
tanford University
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EE311 / Gate Dielectric
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Hot electron injection
Hot electron injection
Fowler-Nordheim Tunneling
e
e
(b)
(a)
• Electrons being injected have to
be highly energetic to overcome
the barrier
• Hot electrons can be produced
in drain depletion region
• Hot holes behave similarly
• Requires sufficient band
bending for electrons to tunnel
into the conduction band of the
oxide
araswat
tanford University
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EE311 / Gate Dielectric
Hot carrier effects in an MOS transistor
• The free carriers passing through the high-field can gain
sufficient energy to cause several hot-carrier effects.
• This can cause many serious problems for the device operation,
e.g. change in Vt, gm, leakage, junction breakdown
araswat
tanford University
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EE311 / Gate Dielectric
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Non Volatile Memories
• Carrier injection is also used beneficially for making non volatile
memories
• Vt shift due to carrier trapping during program and erase
functions
araswat
tanford University
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EE311 / Gate Dielectric
Dielectric Degradation Mechanisms
• Degradation during device operation due to high E field causing current injection
• Degradation during fabrication due to charging in plasma processing
Electron energy at anode
After DiMaria et al. (IBM)
e (1)
Cathode
n(E)
(3)
0
e
(5)
h
(2)
(6)
e
(3)
(4)
Oxide
h
Anode
5
E (eV)
10
(1) Electron injection
(2) Energy released by hot electron
(3) Bond breaking - trap generation
(4) Hot hole generation
(5) Energy released by hot hole - trap generation
(6) Hydrogen release - trap generation
Dielectric damage and breakdown is due to interface trap generation
initiated by the energy loss of injected electrons and holes
araswat
tanford University
26
EE311 / Gate Dielectric
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Intrinsic Dielectric Breakdown
Damage cluster
Damage
Cathode
SiO2
Anode
Damage initiation
Damage propagation
Breakdown
• Damage initiates at anode and cathode interfaces causing degradation.
• Eventually it spreads throughout the body of the dielectric causing breakdown.
• Degradation can be minimized if damage at the interfaces is prevented
araswat
tanford University
27
EE311 / Gate Dielectric
Extrinsic Breakdown
Particle
Structural weakness
Pinhole
Interface roughness
SiO2
• Damage initiates at an extrinsic defect present in the oxide
• Eventually it spreads throughout the body of the dielectric
causing breakdown.
• Degradation is minimized by careful processing to reduce
process induced defects
araswat
tanford University
28
EE311 / Gate Dielectric
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Methods of testing degradation
and breakdown in dielectric films
gate
I v(t)
substrate
Ramped voltage stress
Vg
A voltage (or current) stress is applied to a
capacitor. The current (or voltage) is
monitored till the device breaksdown. Time
to breakdown (tbd) and total injected charge
to breakdown (Qbd) are then determined
Constant current stress
Constant voltage stress
Voltage
BV
Vbd
electron trapping
hole
trapping
Breakdown
Qbd=Jstress x tbd
tbd
Time
araswat
tanford University
tbd
Time
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EE311 / Gate Dielectric
Stress Induced leakage Current
Ref: Dumin, et. al., IEEE Trans.
Electron Devices. May 1993
traps
• Electrical stress in SiO2 causes leakage to increase at low gate voltages
• Electrical stress generates traps
• Leakage is caused by traps assisted tunneling
araswat
tanford University
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EE311 / Gate Dielectric
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Breakdown Statistics
100
80
Intrinsic Breakdown
60
40
Breakdown due to defects
20
0
0.1
1.0
10.0
Charge to breakdown Qbd (C/cm 2)
100.0
• Intrinsic breakdown has higher Qbd
• Extrinsic breakdown results in early breakdown
• A good set of devices should not have early breakdown
araswat
tanford University
31
EE311 / Gate Dielectric
Qbd vs. Trap Generation Rate≈
Qbd (Coul/cm2)
102
101
Tox = 30 - 250 Å
100
T = 20 - 300°C
Jox = 10-2 - 1 A/cm2
10-1
Ref: Apte et. al.,
J. Electrochem . Soc, March, 1993
10-2
10-1
100
101
102
103
(Trap Generation Rate)-1
dQinj/dVg (Coul/V-cm2)
• Qbd and net trap generation track for different oxide thickness,
stress current density and temperature
• Higher trap generation rate causes lower Qbd
• Dielectric damage and breakdown is due to interface trap generation
initiated by the energy loss of injected electrons and holes
araswat
tanford University
32
EE311 / Gate Dielectric
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Dependence of tbd on Electric Field
10
!
4 nm
EF
log(tbd (90%) (ms))
n+ Si gate
n+
b1
E1
e-
E1
Q bd1
<
E2
!
> Q bd2
EF
p+ SiGe gate
b2
E2
p+
e-
pp-
p+ Si gate
(b)
(a)
const I
const V on n+Si gate
1
9
10
11
12
13
14
E (MV/cm)
Ref: Yang, et. al., IEEE Trans. Electron Dev., July 1999
Energy diagrams for (a) n+ poly-Si and (b) p+
poly-Si gate MOS capacitor on p- substrates.
Barrier height is 3.1 eV for n+ gate and 4 eV
for p+ gate. Higher barrier height gives larger
oxide electric field and therefore lower Qbd at
a fixed current density.
Higher E field in gate oxide ⇒ higher electron energy at the anode
⇒ lower Tbd
araswat
tanford University
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EE311 / Gate Dielectric
Effect of Area on tBD
Area A1
Breakdown site
Area A2
Ref: Degreve, IRPS 1997
• Device with larger area has higher probability of containing a breakdown site
⇒ Larger area devices have lower tBD
• Measurements made on larger area capacitors need to be correlated to
smaller area transistors
araswat
tanford University
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EE311 / Gate Dielectric
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Effect of Electrical Stress Temperature
on Qbd
100
25 C
BB
7 nm SiO2
B
10
BB
B B
Qbd (C/cm2)
100 C
J J J
J
J
1
200 C
H
J
B
B
B
B
J
J
H
H
H
0.1
H
H H
H
300 C
0.01
1E-5
F
F
F
F
1E-4
1E-3
1E-2
1E-1
1E+0
1E+1
Jox (A/cm2)
• Higher stress temperature results in lower Qbd
• Important for plasma induced damage
araswat
tanford University
Ref: Apte et. al., J. Electrochem . Soc, March, 1993
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EE311 / Gate Dielectric
Substrate vs. Gate Injection
Gate
THIN OXIDE: Direct tunneling
-Vg
P.E.
Si
THICK OXIDE: FN tunneling
Si
Gate
P.E.
+Vg
Ref: M. Dep as et al., Electrochem S oc., Vol. PV96-1, p . 352, 1996
Qbd is lower for gate injection of electrons ⇒ Effect of the strained transition layer
As gate oxide thickness decreases Qbd is not affected much for substrate injection
but decreases for gate injection ⇒ Effect of the strained transition layer
For ultrathin oxide direct tunneling dominates resulting in lower energy electrons in
the SiO2. Thus damage is reduced and Qbd increases.
araswat
tanford University
36
EE311 / Gate Dielectric
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Transition (Strained) Layer at the
Substrate Interface
THICK OXIDE
THIN OXIDE
SiO2
Gate
SiO2
Transition layer SiOx
Substrate
Transition Layer
• Structural inhomogenity (1-2 monolayers) due to transition from Si to SiO2
• Stress due to volume change during SiO2 formation.
• Strained bonds are easier to break resulting in lower Q bd for gate injection of electrons.
• For thinner films the transition layer becomes a significant fraction of the total layer.
For increased reliability of deep submicron devices, technology
must be developed to reduce the impact of the transition layer
araswat
tanford University
37
EE311 / Gate Dielectric
Why is there a stress?
During thermal oxidation,
+126% volume increase from Si --> SiO2
compressive stress
SiO2
Si
O
SiO2 O
!
!
Si Si Si Si
Si
O
!
Si
higher stress
(less viscous flow)
araswat
tanford University
O
!
Si Si
Si
lower stress
(more viscous flow)
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EE311 / Gate Dielectric
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Correlation Between Stress and Qbd
Tbd
100
e
1000
50% wet O 2
Si
1000°C,30% O2
2% wet O2
!
100
Si
dry O2
10
!’
Si substrate
1
750
Relaxed Si-O-Si bonds
in the oxide bulk
Tbd (90%) (sec)
"
tbd (90%) (sec)
Gate
800
850
900
950
growth temperature (°C)
Stressed Si-O-Si bonds
in the transition layer
Vg-
J= - 300mA/cm2
1000
1050
1000°C,70% O2
800°C,30% O2
10
800°C,70% O2
1
20
40
60
80
Tox (Å)
100 120
Ref: Yang and Saraswat, IEEE Trans. Electron Dev., Ap ril 2000
• Thinner SiO2 films are more susceptible to degradation (for FN tunneling)
• Degradation is always more for conditions resulting in higher physical stress
in SiO2.
• Higher temperatures, steam oxidation and longer growth times allow stress
relaxation through viscous flow and hence result in SiO2 of better reliability.
araswat
tanford University
39
EE311 / Gate Dielectric
Effect of Gate Electrode
10
4 nm
Rough interface
Gate oxide
Silicon substrate
log(tbd (90%) (ms))
Poly-Si gate
1
9
n+ Si gate
p+ SiGe gate
p+ Si gate
const I
const V on n+Si gate
10
11
12
13
14
E (MV/cm)
• Gate electrode roughness at the oxide/gate interface causing
enhanced localized electric field intensity.
• Gate electrode workfunction impacts electric field intensity
• Higher electric field intensity results in lower reliability
araswat
tanford University
40
EE311 / Gate Dielectric
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Effect of Bulk Electron Trapping
Constant Current Stress
e
e
Vg
e
e
e
e
!Vg
Time
4.0
3.5
3.0
50
Silane - 600 oC
2.5
2.0
1.5
1.0
0.5
0.0
-0.5
40
TEOS - 1000 oC
30
Dry oxide
Silane-1000 oC
TEOS-1000 oC
20
Silane - 1000 oC
10
Dry oxide
0
2.0
0 10 20 30 40 50 60 70 80 90 100
Stress time (sec)
Silane-600 oC
2.5
3.0
3.5
Change in |Vg|(V)
4.0
Ref: Bhat, et. al., IEEE Trans. Electron Devices., Ap ril 1996
• Degradation by bulk electron trap generation is observed in deposited oxides used as gate
dielectrics in applications such as non volatile memories and TFTs for flat panel displays
• It can be minimized by a high temperature anneal
araswat
tanford University
41
EE311 / Gate Dielectric
MOS Gate Dielectrics
Outline
•Scaling issues
•Technology
•Reliability of SiO2
•Nitrided SiO2
•High k dielectrics
araswat
tanford University
42
EE311 / Gate Dielectric
21