Unity Power Factor Control for Three Phase Three
Level Rectifiers without Current Sensors
Bingsen Wang
Giri Venkataramanan
Ashish Bendre
Dept. of Electrical and Computer Engineering
University of Wisconsin – Madison
Madison, WI 53706
bingsen@cae.wisc.edu; giri@engr.wisc.edu
Advanced Development Group
DRS Power and Control Technologies
Milwaukee WI, USA
ashishrbendre@drs-pct.com
Abstract— Three level rectifiers with reduced number of
switches (such as the Vienna Rectifier) have been receiving wide
interest in the past years to improve the input power quality of
rectifier systems. In this paper, a new carrier-based pulse width
modulation (PWM) control algorithm is proposed for such
converters to eliminate the low frequency harmonics in the line
current while achieving unity power factor at the rectifier input
terminals. The operating constraints of the Vienna Rectifier with
the carrier-based modulation strategy are examined carefully
and the proposed control algorithm ensures that appropriate
voltage/current directional constraints are met. A promising cost
reduction opportunity can be seen with elimination of input
current sensing to operate the Vienna Rectifier. The control
algorithm is verified via Saber simulation and experimental
results.
Keywords - Unity power factor; Vienna Rectifier; Phase angle
control; Carrier based PWM;
I.
INTRODUCTION
New generations of adjustable speed drive and power
supply producers are increasingly incorporating input power
factor and waveform control to comply with various regulatory
standards [1]. From time to time, specific applications such as
aerospace power require careful regulation of the power
converter front-end line current harmonics to minimize
undesired interaction among the equipment connected to the
same utility grid. A slew of new topologies including the ones
based on three level power conversion have been proposed to
realize high quality input waveforms [2-6]. Among these, the
topology proposed by Kolar in 1994, called the Vienna
Rectifier has the additional benefits of reduced controlledswitch count in addition to the general the benefits of threelevel converter. Thus, due to the opportunities of competitive
cost reduction, Vienna Rectifier is generally considered
attractive [5, 6].
Several control approaches have been proposed for the
Vienna Rectifier. The initial application proposed the use of a
hysteresis current controller. The switching signals are
generated by comparison of reference current template
(sinusoidal) and the measured mains currents [4]. Although this
approach is easy to implement, the switching frequency is not
constant, which is not desired for some applications because of
inter-harmonics. The ramp comparison current control
IAS 2005
presented in [6] derives the duty cycle by comparison of
current error and the fixed-frequency carrier signal. The ripple
current in the input inductor makes the current error noisy even
though synchronization is carefully considered. The space
vector modulation was analyzed in [3] with recognition of the
constraints imposed by the unidirectional nature of the rectifier.
For all the approaches mentioned above, the measurement of
input currents is necessary.
In this paper a new PWM control algorithm without input
current sensing is proposed. Reactive component design
considerations of three level converters are presented in Section
II. In Section III, the operating limitations of the Vienna
Rectifier are examined under the reduced switch realization. In
Section IV, the state space averaged model for the Vienna
Rectifier is developed. Then the proposed control algorithm
and the controller design suitable for the Vienna Rectifier are
presented in Section V. Computer simulations results verifying
the proposed approached are presented in Section VI, backed
up by experimental results in Section VII. The concluding
section presents a summary of the paper.
II.
REACTIVE ELEMENT DESIGN CONSIDERATIONS
A general three-phase three-level rectifier using ideal single
pole triple throw (SPTT) switches is illustrated in Figure 1. The
realization of the SPTT switch will be discussed in the
subsequent section. Appropriate sizing of the reactive elements
is crucial to fulfill the purpose of this active front-end instead
of passive diode bridge, which is typically to meet the line
current harmonic requirement prescribed by the regulation
standards or certain applications. The sizing of the input
inductors for three-level converters is very similar to the twolevel converter case. With proper modulation, the harmonics of
pole voltages are pushed close to switching frequency and
higher. For the same converter rating and harmonic
specifications, the three-level converter input inductor is
smaller since the peak-to-peak ripple voltage seen by the
inductor is only half of the dc bus voltage.
However, the dc-link capacitor sizing is quite different due
to the third harmonic current flowing to the dc bus neutral
point. For typical modulation schemes, the switch in each
phase leg will be modulated between the top throw and the mid
point for half cycle while in the other half cycle the switch will
1677
0-7803-9208-6/05/$20.00 © 2005 IEEE
be toggled between the bottom throw and the neutral point.
Thus, during any interval of π/3, the charging current to the top
dc capacitor will be from either one phase-leg or two phaselegs. The dc link neutral current contains low frequency third
harmonics due the inherent feature of three-level converters,
which will usually increase the necessary dc link capacitor
sizing unless special modulation function is applied [2]. The
typical neutral current and its spectrum from sinusoidal PWM
modulation are shown in Figure 2. The resulting size of the
capacitor is generally bigger than the critical minimum value
considered from dynamic interaction between the dc link
capacitor and the input inductors [7]. This is in contrast with
two-level converters, in which case, all three phase-legs supply
the dc link current during each switching period. Thus, the dc
bus sees no low frequency harmonics.
La
ia
Lb
+
van
vbn
ib
Lc
+
Cdc
ic
A
La
Qb
RL
Qc
Db2
Lb ib
ia
+
vbn
+
ic
+
vcn
- 2
Da1
Cdc
+
vcn
N RL
Qa
Cdc
Da2
Da1
+
Vdc
- 2
+V
Cdc
A
Qa
ia
- 2
0.006
0.008
0.01
0.012
0.014
0.016
Cdc
t (s)
10
A
5
ia
Cdc
Da2
0
20
40
60
80
SWITCH REALIZATION CONSTRAINTS
The ideal SPTT switch can be realized using different
combinations of controlled switches and diodes. One of the
realizations is the unidirectional topology with reduced count
of controlled switches is the Vienna Rectifier as shown in
Figure 3. In each phase-leg, only one controlled switch is used.
With assumption of continuous conduction mode (CCM), the
IAS 2005
+V
dc
- 2
RL
+V
Cdc
A
Cdc
ia
Vdc
- 2
N RL
Qa
dc
- 2
+
Da2
+V
dc
- 2
(d)
Figure 4. Conduction paths for phase-leg A when (a) the line current is
positive and the controlled switch is off; (b) the line current is positive and the
controlled switch is on; (c) the line current is negative and the controlled
switch is off; (d) the line current is negative and the controlled switch is on;
Figure 2. Waveform of the neutral point current and its spectrum for
sinusoidal modulation.
III.
(c)
100
f (×60 Hz)
Cdc
Da1
+
Vdc
- 2
N
Qa
Da2
RL
(b)
Da1
10
+
Vdc
- 2
N
dc
(a)
0.004
2
Figure 3. Schematic of the power circuit of the Vienna Rectifier
+ Vdc
0
0.002
Vdc
-
Dc2
Lc
2
n
RL
ia
0
Vdc
N
C
Da2
10
FFT(iN) (A)
+
Cdc
A
iN (A)
B
Qa
Figure 1. Schematic of the three-phase three-level rectifier using ideal SPTT.
0
Dc1
-
van
N
Db1
Cdc
+
+ V
dc
- 2
Cdc
Da1
rectifier pole voltages (vAN, vBN, vCN) have a definite state
determined by on/off states of controlled switches and the
polarity of line currents at any instant of operation. For
instance, if the line current ia is positive and the controlled
switch Qa is off, the voltage between the converter pole A and
dc bus midpoint N vAN is Vdc/2. The conduction path for this
case is illustrated in Figure 4. (a). If the line current ia is
positive and the controlled switch Qa is on, the voltage vAN is 0,
1678
0-7803-9208-6/05/$20.00 © 2005 IEEE
in which case the conduction path is illustrated in Figure 4. (b).
Similarly, if the line current ia is negative, the voltage vAN can
be either -Vdc/2 if the switch Qa is off or 0 if the switch Qa is on
as illustrated in Figure 4. (c) and (d), respectively. This
operating principle also applies to phase legs B and C. To avoid
low frequency (lower than the switching frequency) harmonics
in line currents, the rectifier phase voltages must be free of low
frequency harmonics except for triplen harmonics, which may
present on the modulation signals to increase the fundamental
component without invoking over-modulation.
Under CCM an important operating constraint can be
recognized. If continuous sinusoidal PWM is used, the polarity
of the line currents and the polarity of the imposed line to
neutral voltage from the switching devices have to be identical.
In the past this has been referred to as the pulse polarity
consistency rule (PPCR) [8]. Thus on an averaged basis, the
line currents have to be in phase with corresponding pole to
neutral voltages. Otherwise, low frequency harmonic distortion
will occur in both line currents and pole voltages. This
requirement is equivalent to the unity power factor at the
rectifier poles (NOT at the source voltages). On the other hand,
under space vector modulation mode the input power factor
angle at the rectifier input terminals may lie between (-π/6, π/6)
[9]. Although this appears to be a drawback, realistic value of
input inductors lead to a power factor at the line terminals to be
greater than 0.98 for typical cases.
IV.
STATE SPACE AVERAGED MODEL
With CCM, the SPTT in each phase leg can be replaced by
the averaged model and the resulting equivalent circuit is
shown in Figure 5. In this model, the harmonics close to
switching frequency are neglected and the pole voltages only
contain the fundamental component and possible third
harmonics coming from the modulation signals. However, the
third harmonics do not have effect on the line currents for
three-wire configuration. So, in the subsequent analysis, only
the fundamental component of the pole voltages is considered.
 1
Vdc a
 
a
θ
M cos ( M θ − I Lθ )  

 Vs cos ( − I L ) −
L
2
 
 I La  

d  θ  1  a
V

I L  =  a  Vs sin ( − I Lθ ) − dc M a sin ( M θ − I Lθ )  − ωe 

dt
LI
2


Vdc   L 
  



1
3
2
V


I La M a cos ( M θ − I Lθ ) − dc 



C2
RL 
where ILa and ILθ are amplitude and phase angle input current
vector (also called dynamic phasor), respectively [10].
Similarly, Ma and Mθ are amplitude and phase angle of the
modulation index space vector, respectively. Here, the phase of
the three-phase ac source voltage is chosen as reference. This
dynamic model has been shown to be convenient for regulator
design based on phase angle coordinates.
Under steady state, the dynamic model (2) reduces to a set
of phasor relations visualized in Figure 6. Due to the operating
constraints imposed by particular switch realization, the line
currents are in phase with rectifier pole voltages. The phase
angle between the source voltages and pole voltages is
determined by the phase angle of modulation functions. It may
be noticed that if the pole voltage is modulated such that it
stays on the trajectory indicated by the dotted half circle, then
the line current is forced to be in phase with the pole voltage.
Furthermore, the phase angle between the source and pole
voltages determines the active power flow, as is classically
formulated in ac power systems theory. For balanced operation,
the power flow to the rectifier is given by
The state space model for the averaged system can be
described by state equation (1).
dx
= Ax + Bu
dt
where
x = [ia

 0


 0


A=  0

 ma1
C
 dc
 ma 2
C
 dc
ib
ic
0
0
−
ma1
La
0
0
−
mb1
Lb
0
0
m
− c1
Lc
mb1
Cdc
mc1
Cdc
−1
RLCdc
mb 2
Cdc
mc 2
Cdc
1
RLCdc
(1)
ma 2 
La 

m 
− b2 
Lb

mc 2 
−
Lc 

1 
RLCdc 

−1 
RLCdc 
,
vbn




B=





1
La
0
0
1
Lb
0
0
0
0
0
0
0 


0 

1 
Lc

0 

0 
van
-
La
+
a
vbn
n
+
+
ib
b
ma1vc1+ma2vc2
ic
c
+-
ma1ia+mb1ib+mc1ic
Cdc
mb1vc1+mb2vc2
B
Lc
(3)
2ωe L
A
Lb
vcn
-
ia
3VsaVdc M a sin ( M θ )
+-
Cdc
mc1vc1+mc2vc2
C
N
ma2ia+mb2ib+mc2ic
+
vc1
-
RL
vc2
+
+-
Van
,
Μθ
j*IaωL
Ia
VAN
vcn ] .
T
With assumptions of La = Lb = Lc = L, and vc1 = vc2 = Vdc/2,
transforming three phase abc quantities to synchronous
reference frame in polar coordinates results in
IAS 2005
P=−
Figure 5. State space average model of the Vienna rectifier.
−
T
vc1 vc 2 ] , u = [ van
(2)
1679
Figure 6. Phasor diagram of unity-power-factor constraint at the rectifier
input.
0-7803-9208-6/05/$20.00 © 2005 IEEE
Notice the maximum power transfer occurs when Mθ = π/4.
Pmax = −
3 (V
)
a 2
s
van
-
2ωe L
ma1ia+mb1ib+mc1ic
vbn
n
Lb
+
Lc
+
-
mc1vc1+mc2vc2
+-
mα
van vbn vcn
I LAωe
0
0
M 

−
2L  ,

0 

2 
−

RLC 
0 


A
l =  − Vdc M 
B
 2 I LA L 


0 

polar
Ma
a
rect. Vs
vβ
Cdc
ma2ia+mb2ib+mc2ic
vc1
RL
vc2
+
abc
mβ
rect.
Μθ+Vsθ
Vsθ
polar
+
-
Μθ
*
+
PI regulator
Vdc
Figure 7. Block diagram of the proposed controller.
40
Magnitude (dB)
20
0
20
40
60
80
100
3
1 .10
4
3
1 .10
4
1
10
100
1 .10
1
10
100
1 .10
180
Phase (degree)
(5)
90
0
90
180
i 
, x =  i  ,
 
 vdc 
 
+
cos
Vdc
To design the PI regulator, the transfer function between the
phase angle Mθ and Vdc is derived from the state space averaged
model formulated in dynamic phasors. The model described in
(2) is nonlinear with respect to the control input Mθ. By
linearizing the system at the nominal operating point, small
signal model is obtained.
A
vα
αβ
A new control algorithm is proposed based on the phase
angle control as shown in Figure 7. Only a voltage loop is used
to regulate the dc bus voltage. No current sensing/estimation is
needed in this algorithm. The error between the dc voltage
reference and the dc voltage feedback is processed by the PI
regulator. The output of the PI regulator becomes the phase
angle difference between the source voltage and pole voltage.
The phase angle difference is also used to calculate the
modulation index space vector. Typically, the phase angle of
the modulation index space vector is small. The amplitude of
the modulation index vector varies only by a small amount
during normal operation. So the power flow is controlled
mainly by the phase angle Mθ, although the proper amplitude
Ma is critical to ensure the unity power factor at the rectifier
poles to achieve good quality of the input current waveforms.
d x l l = Ax + Bu
dt
N
αβ
abc
Cdc
mb1vc1+mb2vc2
+-
vcn
The common practice of controlling the three phase boost
rectifier, either two level or three level topology, resorts to
multi-loop control [7, 11, 12]. Typically, the dc link voltage
reference is compared against the feedback voltage and the
error is fed to a PI regulator. The output of the PI regulator
becomes the current reference. The inner current loop uses a
proportional gain to calculate the required pole voltage
reference. Due to the bandwidth limitation of the inner current
loop, the controller is preferred to be implemented in the
synchronous reference frame, which is complicated.
Particularly to the Vienna Rectifier, the controller is even more
complicated due to switch realization. The space vector
modulation is often the choice to stay within the constraints.
IAS 2005
+-
PROPOSED CONTROLLER
V.
u = m Θ .
ma1vc1+ma2vc2
(4)
The maximum power point typically corresponds to unpractical
large input current, which would not be suitable for practical
applications.

 0
where

lA =  − ωe
A
 IL
3 M A

 2 C
La
+
A
L
Θ
L
Frequency (Hz)
Figure 8. Bode plot of loop gain transfer function with a PI regulator.
The small signal transfer function between mΘ and vdc may
be determined to be
G ( s) =
1680
vdc
= G0 ⋅
mΘ
1
s
s2
1 s
+ 2)
(1 + )(1 +
ωr
Qc ωc ωc
(6)
0-7803-9208-6/05/$20.00 © 2005 IEEE
(V) : t(s)
,
50.0
8ω 22 L
V_ab
0.0
−50.0
2
1
ωc
, and Go = − 3Vdc M A ⋅ R
2
ωr ωc
8ωe L
2 −1
ωr
−100.0
(A) : t(s)
4.0
50.0
(V)
It is interesting that the control transfer function of a three
phase boost derived Vienna rectifier features a third order
system with a real pole and a pair of complex poles under angle
control. This is in stark contrast to more classical control
approaches exhibiting a right half plane zero in their dynamics.
0.0
i_a
2.0
0.0
(V) : t(s)
V_AN
−2.0
−50.0
−4.0
0.25
A proportional and integral (PI) regulator is designed to
stabilize the system by shaping the loop gain transfer function
with adequate phase margin and gain margin. The compensated
loop gain transfer function is plotted in Figure 8. The loop gain
gives about 60 degrees phase margin and 10 dB gain margin.
The bandwidth of the closed loop system is about 20 Hz.
0.26
0.27
0.28
0.29
t(s)
Figure 9. Steady state simulation results of salient quantities with the
proposed control algorithm: top two traces are sinusoidal line-to-line source
voltage Vab and modulated pole-to-pole voltage VAB; bottom two traces are
sinusoidal line current ia and modulated pole-to-neutral voltage VAN.
(V) : t(s)
2.0
SIMULATION RESULTS
A detailed Saber model has been built to verify the control
algorithm. The salient parameters used in the small scale
simulation model are listed in TABLE I.
V_AN
50.0
(A)
VI.
V_AN
100.0
(V)
RC +
2
2
, ω = ω2 + 3 M A
c
e
4 LC
(A)
Qc =
ωr =
1
3M A2 R
0.0
(V)
where
(A) : t(s)
0.0
i_a
−50.0
SALIENT PARAMETERS USED IN SIMULATION
−2.0
2.0
35 Vrms
100 V
60 Hz
5 kHz
10 mH
0.2 Ω
180 µF
96 Ω
V_AN
50.0
0.0
(V)
Source voltages Van = Vbn = Vcn
Dc link voltage
Source Frequency
Switching frequency
Input inductances La = Lb = Lc
Input resistances Ra = Rb = Rc
DC capacitance Cdc
Nominal load resistance R
(A)
TABLE I.
(A) : t(s)
0.0
i_a
−50.0
−2.0
0.265
0.27
0.275
0.28
0.285
t(s)
The transient response of the pole-to-pole voltage vAB, input
current ia and dc bus voltage Vdc to a step-up and step-down
change of the output load is shown in Figure 11. a and
Figure 10. Simulation of line current ia and pole voltage VAN for case (a) the
magnitude of the modulation index is NOT controlled properly (upper panel)
and case (b) with proper control of modualtion index (lower panel).
V_AB
100.0
(V)
50.0
0.0
−50.0
−100.0
(A)
0.0
i_a
2.0
100.0
50.0
(A) : t(s)
4.0
150.0
(V)
Under steady state operation, sinusoidal line-to-line source
voltage Vab and modulated pole-to-pole voltage VAB are shown
in the top panel of Figure 9. It is observed that the pole voltage
at the rectifier slightly lags the source voltage. The small phase
angle difference between the source voltage and the pole
voltage results in appropriate power flow to regulate the dc bus
voltage. The sinusoidal line current ia and modulated pole-toneutral voltage VAN are exactly in phase as shown in the lower
panel of Figure 9. It is critical to satisfy the phasor relation
defined by the diagram in Figure 6. Otherwise, the reduced
switch realization of the converter results in low frequency
distortion. To illustrate this point, distorted line current and
pole voltage due to violation of the necessary phasor relation
are shown in the top panel of Figure 10. compared to the proper
line current and pole voltage shown in the lower panel of the
same figure. In addition, the dc link voltage has more ripple
voltage not shown in the figure.
0.0
(V) : t(s)
Vdc
−2.0
−4.0
0.24 0.26 0.28 0.3 0.32 0.34 0.36 0.38 0.4 0.42
t(s)
(a)
IAS 2005
1681
0-7803-9208-6/05/$20.00 © 2005 IEEE
v AB
50 V/div
V_AB
100.0
(V)
50.0
0.0
−50.0
−100.0
i_a
2.0
100.0
(A)
(V)
v ab
25 V/div
(A) : t(s)
4.0
150.0
50.0
0.0
0.0
v AN
25 V/div
(V) : t(s)
ia
1 A/div
Vdc
−2.0
−4.0
0.24 0.26 0.28 0.3 0.32 0.34 0.36 0.38 0.4 0.42
t(s)
(b)
5 ms/div
Figure 11. Simulation of the dyanmic response of the pole-to-pole voltage vAB
(upper panel), ac line current ia and dc bus voltage Vdc (lower panel) to a load
step change: (a) load step-up; (b) load step-down.
Figure 12. Steady state experimental results of salient quantities with the
proposed control algorithm: top two traces are sinusoidal line-to-line source
voltage Vab and modulated pole-to-pole voltage VAB; bottom two traces are
sinusoidal line current ia and modulated pole-to-neutral voltage VAN.
Figure 11. b, respectively. During the transients, both the poleto-pole voltage and the line current off-tune, but return to
normal waveforms after the dc link voltage transient dies out
and the rectifier settles to a new operating point.
Line current ia
0.5 A/div
VII. EXPERIMENTAL RESULTS
In order to verify the proposed controller and the
simulations, experiments have been conducted on a laboratory
scale prototype. The steady state measurements are recorded in
Figure 12. , which shows the line-to-line voltage vab and poleto-pole voltage vAB in the upper panel and line current ia and
pole-to-neutral voltage vAN in the lower panel. Similar to the
simulation results, leading phase angle of the source voltage
with respect to the pole voltage and in phase between the line
current and the pole voltage have been observed. In the
experiment, the identified operation constraints are deliberately
violated and the ac line current distortion is obvious as shown
in the upper panel of Figure 13. Even the pole-to-neutral
voltage is distorted due to the distorted zero-crossing of the line
current.
The transient response of the controller has been tested
against the step changes in load. The pole-to-pole voltage vAB,
input current ia and dc bus voltage Vdc to a step-up and stepdown change of the output load are shown in Figure 14. a and
Figure 14. b, respectively. During the transient, both the poleto-pole voltage and the line current are off-tune, but return to
normal waveforms after the dc link voltage transient dies out
and the rectifier settles to a new operating point. The strong
agreement between the experimental results and the simulation
results are readily evident from the figures.
VIII. CONCLUSIONS
This paper has presented design oriented analytical
solutions addressing the application of three level rectifiers,
with particular focus on the Vienna rectifier. The harmonic
loading on the dc bus capacitor due to circulating neutral
currents have been identified as an issue to be considered in si-
IAS 2005
Pole voltage v AN
25 V/div
Line current ia
0.5 A/div
Pole voltage vAN
25 V/div
2 ms/div
Figure 13. Experimental measurement of line current ia and pole voltage VAN
for case (a) the magnitude of the modulation index is NOT controlled properly
(upper panel) and case (b) with proper control of modualtion index (lower
panel).
zing the dc bus capacitor. The operating constraint introduced
by the reduced switch realization, namely unity power factor at
the rectifier poles, as opposed to source terminals, is identified
under typical carrier-based PWM mode control. Although the
phase angle difference between the source voltage and pole
voltage is small (less than a few degrees) for typical inductor
values, unity power factor at pole voltages is critical in
ensuring optimal ac line currents quality. For a particular
design, the phase angle difference may be so small that the
current distortion may not be obvious with unity power factor
at ac sources.
A new PWM control algorithm based on phase angle
control is proposed to ensure operating constraints of the
1682
0-7803-9208-6/05/$20.00 © 2005 IEEE
reduced switch realization are met. The system is modeled
using dynamic phasor and the controller is designed based on
that model. The proposed control algorithm is verified by Saber
simulation and laboratory experiment. The match between the
simulation and experimental results validates the modeling and
the controller design.
This new control algorithm is relatively simple compared to
inner-current-outer-voltage multi-loop controller. Constant
switching frequency provides better line current spectrum
compared to the hysteresis current controller. Furthermore, this
controller offers promising cost reduction opportunity by
eliminating the line current sensors.
v AB
50 V/div
ia
1 A/div
v dc
50 V/div
20 ms/div
(a)
vAB
5 0 V /d iv
ia
1 A /d iv
v dc
5 0 V /d iv
2 0 m s /d iv
(b)
ACKNOWLEDGMENT
The authors would like to acknowledge support from The
Boeing Company and the sponsors of the Wisconsin Electric
Machine and Power Electronics Consortium (WEMPEC) at the
University of Wisconsin-Madison. The work made use of ERC
shared facilities supported by the National Science Foundation
(NSF) under AWARD EEC-9731677.
REFERENCES
[1]
T. S. Key and J. S. Lai, "Comparison of standards and power supply
design options for limiting harmonic distortion in power systems,"
Industry Applications, IEEE Transactions on, vol. 29, pp. 688, 1993.
[2] A. Bendre and G. Venkataramanan, "Modeling and design of a neutral
point regulator for a three level diode clamped rectifier," in Conference
Record of the 2003 IEEE Industry Applications Conference (Cat.
No.03CH37459), Salt Lake City, UT, USA, 2003, pp. 1758.
[3] J. W. Kolar and U. Drofenik, "A new switching loss reduced
discontinuous PWM scheme for a unidirectional threephase/switch/level boost-type PWM (VIENNA) rectifier," in 21st
International Telecommunications Energy Conference. INTELEC '99
(Cat. No.99CH37007), Copenhagen, Denmark, 1999, pp. 10 pp.
[4] J. W. Kolar and F. C. Zach, "A novel three-phase utility interface
minimizing line current harmonics of high-power telecommunications
INTELEC.
Sixteenth
International
rectifier
modules,"
in
Telecommunications Energy Conference (Cat. No.94CH3469-4), 1994,
pp. 367.
[5] N. B. H. Youssef, F. Fnaiech, and K. Al-Haddad, "Small signal
modeling and control design of a three-phase AC/DC Vienna converter,"
in IECON'03. 29th Annual Conference of the IEEE Industrial
Electronics Society (IEEE Cat. No.03CH37468), Roanoke, VA, USA,
2003, pp. 656.
[6] U. Drofenik and J. W. Kolar, "Comparison of not synchronized sawtooth
carrier and synchronized triangular carrier phase current control for the
VIENNA rectifier I," in ISIE '99. Proceedings of the IEEE International
Symposium on Industrial Electronics (Cat. No.99TH8465), Bled,
Slovenia, 1999, pp. 13.
[7] B. Shi, G. Venkataramanan, and N. Sharma, "Design Considerations for
Reactive Elements and Control Parameters for Three Phase Boost
Rectifiers," in Proceedings of International Electric Machines and
Drives Conference, Antonio, Texas, 2005, pp. 1757-1764.
[8] J. Zubek, A. Abbondanti, and C. J. Norby, "Pulsewidth modulated
inverter motor drives with improved modulation," IEEE Transactions on
Industry Applications, vol. IA11, pp. 695, 1975.
[9] Y. Zhao, Y. Li, and T. A. Lipo, "Force commutated three level boost
type rectifier," IEEE Transactions on Industry Applications, vol. 31, pp.
155, 1995.
[10] G. Venkataramanan and B. Wang, "Dynamic modeling and control of
three phase pulse width modulated power converters using phasors," in
2004 IEEE 35th Annual Power Electronics Specialists Conference
(IEEE Cat. No.04CH37551), Aachen, Germany, 2004, pp. 2822.
[11] M. Malinowski, M. Jasinski, and M. P. Kazmierkowski, "Simple direct
power control of three-phase PWM rectifier using space-vector
modulation (DPC-SVM)," IEEE Transactions on Industrial Electronics,
vol. 51, pp. 447, 2004.
[12] P. Barrass and M. Cade, "PWM rectifier using indirect voltage sensing,"
IEE Proceedings: Electric Power Applications, vol. 146, pp. 539, 1999.
Figure 14. Exeprimental results of the dyanmic response of the pole-to-pole
voltage vAB (upper panel), ac line current ia and dc bus voltage Vdc (lower
panel) to a load step change: (a) load step-up; (b) load step-down.
IAS 2005
1683
0-7803-9208-6/05/$20.00 © 2005 IEEE