6 Key Considerations for Choosing the Right
Analog IP
By Bob Salem and Kevin Yee, Product Directors, Cadence Design Systems
Analog circuitry continues to play a critical role in today’s advanced systems on a chip (SoCs), especially given the rise
of mobile computing and the Internet of Things. Designing with analog designs comes with unique challenges (To
learn more, read our paper, 5 Key Challenges in designing with High-Speed Analog IP Design). One way to address
these challenges and meet time-to-market expectations is by integrating off-the-shelf analog intellectual property
(IP) blocks into the SoC design. This paper discusses six key considerations for choosing the right analog IP for nextgeneration mixed-signal designs.
Introduction
Contents
Introduction.................................. 1
Sampling Rate: How Much
Speed is Necessary?...................... 2
Resolution: a Look at Quality
of Signal Sampling........................ 2
Architecture.................................. 2
Process Node: Advantages
and Challenges at 28nm............... 3
Power Consumption and Die Size:
What’s Important in Analog.......... 3
More than 250 Silicon-Tested
Analog IP Blocks........................... 4
Footnotes..................................... 5
For Further Information................. 5
For next-generation designs, high-performance data converters and analog
front ends (AFEs) must support the latest radio and optical interfaces. At
advanced nodes, such analog IP blocks are challenging and time-consuming
to design. Faced with competitive pressures around time to market and cost,
many SoC designers are turning to analog IP providers with off-the-shelf
solutions. There are plenty of analog IP providers on the market—according
to Semico, demand for analog IP cores such as analog-to-digital converters
(ADCs) and digital-to-analog converters (DACs) is expected to increase at more
than 17% through 20151. With readily available analog IP, designers now have
the option to integrate such IP and thus minimize potential challenges that
can occur with doing analog design from scratch—such as synchronization,
noise, and, layout. However, not all analog IP is the same. Choosing the right
solutions can mitigate risks, speed up the design cycle, and guarantee design
performance goals.
How to choose the right building blocks? The life of a designer is always about
trade-offs. From signal sampling rates to power consumption, there are a
variety of criteria to consider when choosing the optimal analog IP for an
SoC—in other words, IP that will support stringent performance, power, and
other requirements. This paper examines six key selection criteria:
• Sampling rate
• Bit resolution
• Architecture
• Process node
• Power consumption
• Die size
6 Key Considerations for Choosing the Right Analog IP
Sampling Rate: How Much Speed is Necessary?
Signal speed is an obviously important criterion for data converters. For greater accuracy in rendering analog
signals, the data converter should support fast speeds in the sampling of incoming data. Following the guidance of
the Nyquist sampling theorem, the sampling rate should be higher than twice the highest frequency of the signal,
in order to generate an accurate reproduction of an analog signal in digital form. When evaluating analog IP, the
fastest signal that is targeted for sampling will determine how fast the sample rate must be. Under conventional
thinking, it would appear that faster is better. However, as we noted earlier, life is about trade-offs. So, more speed
also means higher power. The art is to strike a balance between just fast enough and just low enough power.
Data converters that support emerging high-speed communications protocols, such as WiGig (802.11ad), Long
Term Evolution (LTE), and LTE Advanced, require fast sampling rates. WiGig, for instance, runs on a 60GHz
spectrum, with a potential data throughput up to 7Gbps, or 2.16GHz bandwidth (a rate 10X higher than in
801.11n). As a result, the ADC needs to be 10X faster. Such capabilities would bring functions like wireless transmission of uncompressed video to reality.
Resolution: a Look at Quality of Signal Sampling
How fast do you need to sample (as discussed above) and how many bits you select will determine how accurately
you represent your analog signal. This is resolution. The higher your resolution, the more accurate you will be
to represent your original analog signal. In other words, the combination of your sample rate and bit width will
determine the quality of the signal. When designing an SoC for an audio application, strive for as large a number
of sample rates (bits) as possible, to allow higher sensitivity to noise. For typical sensor applications, a sample rate
of six to seven bits can be sufficient.
Effective number of bits (ENOB) provides a holistic measurement of analog-to-digital (A to D) performance. This
metric assesses what the quality of the A to D conversion will be like in a real application, accounting for factors
including noise, temperature, and signals. An ideal ENOB is one that is as high as the number of bits in the ADC.
Architecture
There are a variety of ADC architecture types, each with varying sample rates, resolution, and power efficiency.
The successive approximation register (SAR) architecture is the most popular ADC architecture today, as it is very
fast and, with the reuse of each slice of ADC, it is also quite scalable. A single SAR data converter can have sample
rates from 100KSPS to 500MSPS (along with high power efficiency and medium-level resolution at 6 to 12 bits).
A parallel SAR converter (as shown in Figure 1) can boast sample rates from 500MSPS to 40GSPS, though with a
medium-level power efficiency and resolution (6 to 12 bits). By comparison, the Flash ADC architecture provides
the highest sample rates—100MSPS to 40GSPS—but it also comes with the lowest power efficiency and resolution
(three to six bits). Another popular ADC architecture, the sigma delta architecture, features high resolution (10 to
24 bits) but low sampling rate, at 10 SPS to 50 MSPS.
www.cadence.com
2
6 Key Considerations for Choosing the Right Analog IP
Capacitor DAC
SAR ADC
Capacitor DAC
SAR ADC
Capacitor DAC
SAR ADC
Capacitor DAC
SAR ADC
Capacitor DAC
SAR ADC
.
.
.
Capacitor DAC
ADC
Interface
Digital
Logic
SAR ADC
Reference
Figure 1: Parallel SAR ADC Architecture Block Diagram
Process Node: Advantages and Challenges at 28nm
While most applications are currently based on the 65nm process node, advanced nodes such as 28nm and below
are worth considering for next-generation designs. At 28nm, there are many benefits that are ideal for mobile and
Internet of Things applications: faster transistor speeds, less leakage power, and smaller chip sizes, just to name
a few.
At smaller process nodes, however, design challenges do increase. Complex design rules impact IC architecture—
there’s more cross coupling and resistance in interconnects and through holes or vias at 28nm, for example. With
intra-cell dependence, there may be substantial timing slack and leakage power problems if the designer doesn’t
account for stress and lithography effect around the cell boundary. Other challenges include electromigration,
impact on parasitic resistance and capacitance from metal thickness variation, and sensitivity of smaller wires to
random defects and lithography distortion. 2
Typically, providers deliver their analog IP blocks as hard macros—which are very dependent on process technology
and hard to modify and test 3. To mitigate these challenges, choose analog IP from a provider who has demonstrated silicon-proven blocks at advanced nodes.
Power Consumption and Die Size: What’s Important in Analog
While die shrinks yield substantial power advantages in digital designs, the impact is less on the analog side.
With digital ICs, moving from one geometry to a smaller one results in equivalent savings in die size and power
consumption. But in analog ICs, the resistor doesn’t shrink along with geometry, so the size and power savings are
not as great.
The analog IP should be a consideration when developing the power management strategy for analog designs.
Early in the SoC design process, consider the analog building blocks that can manage power and temperature in
the device. Temperature sensors, for instance, can pinpoint areas of the circuit where temperatures run high—an
occurrence that can increase leakage currents and impact performance. Voltage regulators, especially when implemented on the die, can adjust supply voltage in areas of the system that do not require peak performance 4.
An important measure of power efficiency in an ADC is the Figure of Merit (FoM). Technical papers at conferences
often compete for the best FoM number, which can be calculated as:
FoM = Power/2ENOB * FSample rate
www.cadence.com
3
6 Key Considerations for Choosing the Right Analog IP
Exercise caution when evaluating ADCs based on FoM, as there are a number of ways to “optimize’ the FoM.
For example, one can exclude reference circuitry from power numbers, or the input buffer in the design. One
can include a large amount of calibration, including foreground calibration (which is generally undesirable from a
system standpoint), or increase the input voltage range of the ADC (which saves power but makes the ADC more
difficult to drive).
More than 250 Silicon-Tested Analog IP Blocks
Cadence offers a broad portfolio of more than 250 analog IP products that meet key requirements and can be
easily integrated into a wide range of SoC designs for markets including consumer, mobile, infrastructure, and
industrial. See Table 1 for an overview of the offerings and the process nodes they support. The products can be
grouped into these categories:
• AFE: AFEs, ADCs and DACs
• Timing: clocks, delays, and phase-locked loops
• Power: low-dropout regulators (LDOs) and linear regulators
• Monitor: temperature sensors
Bias
Current Array
Logic
Switch Array
Clock and Reg
Supply Cap
Figure 2: Layout Example: 14-Bit 650MSPS DAC
The newest products in this portfolio are silicon-proven, high-performance, low-power data converter IP for
28nm designs. These hard IP blocks provide up to 10X faster conversion rates (up to 3GSPS) with up to 50% less
power consumption and up to 40% smaller area compared to other IP solutions on the market. Based on a parallel
SAR architecture, the IP products support next-generation applications including WiGig. Developed with low
non-restrictive metal stacks and self-contained analog macro design, the cores can be easily integrated into SoCs.
The cores are also highly testable, featuring an analog test bus that provides access for characterization and testing.
The Cadence ® 28nm analog IP family consists of four solutions:
• 7-bit 3GSPS dual ADC and DAC
• 11-bit 1.5GSPS dual ADC
• 12-bit 2GSPS dual DAC
www.cadence.com
4
6 Key Considerations for Choosing the Right Analog IP
Table 1: Cadence’s Broad Analog IP Portfolio
65nm
Data
Converter
ADC
DAC
Sensor
Temperature
Voltage
Timing
PLL
DLL
Power
LDO
POR
AFE
Clock
40nm
28nm
FinFET
•
•
•
In Development
•
•
•
In Development
•
•
•
In Development
•
•
•
Footnotes
1.Allan Chin, “Understanding analog IP cores for embedded computing needs,” Embedded Computing Design,
Oct. 10, 2012, http://embedded-computing.com/articles/understanding-analog-cores-embedded-computingneeds/
2.Nora Chu, “28nm IC Design: The Devil is in the Details,” Digital Implementation (blog), Cadence Community,
March 14, 2011, http://www.cadence.com/Community/blogs/di/archive/2011/03/14/28-nm-ic-design-the-devilis-in-the-details.aspx
3.Chin, “Understanding analog IP cores for embedded computing needs,” Embedded Computing Design
4.Bal Sandhu, “Strategic Analog IP Power Management for SoCs,” SemiWiki, http://www.semiwiki.com/forum/
content/2879-strategic-analog-ip-power-management-socs.html, (Oct. 27, 2013).
For Further Information
To learn more about Cadence’s analog IP portfolio,
visit: http://www.cadence.com/ip/analog_ip/Pages/Default.aspx.
Cadence Design Systems enables global electronic design innovation and plays an essential role in the
creation of today’s electronics. Customers use Cadence software, hardware, IP, and expertise to design
and verify today’s mobile, cloud and connectivity applications. www.cadence.com www.cadence.com
© 2014 Cadence Design Systems, Inc. All rights reserved. Cadence and the Cadence logo are registered trademarks of Cadence Design Systems, Inc.
All others are properties of their respective holders. 1733 01/14 CY/DM/PDF