Astrium Satellites
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Document Nr : ADS.E.1031
Issue 1 Rev 0
Page 1 of 49
Belong to Process(es) :
D4 Design & Develop Products
Doc Type : Requirements
Replacement :
-
Comes into force : July 2010
ELECTRICAL DOUBLE INSULATION
Technical Requirements to Suppliers
The copyright in this document is the property of Astrium Satellites SAS/Ltd/GmbH and the contents may not be reproduced or revealed
to third parties without prior permission of that company in writing.
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Document Nr : ADS.E.1031
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CONTENTS
1
INTRODUCTION .......................................................................................................................... 3
1.1
1.2
2
RELATED DOCUMENTS............................................................................................................. 4
2.1
2.2
3
4
5
6
Applicable Documents ........................................................................................................................4
Reference Documents .........................................................................................................................4
DOCUMENT CHANGE DETAILS ................................................................................................ 5
DEFINITIONS AND ACRONYMS ................................................................................................ 5
APPLICATION PERIMETER OF THE DOUBLE INSULATION PROCESS ............................... 6
SUPPLIER TASKS FOR DOUBLE INSULATION ANALYSIS AND VALIDATION.................... 7
6.1
6.2
6.3
7
Scope.....................................................................................................................................................3
Applicability..........................................................................................................................................3
Equipments / Assemblies ...................................................................................................................7
Satellite or modules DC Harnesses level ........................................................................................12
Equipment Verification and Control Document..............................................................................14
DOUBLE INSULATION REQUIREMENTS................................................................................ 16
7.1
7.2
7.3
7.4
7.5
Definitions...........................................................................................................................................16
Generic requirements ........................................................................................................................16
Harnesses requirements ...................................................................................................................18
Equipments requirements.................................................................................................................20
PCB lay-out minimum proximities applicable requirements.........................................................22
7.5.1
7.6
7.7
7.8
8
PCB Screening tests requirements ..............................................................................................................24
Solar Arrays Double Insulation requirements ................................................................................25
Solar Array Drive Mechanisms Double Insulation requirements..................................................27
EGSE Double Insulation requirements ............................................................................................28
MATERIALS FOR USE IN DOUBLE INSULATION .................................................................. 29
ANNEX 1 – DI IMPLEMENTATION GUIDELINES........................................................................... 30
A1-1
A1-2
A1-3
A1-4
A1-4
A1-5
A1-6
A1-6.1
A1-6.2
A1-6.3
Harnesses DI Guidelines ...............................................................................................................31
Equipments DI Guidelines .............................................................................................................34
PCB Double Insulation rules .........................................................................................................39
Solar Array Double Insulation Guidelines ...................................................................................39
Solar Array Double Insulation Guidelines ...................................................................................40
SADM Double Insulation Guidelines ............................................................................................40
Materials Guidelines.......................................................................................................................41
Materials Selection Guidelines..................................................................................................41
Evolution of properties of materials and associated guidelines ...........................................42
Example of Materials Selection .................................................................................................43
A1-6.3.1 Rigid barrier materials ..................................................................................................................................45
A1-6.3.2 Non-Rigid barrier materials...........................................................................................................................46
ANNEX 2 – APPLICABILITY OF TECHNICAL REQUIREMENTS TO EOS ................................... 47
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Document Nr : ADS.E.1031
Issue 1 Rev 0
Page 3 of 49
INTRODUCTION
This document defines the mandatory technical requirements to be applied to equipments, subassemblies and harnesses suppliers to guarantee the robustness of the Astrium products against
potential critical insulation failures.
These requirements have been established with the expertise of the different BDs, electrical
specialists, the M&P specialists. A common understanding of the needed requirements has been
reached and is reflected in this document.
1.1
Scope
The document is intended to be almost directly exportable to the suppliers and is structured as
following :
•
DI applicable perimeter e.g. the critical cases for which it is necessary to ensure a double
insulation protection are defined
•
The tasks expected from suppliers :
–
–
–
to properly analyse, throughout the equipment, the potential insulation issues that
may require to define local double insulation implementation
to highlight/define how the double insulation protections will be implemented and to
include them in the manufacturing files
to verify that insulation protections have been properly applied and inspected in all
related areas at equipment / assembly or harness levels.
•
The mandatory technical requirements related to design and implementation of double
insulation protections, addressing in particular harnesses, electronics equipments /
assemblies, solar array and solar array drive mechanisms
•
A number of guidelines, e.g. known best practices to serve as implementation examples
but which are not mandatory
This document aims at a generic implementation, however some projects may elect to make it
applicable through their specific design and interfaces requirements.
1.2
Applicability
(FOR FURTHER DETAILS SEE PROPERTIES SHEET AT THE END OF THE DOCUMENT)
This document is applicable to all Astrium Satellites (or Astrium subsidiaries) internal or external
suppliers.
These requirements can be applied either through the equipment specification or through generic
design requirements documents or using this document.
In case of discrepancy or conflict with other applicable requirements, the Contractor shall bring the
point to the attention of the Prime for applicability clarification.
The copyright in this document is the property of Astrium Satellites SAS/Ltd/GmbH and the contents may not be reproduced or revealed
to third parties without prior permission of that company in writing.
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Document Nr : ADS.E.1031
Issue 1 Rev 0
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RELATED DOCUMENTS
2.1
Applicable Documents
REFERENCE
TITLE
AD.1
ECSS Q-ST-70C
Materials, Mechanical parts and Processes
AD.2
ECSS E-20-06
Spacecraft charging
AD.3
ADS-E-0723
Tin whiskers growth mitigation risks
AD.4
ADS-E-0592
MPCB Policy
2.2
Reference Documents
REFERENCE
TITLE
RD.1
ENS.06.00123.ASTR
EOS GDIR 1
RD.2
EUR3.SP.5060.MMT
E3000 DIET 1
RD.3
ABU.JPT.SP.00563
AlphaBus GDIE 1
RD.4
QTM.CDS.ND.06.18
Forbidden materials guideline for space applications
RD.5
QTM.NT.BJP.07.81
Techniques used in order to improve the liability of the shield
terminations
RD.6
ECSS-Q-30-02C Annex G
FMECA Analysis – Parts failure modes 1
RD.7
IPC 2221A
Generic standard on printed board design 1
RD.8
ECSS.Q.70.11
ECSS.Q.70.10
GAL.REQ.ASTD.SA.R.0005
Is. 2 Rev. 2
Procurement of Printed Circuit Boards 1
Qualification of Printed Circuit Boards
RD.9
Galileo space environment requirements
Note 1 : The requirements in this document will alter this RD document
The copyright in this document is the property of Astrium Satellites SAS/Ltd/GmbH and the contents may not be reproduced or revealed
to third parties without prior permission of that company in writing.
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Issue 1 Rev 0
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DOCUMENT CHANGE DETAILS
ISSUE DETAILS
ISSUE / REV
DATE
CHANGES – AFFECTED SECTIONS – SUPERSEDED DOCUMENT(S)
1/0
June 2010
First issue
4
DEFINITIONS AND ACRONYMS
AIT
AQI
BD
BOB
BOL
BU
CDR
CPS
DE
DI
DRB
DT
Assembly, Integration and Tests
Integration Quality Assurance
Subsystems, Equipments & Operations
Division
Business Division
Break-out-Box
Beginning Of Life
Business Unit
Critical Design Review
Combined Propulsion Subsystem
Test Request
Double Insulation
Delivery Review Board
Work Request
EGSE
Electrical Ground Support Equipment
RACI
EOS
Earth Observation and Science BD
RAMS
AS
EPS
EQSR
ESD
ESM
GEO
KIP
LDC
LEO
M&P
MIP
MLI
MPC
MRB
MRR
Electrical Power Subsystem
Equipment Qualification Status Review
ElectroStatic Discharge
Astrium Equipment Supply Manager
GEOstationnary orbit
Key Inspection Point
Lot Date Code
Low Earth Orbit
Materials and Processes engineer
Mandatory Inspection Point
Multi Layer Insulation (thermal blanket)
Major Project Components (BD EOS)
Material Review Board
Manufacturing Readiness Review
(equipment level)
MSC
NCR
Major Satellite Components (BD T)
Non Conformance Report
O/C
Open Circuit
ORM
PA
PCB
PF
PIU
PL
PLM
PPS
PR
PU
Manufacturing Rework Order (AIT)
Product Assurance engineer
Printed Circuit Board
PlatForm
Payload Interface Unit
Payload
PayLoad Module
Plasmic Propulsion Subsystem
Phase Review
Product User (Astrium unit specialist)
Responsible, Approve, Contribute,
Information
Reliability, Availability, Maintainability,
Safety
Solar Array Drive Mechanism
SpaceCraft
Service Module (Platform)
Surface Mounted Component
Statement Of Work
Single Point Failure
Astrium unit Supply Quality Manager
Telecommunications BD
Thales Alenia Space
To Be Confirmed
To Be Determined
Telecommand / Telemetry
UlraViolet
SADM
SC
SM
SMC
SOW
SPF
SQM
T
TAS
TBC
TBD
TC / TM
UV
VCD
Verification Control Document
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to third parties without prior permission of that company in writing.
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APPLICATION PERIMETER OF THE DOUBLE INSULATION PROCESS
The requirements are defined to prevent single insulation failures that may generate or propagate
anomalies with critical consequences at mission level. Many possibilities of insulation failure
(design, manufacturing lay-out, workmanship) are not addressed in the FMECA analysis and as
such require a dedicated analysis.
Double insulation protection requirements are identified in the following pages of this document and
numbered as :
•
[REQ-SOW xx] for outlining tasks to perform in order to properly identify the potential
risks, to devise mitigations and to verify implementation of these mitigations or verify build
conformance
•
[REQ-TEC xx] for the technical requirements (design and/or implementation)
It is mandatory, as a starting point, for each supplier, to identify accurately within their equipments
and EGSEs, where are the specific areas of concern related to the perimeter cases highlighted
below.
[REQ-TEC 1] All the cases described in this chapter shall be mandatorily mitigated by double
insulation protection or by a conforming appropriate design. The applicable perimeter
covers any part of circuit where a loss of insulation can generate major degradation of
mission :
Î Power lines : all equipments generating electrical power, conductors, harnesses
(including dismountability sections) and distribution areas upstream of protections and
inclusive of these protections
Î Cross-Strapped functions and associated common links from source to
Double insulation shall be applied whenever an internal or external electrical
cross-strapping is common to prime and redundant functions, generating the
possible loss of both functions together (hot redundant power links, majority
"reliable" links, specific telecommand or telemetry matrices)
load :
link or
risk of
voters
Î Areas when loss of insulation would result in electrical failure propagation :
overvoltage, arcing and all its consequences, power applied to interfaces, primary to
secondary, specific telecommand or telemetry matrices (connected equipments internal
failure leads to command or telemetry inoperability for other fully functioning units),..
Î Areas where nominal insulation can be damaged by mission environment : for
example radiations, thermo-elastic constraints, chemical products, vibrations,..
Î Areas where loss of nominal insulation would result in electrical shock or safety
hazard for human operator
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to third parties without prior permission of that company in writing.
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6.1
Document Nr : ADS.E.1031
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SUPPLIER TASKS FOR DOUBLE INSULATION ANALYSIS AND VALIDATION
Equipments / Assemblies
Equipment / Assembly level (platform, payload & instrument) :
At the early stage of programme (Equipment RFP or supplier Kick-Off latest) :
[REQ-SOW 1] The equipment supplier is required to prepare a technical note that will
be kept up-to-date until equipment closure MIP or before TRR. This document shall
analyse exhaustively the equipment compliance and shall present the solutions retained
to comply to the double insulation requirements. This document shall be prepared
according to the following guidelines :
1. Identification of links (or equipotential) to be double insulated
-
All the interfaces and links requiring a double insulation at equipment level shall be
clearly identified and listed. This concern the following elements :
a)
Power conductors up to, and including the power bus protection
ƒ
ƒ
b)
All cross-strapped functions from source to load : whenever an internal or external
electrical link or cross-strapping is common to prime and redundant functions,
generating the risk of possible loss of both functions together (e.g. external secondary
supplies, control and monitoring signals to/from secondary units, etc..)
ƒ
ƒ
c)
In the case when a reliable signal (e;g. a single signal with no redundancy inside an
internally redundant unit) is formed by combination or voting of several signals, DI shall
be implemented in order to keep the reliable signal performance on any single insulation
loss
Matrix Telecommands and matrix Telemetry
ƒ
e)
The supplier shall identify the equipment internally cross-strapped signals
The externally cross-strapped signals will be defined in the equipment specification by the
Prime
Any element where insulation loss would result in mission loss or degradation (e.g.
majority voting)
ƒ
d)
If the primary power bus protection is inside the unit, DI requirements are applicable from
power bus connector down to and including the protection itself
If the primary power bus protection is external to the unit, DI is not required on unit power
circuits except where point (b) below is concerned
Matrix TCs (HLCD, HLCP, VHLC, HPC, DTC) and matrix TMs (TMBLD, DTM) are by
nature cross-linked between prime and redundant drivers / circuits and are therefore
subjected to DI requirements
Any element where insulation loss would result in electrical failure propagation
Even in the case when power bus protection is outside the equipment, DI is required at
locations of power circuits where a loss of insulation could propagate failures to
equipment redundant functions or to equipment external interfaces
ƒ If insulation loss, at a given place, can lead to failure propagation to equipment redundant
functions or to its external interfaces, DI shall be implemented in this place
Failure propagation stands for any kind of propagation, electrical (voltage, current), thermal,
part blast, arcing, etc, where deratings can be exceeded
ƒ
f)
g)
Any element where nominal insulation might be damaged by radiations, thermo-elastic
stresses, chemical product contamination, vibrations
Any element where loss of insulation would result in safety hazard for human operator
-
For each identified interface and link, the double insulation shall then be verified from
end to end, including connector, wires, PCBs, tracks, components, etc…
-
To give a clear overview, the areas to be double insulated shall be identified on
circuit board diagrams and with photos.
-
All grounding paths shall be identified
-
The test connectors and their functions shall be reviewed and double insulation needs
shall be addressed
The copyright in this document is the property of Astrium Satellites SAS/Ltd/GmbH and the contents may not be reproduced or revealed
to third parties without prior permission of that company in writing.
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2. Connectors
-
The pin allocation of each connector embedding a signal to be double insulated shall
be given for information, especially if MDM connectors are used (due to the short
distance between adjacent contacts)
-
The double insulation at connector rear level (inside the equipment) shall be
described (eg if pins are soldered on PCB: non conductive coating loaded with filler
material on pins from connector to PCB or sleeves covering all conductive areas of
contact).
-
Photos of the connectors rear (in flight configuration ie potted for example) are
recommended.
3. PCB
-
It shall be indicated the minimum distances between :
ƒ adjacent tracks of the same layers or of different layers
ƒ tracks and a connection
ƒ adjacent connections
ƒ tracks or connections and any other metallic part (cover, screw, etc)
-
The PCB design rules shall be explained and compared with the applicable PCB
requirements defined in § 7.5 of this document
-
The insulation tests performed at PCB level for qualification or for acceptance
screening shall be detailed : e.g. defining voltage, duration, the exhaustiveness and
combinatory of all the equipotentials tested wrt the others.
4. Coating
-
The type(s), typical thickness(es), and minimum thickness(es) of coating(s) used on
PCB and on components shall be indicated as the coating ensures the insulation in
case of internal particulate contamination.
-
It shall also be mentioned if the coating is loaded with filler material or not.
-
If any, PCB areas (front or back) or components which are left uncoated shall be
identified and it shall be verified that these locations do not require double insulation
(pictures recommended).
5. Internal wires or harness
-
It shall be explained how the internal wires that require a double insulation are
protected with regard to any other element at a differential voltage (ie components
cases, mechanical parts like screws or equipment chassis…). Pictures are
recommended.
6. Components to be double insulated
-
The double insulation at component level (diodes, transistors, relays, transformers,
capacitors, resistors, etc …) shall be detailed with adequate schematics and/or
pictures detailing the different insulation layers.
-
If diodes and transistors with metallic case are used, it shall be indicated whether the
case is insulated wrt internal chipset or not.
-
The type and thickness of insulated bushes (for screws) shall be given.
-
The type and thickness of the insulation layer between the component and its support
(metallic frame or PCB) shall also be indicated.
-
The insulation at components leads level shall also be verified, particularly for through
hole leaded components.
-
The minimum distances between the components (or their leads) and the other
elements at a different potential (mechanical elements, other components, PCB
tracks) shall be assessed.
-
The double insulation wrt these elements is generally ensured by the coating applied
at PCB level. The process used to keep a constant distance between components
and leads and adjacent tracks shall also be explained (wedge used at component
installation for example).
The copyright in this document is the property of Astrium Satellites SAS/Ltd/GmbH and the contents may not be reproduced or revealed
to third parties without prior permission of that company in writing.
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7. Equipment chassis and internal covers
-
If the equipment chassis and internal covers (if any) benefit from an insulating surface
treatment (anodisation for example) or from a specific additional protection (local
application of kapton tape for example), this information shall be indicated as far as
this participates to the double insulation at equipment level.
8. Processes
-
The double insulation justification note shall also provide details on the processes
(manufacturing and storage processes) that allow to ensure that no contamination /
pollution of boards is possible before or during the application of coatings.
-
Note that many control points evidence difficulties of inspection but shall nevertheless
be addressed :
ƒ Varnish thickness control and adherence, especially on sharp edges or
ƒ
ƒ
ƒ
components through hole leads
Pollution control inside connectors
Sealing
Air bubbles inside non transparent pottings
9. KIP/MIP inspection criteria
-
The aim of this technical note is primarily to give guidance on the method by which
justification of the compliance of the design to double insulation requirements is
made. However, the verification methods (inspection, tests, specific tooling, etc..) put
in place by the supplier at board and equipment levels, and corresponding
acceptance criteria shall also be identified. The customization of the inspection
template (refer to § 6.3) will contribute to meet this requirement.
-
KIP/MIP inspection criteria shall be identified (ex : no air bubbles in the coating
between 2 adjacent leads or pins, no particle, etc…).
10. Non Compliance identification
-
All Non Conformance to the double insulation rules and requirements shall be clearly
identified and listed
-
The corresponding RFD/RFW shall be submitted to prime for approval.
-
If double insulation implementation leads to get floating metallic parts (eg no bleeding
possible), the exhaustive list of floating metallic parts shall be identified in the
technical note to evaluate the risks linked to deep charging effect.
The copyright in this document is the property of Astrium Satellites SAS/Ltd/GmbH and the contents may not be reproduced or revealed
to third parties without prior permission of that company in writing.
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For equipment design reviews (PDR/CDR) preparation or MRR 1 at the latest :
ƒ
ƒ
To update the technical note (ref. REQ-SOW 1) with design justification reports and
compliance status that presents :
− The double insulation protection design solutions
− The exhaustive analysis of the equipment compliance to the double insulation
requirements. To ensure that equipment design drawings indicate the areas
where double insulation is needed
− The details of the double insulation protection manufacturing implementation as
specified
[REQ-SOW 2] The dedicated inspection and control checklists, related to the
verification (KIP/MIP) of the double insulation protection implementation along the
manufacturing, shall be available (defined or correctly updated) with agreed
acceptance criteria and timing (before they cannot be seen any longer or before box
closure).
It shall include specific manufacturing inspection (KIP) for the items that cannot be
guaranteed by design or manufacturing process like :
a) flexible cover
b) uncontrolled application of potting. It is mandatory to be able to control
and guarantee a minimum thickness of varnish or potting in areas like
sharp metallic edges or at the lead end of components at the back of
PCBs. This can be ensured for example by use of loaded varnish.
c) risk of pinched wire
d) ill-defined wire runs
e) bubbles in potting inspection (bubbles especially forbidden in areas
where voltage >12 V and current source capability > 3A)
f) wire in contact with metallic piece and risk of wear out
g) etc,….
This "double insulation report" shall be the technical note (stand alone document) as
defined per [REQ-SOW 1] and shall be submitted to Astrium for approval. However,
for the on-going programmes at the time of release of the first issue of this document,
the technical note could be a dedicated section of the equipment design report.
Note 1 : when there is no design review for a recurring equipment for example or to update the double insulation
document with inspection and control details that cannot be defined properly without a manufacturing file at the time of
CDR.
The copyright in this document is the property of Astrium Satellites SAS/Ltd/GmbH and the contents may not be reproduced or revealed
to third parties without prior permission of that company in writing.
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Verification during equipment manufacturing and assembly :
As Astrium quality inspectors cannot be physically and permanently present during the
equipment manufacturing, delegation may be given to the supplier for inspections and
controls of the implementation of the double insulation protections.
ƒ
[REQ-SOW 3] Therefore, all potential critical areas shall be properly controlled
during manufacturing by :
− inspections (KIP/MIP all along manufacturing flow), in line with previously
defined and approved checklists. Specific tests may be required by some final
customers.
− Pictures shall be taken and transmitted immediately for Astrium approval.
ƒ
[REQ-SOW 4] In case of modification, made on the equipment, impacting areas
where double insulation is applied, the double insulation report (including
compliance, impact on manufacturing implementation and relevant checklists) shall
be updated accordingly. The embodied changes shall be controlled at MRR or by
NRB if occurring during manufacturing.
ƒ
[REQ-SOW 5] Need of improving / updating checklists with unexpected or missing
topics (Lessons Learned) has to be transmitted immediately for Astrium approval.
•
[REQ-SOW 6] For recurring equipments, the same verification plan during the
manufacturing phase is mandatory to ensure that no process or workmanship quality
drift occurs.
To verify that the applicable process and requirements are exhaustively applied, a
Verification and Control (VCD) process aiming at generating systematically a justification
document within the MIP to provide evidence to Astrium that double insulation protection
has been correctly implemented and inspected (see VCD requirements and template in
chapter 6.3) all along the equipment manufacturing phase from manufacturing release
until MIP before closure or before TRR.
The VCD document shall be completed at MIP by the Astrium quality inspector with the
filled inspection and MIP checklists.
.
The copyright in this document is the property of Astrium Satellites SAS/Ltd/GmbH and the contents may not be reproduced or revealed
to third parties without prior permission of that company in writing.
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Satellite or modules DC Harnesses level
At the early stage of programme (Harness RFP or supplier Kick-Off latest) :
ƒ
ƒ
ƒ
The harness supplier shall verify that the technical specifications address properly
and completely the double insulation protection requirements. The electrical links
where the double insulation is needed shall be clearly indicated.
For all links subject to a requested DI, the supplier shall take into account any plug in
the circuit
The double insulation protection requirements are defined according to §7 in this
document
For Harness design review (PDR/CDR) preparation or MRR 1 at the latest :
ƒ
[REQ-SOW 7] Harness design analysis shall include identification of critical areas
for double insulation protection. Harness design drawings shall indicate the areas
where double insulation is needed
ƒ
[REQ-SOW 8] Supplier shall provide a document (refer to REQ-SOW 1) that
presents the solutions retained to comply and that demonstrate the compliance to
the double insulation protection requirements. This "double insulation report"
document shall contain :
–
–
–
the manufacturing files or the accurate extracts of the lay-out routing drawings
showing exact locations of areas to be double insulated (power lines, Matrix TC lines,
Cross-strapping lines,…).
all the details of the double insulation implementations (procedure, materials, physical
characteristics and qualification)
the detailed inspection and control checklists defined (or correctly updated) with
acceptance criteria and timing related to verification (KIP/MIP) of the double
insulation protection implementation along the manufacturing
This report can be either a technical note (separate document) or a dedicated
section of the harness design report. This "double insulation report" document
shall be submitted to Astrium approval.
During harness design review (PDR/CDR) or at MRR 1 at the latest :
ƒ
[REQ-SOW 9] To detail inspection checklists (with defined and agreed acceptance
criteria and timing) related to the verification of double insulation protection
implementation. Checklists shall address in particular specific manufacturing topics
for the items that cannot be guaranteed by design or manufacturing process like :
a) flexible cover
b) uncontrolled application of potting. It is mandatory to be able to control and
guarantee a minimum thickness of varnish or potting in areas like sharp
metallic edges, this can be achieved for example by use of loaded varnish.
c) risk of pinched wire
d) ill-defined wire runs
e) bubbles in potting inspection (bubbles especially forbidden in areas where
voltage >12 V and current source capability > 3A)
f) harness plugs
g) wire in contact with metallic piece and risk of wear out
h) etc,….
Note 1 : when there is no design review for a recurring equipment for example or to update the double insulation
document with inspection and control details that cannot be defined properly at the time of CDR.
The copyright in this document is the property of Astrium Satellites SAS/Ltd/GmbH and the contents may not be reproduced or revealed
to third parties without prior permission of that company in writing.
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During harness builds :
As Astrium quality inspectors cannot be physically and permanently present during the
equipment manufacturing, delegation may be given to the supplier for inspections and
controls of the implementation of the double insulation protections.
ƒ
[REQ-SOW 10] Therefore, all potential critical areas shall be properly controlled
during manufacturing by :
− inspections (KIP/MIP all along manufacturing flow), in line with previously
defined and approved checklists. Specific tests may be required by some final
customers.
− Pictures shall be taken and transmitted immediately for Astrium approval.
ƒ
[REQ-SOW 11] In case of modification, made on the harness, impacting areas
where double insulation is applied, the double insulation report (including
compliance, impact on manufacturing implementation and relevant checklists) shall
be updated accordingly. The embodied changes shall be controlled at MRR or by
NRB if occurring during manufacturing.
ƒ
[REQ-SOW 12] Need of improving / updating checklists with unexpected or missing
topics (Lessons Learned) has to be transmitted immediately for Astrium approval.
For recurring harnesses, the same verification process during the manufacturing phase
is mandatory to ensure that no process or workmanship quality drift occurs.
At Harness MIP before delivery :
•
[REQ-SOW 13] To verify that the applicable process and requirements are
exhaustively applied by the harness supplier, a VCD process aiming at generating
systematically a justification document within the MIP to provide evidence to Astrium
that double insulation protection has been correctly implemented and inspected (see
VCD requirements and template in chapter 6.3) all along the harness manufacturing
phase from manufacturing release until final MIP before delivery.
The VCD document will be completed at MIP by the Astrium quality inspector with
the filled inspections and MIP checklists.
At Harness Installation on Spacecraft structure panels :
•
[REQ-SOW 14] If this operation is performed by the harness supplier, either on
stand alone panels or on the spacrecraft structure (partial or complete), it is required
that the supplier maintains the verification process and evidence of DI
implementation shall be given at the end of this phase.
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6.3
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Equipment Verification and Control Document
[REQ-SOW 15] As the equipment design and manufacturing processes progress, the equipment
supplier has to provide information and shall record and give evidence with photos that the
proper double insulation protections have been implemented as necessary and at the appropriate
stage.
These informations shall form the inputs for the final update of the design technical justification note
and for the Verification and Control Document (VCD). The inspection template embedded below can
be used as a starting point and shall be customized for the equipment to get a clear, exhaustive and
agreed list of the inspections to be completed.
Unit double insulation
inspection.xls
The frame of the VCD as a core document is a table consisting in 6 columns as following :
°
First column (col1): Chapters and paragraphs of the full descriptive part of all the double
insulation design locations of the equipment according to requirements (organised along the
chapters of the equipment DI technical justification note (ref. REQ-SOW 1)
°
Second column (col2): Conformity of each double insulation design point (C if fully conforming
to DI requirements as defined in this document / NC if not). If NC, RFD reference shall be given.
°
Third column (col3): Manufacturing document reference. This is the place where a double
insulation design is properly implemented in the Industrial File.
°
Forth column (col4): Equipment supplier control. This is the place where the manufacturing of
the double insulation design is inspected and quality control checked, with evidence collected for
later proofing.
°
Fifth column (col5): Astrium Verification. This is the place where either a second inspection (as
the one operated by the Equipment supplier if feasible) can be operated by the Astrium QTM
during the MIP before closure of the equipment, or the check issued from the Astrium MIP check
list is performed.
°
Sixth column (col6): Astrium Agreement. This is the place where endorsement of the VCD is
recorded by the Astrium QTM.
Column content management is made according to the development progress of the equipment :
- the justification of the double insulation design of the equipment (col1) with the compliance (col2)
are reviewed in the frame of design reviews
- the manufacturing file implementation and the proposed inspection checklists are prepared in col3
and reviewed before the equipment MRR. The two last columns are not filled at that time.
- update of the description document (technical note) is made according to the manufacturing file
informations that would not be in line with the design description
- after the equipment MRR, col4 is filled by the Equipment supplier as appropriate along the
manufacturing process when a required control point has been completed.
- at MIP before equipment closure or at final MIP depending on equipment inspection programme,
the VCD is then endorsed by Astrium with the equipment supplier support and filling of col5 and
col6 is fully under the Astrium QTM at this stage.
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VCD structure :
(example shown below)
at MRR
During Build
MIP before closure or
Final MIP
Manufacturing file
(DI…)
Control/ inspection and any
intermediary KIPs or MIPs
MIP Checklist
(Astrium *)
Design phase until equipment CDR
TN ref. with its various chapters,
to be updated after :
- completion of manufacturing
file
- hardware modification during
build
Ch 1.
Ch 2.
§ 2.1
§ 2.2
Ch 3.
….
….
….
Compliance
(wrt DI
requirements)
C
NC + RFD
C
C
C
Ref & Issue + chapter
Ref & Issue + chapter
Ref & Issue + chapter
Ref & Issue + chapter
Ref & Issue + chapter
…
…
KIP ref + photo file
KIP ref + photo file
KIP ref + photo file
KIP ref + photo file
KIP ref + photo file
Astrium MIP check list
KIP ref . (repetition)
N/A
N/A
Astrium MIP check list
* Note : During Final MIP, the Astrium quality inspector (QTM) shall :
− review the status of KIPs held during build and check the pieces of evidences collected at that time
− approve the KIP status
− follow his own checklist and finally give his agreement on the equipment double insulation status and compliance
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Filename : ADS 1031 Double Insulation_Technical requirements_final_Iss1.doc
Astrium Agreement
at Final MIP
OK
OK
N/A
OK
NOK --> NRB
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DOUBLE INSULATION REQUIREMENTS
Double insulation will prevent short circuits leading to major failure on ground or in-orbit.
7.1
Definitions
•
Gap or void : no material between two conductive elements. A gap of 1 mm or above may
account for one barrier (and only one) if gap is not subject to variations (see §7.2).
•
Invariable gap : when the physical distance between two electrically conductive elements is not
subject to variations or changes, whatever the constraints (mechanical or thermal) applied to the
equipment or part of the equipment during its lifetime (manufacturing, AIT operations, tests and
in-flight operations, time).
•
Insulating material : it shall maintain its characteristics and be resistant whatever the constraints
undergone during lifetime (manufacturing, AIT operations, environmental tests, launch and inorbit operations)
F A measure can be given in terms of dielectric strength (V/m)
•
Rigid insulating material : strong, resistant, non porous, piercing resistant
F A measure can be given in terms of mechanical hardness (HV)
•
Non rigid insulating material : flexible, thinness (kapton, chotherm, glue, varnish,..) but has the
insulating material characteristics as defined above
•
Variable gap : when the physical distance between two electrically conductive elements can be
subject to variations or changes, according to constraints applied to the equipment or part of the
equipment (manufacturing, environmental tests, AIT operations, changes with time,…)
•
Voltage : the potential difference between the conductor elements under consideration
7.2
Generic requirements
[REQ-TEC 2] The double insulation shall be implemented by means of two different insulating
barriers as detailed hereafter in [REQ-TEC 2a and 2b].
[REQ-TEC 2a] The first barrier shall be mandatorily an insulating material enveloping or
covering all the concerned conductive pieces, so that not any area of bare conductor is left
exposed.
No part of the interface or circuit or conductor to be double insulated shall be left bare e.g.
without coating or not fully covered by insulating material. Specific focus is to be given to sharp
edges like component lead ends to prevent tip effects which reinforce the surrounding electrical
field.
[REQ-TEC 2b] The second barrier shall be another one as defined below in REQ-TEC 3.
For PCBs, the requirements (REQ-TEC 2 and 3) are not directly applicable, but specific
requirements are defined in § 7.5
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[REQ-TEC 3] In order to achieve the double insulation, one or two insulating materials are required,
as shown below.
DOUBLE INSULATION RULES between ZONE A and ZONE B
2 DIFFERENT CASES
ZONE A
RIGID OR NON RIGID BARRIER
ZONE A
d
d > 1 mm
AND
d < 1 mm
OR
d invariable
d variable
RIGID BARRIER
d
RIGID OR NON RIGID BARRIER
ZONE B
ZONE B
Rigid and non-rigid barriers materials are defined in § A1-6 of Annex 1.
Gap type
Gap distance (d)
Minimum Insulation rule
d ≥ 1 mm (40 mil)
Apply one insulating
material (rigid 3 or not)
d < 1 mm
Apply two insulating
materials, one of them
being rigid 3
Invariable 1
Variable 1, 2
N/A
(40 mil)
Apply two insulating
materials, one of them
being rigid 3
Notes :
1. It is mandatory that no foreign particle can be found or be inserted even accidentally or by pollution
during ground operations. This may result either in the insulating gap jeopardy or in possible damage
of a non rigid insulation. If risk of pollution during in-orbit life of product cannot be avoided, two
insulating materials shall be applied.
2. Only in the case of internal modules for which variability is present only because of the dynamic
displacements during environmental tests and if worst case minimum gap d is > 1 mm as
demonstrated by analysis, the invariable case can be applied.
3. Rigid or Non-Rigid barrier materials are defined in § A1-6.3 of Annex 1.
4. For material selection and dielectric strength margin calculations, the system operational maximum
voltage shall be taken into account, for example, series regulator solar array section inputs may get up
to 2 times nominal voltage at eclipse exit depending on solar cell temperature at eclipse exit
The next paragraphs detail the specific DI requirements to be applied to the following items :
– Harnesses
– Equipments or assemblies
– PCBs
– Solar Array equipment
– Solar Array Drive Mechanisms equipment
In addition, Annex 1 illustrates how the generic requirements could be implemented according to
current designs and manufacturing practices
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7.3
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Harnesses requirements
[REQ-TEC 4] The pieces of S/C harnesses or equipment internal harness for which a loss of
insulation has been identified as critical, shall be additionally insulated while keeping compliance
with the thermal requirements, this includes the CPS harness as well.
Shielded harness case :
•
[REQ-TEC 5] The use of screened or shielded cable types, in areas where double
insulation is required, shall be identified and submitted to Prime for approval, unless the
cable is :
Ö tailor-made and incorporate a dedicated additionnal compliant insulating sheath
between the wire(s) and the screen/shield
or
Ö is listed in Annex 1 (authorized cables)
•
[REQ-TEC 6] In case bundle (or wire) comes into contact with a sharp edge (equipment,
a bracket) or anything connected to the structure, or a MLI, this bundle (or wire) part shall
be adequately protected and DI shall be maintained.
External harness double insulations :
Whatever, a wire build, e.g. number of insulating layers constituting the wire enveloppe, it shall be
considered as a single barrier.
The wires insulators are considered to constitute a double insulation between adjacent wires (first
wire insulator is one barrier, second wire insulator is the second barrier).
•
[REQ-TEC 7] Arcing and arc tracking potential areas :
Distribution lines, even after power protections, but running outside the spacecraft main
body shall be considered as an exception wrt defined perimeter (due to higher risks of
arcing) and double insulation is required if :
– these pieces of distribution harnesses can supply and sustain permanent energy
with Imax > 0.5 A, that is sufficient to maintain arc tracking if a short-circuit exists
between neighbouring wires at different potentials
and
– failure propagation might be critical.
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Connectors mating area :
•
[REQ-TEC 8] Some connectors leave bare contacts in view of each other within the
mating area due to manufacturing tolerances. For those connectors carrying different
potentials and where ESD arc can be generated between two contacts due to a wire
being charged at a high potential, it might be necessary to install an interfacial
compressible seal to remove all conductor exposed surfaces. These cases shall be
brought to the attention of Prime for approval.
Connector backside level :
•
•
[REQ-TEC 2a] No exposed bare conductor is allowed.
[REQ-TEC 9] In all cases, it shall be ensured that insulating material will not retract nor
move such to avoid that bare conductor become visible during thermal cycling.
•
[REQ-TEC 10] Miniature connectors (MDM for example) and their contacts shall be
procured according to ESA SCC 3401/029 specification and with interfacial seal.
Because gap between adjacent contacts is < 1 mm, they are considered compliant with
double insulation rules when :
–
Case 1 : voltage between adjacent pins or between pin and connector body is
≤ 50V
Ö MDM connector has backside potting after contacts installation.
–
Case 2 : voltage between adjacent contacts or between contact and
connector body is > 50V
Ö MDM connector has one spare pin between considered contacts and
backside is potted after contacts installation. Each spare contact shall be
referenced to ground via one dedicated resistor (90 kOhm – 1.1 Mohm).
MDM connectors procured with another specification (MIL) are not compliant to
double insulation because after mating, a part of the contacts are left without
insulation.
Busbars insulation :
•
[REQ-TEC 11] The Busbars shall be all double insulated by design.
Telecom busbars are shown in A1-1 of Annex 1 as examples.
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Equipments requirements
•
•
[REQ-TEC 12] The double insulation protection is applicable end to end, for all
connector types, terminals, solder joints, crimp contact, wire wrap contact, PCBs,
tracks and components, etc..
[REQ-TEC 13] The rules defined on harness and connectors (§ 7.3) are fully applicable
as a minimum to the connectors and internal harnesses of the equipments or of any
complete assembly in their critical areas.
•
[REQ-TEC 14] No part, even the smallest one, of a design submitted to double
insulation requirement, shall be left without the required insulation, in particular it
is not allowed to leave bare conductor.
•
[REQ-TEC 15] Within the critical path, any short-circuit to component metallic case or
between some leads shall be considered a credible failure (ex. relay chassis, transistor
radiator).
For example :
– Relays carrying unprotected power must be double insulated at relay mounting
interface and one insulation shall be able to withstand a high dissipation
generated by an internal arc. The relay internal insulation is not allowed as a valid
barrier due to potential internal arcing at switch-on or off, unless dedicated reliable
transient suppression snubbers are used
– Optocouplers (applicable only for loads of TC matrix) : internal short-circuits
between leads, due to rupture of internal bonding, to be considered on a case by
case basis. Types 66168 (all LDC) and 66189 (LDC until 06) from MII-US are
potentially at risk
•
[REQ-TEC 16] In addition to the application cases defined §5 ([REQ-TEC 1], the DI is
required at locations of equipment power circuits where a loss of insulation could
propagate failures to equipment redundant functions or to equipment external interfaces
even in the case when power bus is protected outside the equipment.
•
[REQ-TEC 17] Equipment test connectors, internal test related harness and circuits shall
be subject to review against the herein requirements and shall be double insulated if a
mission critical risk exists.
A number of technological elements for implementation within equipments, that may be
concerned by situations where double isolation is required, are shown in § A1-2 of Annex 1.
This set of examples is not exhaustive and is given as guidelines.
In depth equipment analysis and supplier proposed solutions will be sole reference for
completion and compliance verification analysis.
Components installation that need specific attention during double insulation analysis :
•
[REQ-TEC 18] Component that need double insulation, shall be insulated by materials
which keep their insulating properties, including in case of high dissipation due to
component failure cases.
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[REQ-TEC 19] Large insulated metallic components or sub-assemblies shall have
redundant connection to ground through bleeding resistors to prevent ESD charging (see
example below). General Design Requirements specifications (RD.1 or RD.2 or RD.3 as
relevant) are applicable for authorized ungrounded area size.
•
[REQ-TEC 20] Inside the equipment, within the DI critical areas perimeter, the double
insulation analysis shall be applied to the directly connected circuits, taking into account
a potential short-circuit failure (refer to RD.6) of the circuit components. Double Insulation
shall be applied to the circuit if critical propagation is identified.
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7.5
PCB lay-out minimum proximities applicable requirements
The rules are applicable to simple and multilayer PCB depending on voltage, as shown below.
PCB double insulation requirements shall be applied when PCB circuits are deemed critical (ref.
REQ-TEC 1 and 12) :
− they carry power lines upstream of bus protections or
− there is a risk of failure propagation to redundancies or to other critical interfaces or loss
of cross-strapped functions on the same PCB (if short-circuit between tracks and/or
plated holes and/or pads)
PCB design requirements shall be :
•
[REQ-TEC 21] For the rigid PCBs, the table below reflects the design requirements to
be applied. The distances to be considered (PCB data from manufacturer) shall be the
minimum one, taking into account the worst case manufacturing tolerances. This table is
the expected outcome of the ESA/CNES harmonisation on PCB standards.
Minimun spacing (µm )
Voltage (V)
between
conductors
Layer to layer
External conductor
( DC or AC peaks )
Axis Z
In plane Axis X-Y
Internal conductor or
conductor to plated through
hole or to pad
In plane Axis X-Y
0 - 70
70
or 60 ( high density
via technology )
71 - 100
≥ 1 µm / Volt
120 when 17.5 ≤ h < 35
150 when 35 ≤ h < 60
200 when 60 ≤ h < 95
300 when h ≥ 95
(h : track thickness in µm)
101 - 300
≥ 1 µm / Volt
400
301 - 500
≥ 1 µm / Volt
800
U > 500
500 + 2.5 x (U-500) µm
800 + 3.05 x (U - 500) µm
70 when 12 ≤ h < 15
100 when 15 ≤ h < 17.5
120 when 17.5 ≤ h < 35
150 when 35 ≤ h < 60
200 when 60 ≤ h < 95
300 when h ≥ 95
(h : track thickness in µm)
Maximum value of
≥ 1 µm / Volt
or
120 when 17.5 ≤ h < 35
150 when 35 ≤ h < 60
200 when 60 ≤ h < 95
300 when h ≥ 95
500 + 2.5 x (U - 500) µm
The application of this table with the application of screening tests (ref. REQ-TEC 24) is illustrated by
examples given in §A1-3 of Annex 1.
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ADS
•
[REQ-TEC 22] For the flexible PCBs, the minimum gap shall be as defined in the
following table
Minimun spacing (µm )
Voltage (V)
between
conductors
Layer to layer
( DC or AC peaks )
Axis Z
Internal conductor or
conductor to plated through
hole or to pad
In plane Axis X-Y
0 - 50
50 µm
250 µm
51 - 250
≥ 1 µm / Volt
≥ 1 µm / Volt
251 - 500
U > 500
500 + 2.5 x (U-500) µm
500 + 2.5 x (U-500) µm
PCB double insulation specific requirements are :
•
•
•
•
[REQ-TEC 23] The PCB interlayer's insulation shall be made at least with 2 prepeg
layers (when prepeg layers are used)
[REQ-TEC 24] PCB shall be submitted to screening test approved by Prime, if the E-field
> 300 V peak per mm between any PCB equipotentials (see figures in Annex 1)
[REQ-TEC 25] PCB with critical areas (wrt DI perimeter) shall be identified in the critical
item list with the associated screening tests as agreed with Prime
[REQ-TEC 26] PCB tracks, plated holes and pads shall follow the following insulation
rules :
– PCB design rules are respected (minimum distance between tracks / layers /
connections compliant with E-field requirements and screening tests)
– the PCB is compliant with PCB insulation spacing requirements
– No track is routed under a SMC type component when either the track is a DI related
critical line or the component is in the DI related critical circuit
– the PCB is coated with a material conforming to those required for double insulation
– the coating minimum thickness is > 50µm TBC (refer to RD.7)
– KIP/MIP before coating and application processes allow to guarantee the absence of
pollution under coating
This requirement applies only to PCB tracks, plated holes and pads.
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•
[REQ-TEC 27] All parts and components mounted on PCBs and in the critical paths
shall be submitted to the double insulation rules. The coating minimum thickness shall
be between 50µm and 200 µm depending on coating material (refer to RD.7). A special
care shall be paid to sufficiently cover their salient points (both sides of PCB)
•
[REQ-TEC 28] For voltage above 500V, PCB design justification and screening tests
shall be submitted to Astrium for approval
.
7.5.1
PCB Screening tests requirements
[REQ-TEC 29] The following screening tests requirements shall be applied on top of the standard
ECSS-Q-70-11A (RD.8) or IPC 2221 A (RD.7) rules, where the calculated E-field is above 300
V/mm between any critical lines and any other track or pad or plated hole. The following tests shall
be applied :
A – New technology qualification
For each new PCB design, the build-up and design rules shall be thoroughly
examined to identify any deviation to existing qualifications at supplier level. If any
deviation is highlighted, the new build shall be qualified, following ESA standard
ECSS-Q-ST-70-10C but replacing the damp heat test (240h at 40°C and 93% RH)
with the specific THB (Temperature, Humidity, Bias) test defined hereafter.
The conditions to be applied for the THB tests shall be :
•
•
•
Environment : 40°C (+/- 2°C), RH >93% (+2%/-3%), duration 240 hours
Voltage Bias : to apply a voltage corresponding to Vmax between equipotential
circuits where the calculated E-Field (intralayer and interlayer) is the highest. Vmax
corresponds to the worst case maximum voltage (and shall include the spikes)
existing during the mission life.
Acceptance criterion : no electrical breakdown during THB test (insulation
resistance R> 500 MΩ)
Tests after ageing :
•
•
•
Visual inspection
Insulation resistance following ECSS-Q-ST-70-10C
Dielectric Withstanding Voltage following ECSS-Q-ST-70-10C
B – Screening / Acceptance test on each flight PCB
•
Measure at room temperature (22°C +/-4°C), the insulation resistance with a
minimum of 2x Vmax, 60 s between the different equipotential circuits. Vmax
corresponds to the worst case maximum voltage (including spikes) existing during
the mission life.
•
Acceptance criterion : insulation resistance R> 500 MΩ.
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Solar Arrays Double Insulation requirements
Considering the peculiarities of this equipment (environment and physical lay-out), specific
requirements for securing and implementing the DI requirements shall be applied mainly to prevent
damage to the existing insulation. They are outlined hereafter.
Solar Array related equipments and signal harnesses
•
[REQ-TEC 30] The solar arrays electrical related side-equipments (motors, deployment
devices,..) and signal harnesses if concerned, shall follow the rules previously defined for
harness and equipments in this document, using materials compatible with the space
conditions existing outside the spacecraft body.
Solar Array Structure Grounding
•
[REQ-TEC 31] All panel and yoke structures shall be insulated from each other and from
spacecraft ground. Each panel and yoke shall be connected to the spacecraft ground
through redundant bleeding resistors. Exceptions to meet this requirement (partial
deployment configuration or S/C body mounted SA panels) shall be approved by the Prime.
The requirements, below, for the Solar Array power harnesses design and installation are only
applicable to section lines from diode boards (just after wire solder or welds) up to spacecraft
interface connectors. The cell network, the individual strings and their wire connection to diode
boards are excluded.
Harness design and installation
•
[REQ-TEC 32] There shall be no area left with bare conductor all along each conductor
path, especially at connector interfaces
•
[REQ-TEC 33] For GEO and MEO missions, the cables shall have an external ESD bleeding
envelope (for example, the ASW type cable, specification GSC 05-82280-00) and charges
shall be evacuated to the panel or yoke structures. Alternatively, the cables ESD charging
behaviour acceptability shall be verified by adequate testing.
•
[REQ-TEC 34] For LEO missions with polar orbits, the cables ESD charging behaviour
acceptability shall be verified by adequate testing or with heritage data.
•
[REQ-TEC 35] the power lines cables shall be covered by at least 2 layers of insulating
material that can withstand the mission environment (radiation, ESD, thermal cycling, etc..)
without significant degradation (ref. to Annex 1 for approved cables). Shielded cable use for
power lines shall be approved by Astrium.
•
[REQ-TEC 36] Wire bundles need to be adequately protected against wear-out and
damages, including at tie-base locations
•
[REQ-TEC 37] Provisions shall be taken for harness and connector thermal distortions that
may induce stress at wire or connector contact levels and on the routing of the cables (stress
on wires at tie-base edge or other place of non uniform contact)
•
[REQ-TEC 38] To prevent wire insulation damage or damage propagation due to the severe
environment conditions, wire sharp bends shall be avoided wherever possible.
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[REQ-TEC 39] The solar array pin function shall be defined jointly by the project electrical
architect and the SA supplier to ensure the best possible segregation of the power section
paths e.g. separation of positive potentials and returns inside connectors and also between
superposed connectors or flexprints to prevent increased risk of propagating sustained arc.
This requirement shall be extended to the power harness section wires if magnetic moment
and line inductance increase are compatible with the system design.
Robustness to insulation degradation with propellant contaminants
The Spacecraft system manager will be responsible to identify and to have the equipment
specification incorporating the locations of the SA power transfer harness, which need to be
protected from the potential flux of thrusters (chemical degradation or erosion).
•
[REQ-TEC 40] The supplier shall implement protections at these locations.
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Solar Array Drive Mechanisms Double Insulation requirements
The principles and harness requirements defined previously in this document are applicable to the
SADM, however, due to the unique function of transferring live power and signals into the spacecraft
via rotating contacts, the additional specific requirements listed hereafter, shall be applied to this
equipment :
Design robustness
•
•
•
•
•
•
•
•
•
•
•
•
•
[REQ-TEC 41] Double insulation between any power live conductor1 and any other power
live conductor1
[REQ-TEC 42] Double insulation between any power live conductor1 and any return
conductor1
[REQ-TEC 43] Double insulation between any power live conductor1 and housing1 or any
wire1 or component connected to housing
[REQ-TEC 44] Double insulation between any power live conductor1 and any signal
conductor1
[REQ-TEC 45] Wires shall be covered by at least 2 layers of insulating material that can
withstand the mission environment (radiation, ESD, thermal cycling, etc..) without
significant degradation (for example ESA/SCC n°3901/001 cables)
[REQ-TEC 46] Minimum wire bend radius shall be > TBD mm
[REQ-TEC 47] The insulators geometry shall be stable (no shrinkage, no deformation,
etc..) whatever the equipment internal temperature variations during qualification operating
conditions
[REQ-TEC 48] Connectors shall follow the following rule :
– Adjacent contacts shall not have different potentials, unless connector design
ensures no visibility of bare conductor (Deutsch connector for example)
– Contact penetration (between pin / socket) shall be without gap, according to
connector supplier standards
[REQ-TEC 49] The maximum voltage taking into account worst case BOL solar array
voltage and current, also taking into account the voltage spikes due to the SA section
switching, shall be used for insulation design
[REQ-TEC 50] Following life tests, the particles / debris generation and size due to wear
out, burrs, etc…shall be assessed and compared to the metallic particle minimum size that
may generate a short-circuit (bridge) between any power live conductor and any other
conductor or housing, in the areas where double insulation cannot be implemented
[REQ-TEC 51] The design shall ensure that no foreign metallic particle / debris can enter
in the critical electrical and mechanical areas
[REQ-TEC 52] Select metal material assemblies to avoid metals corrosion
[REQ-TEC 53] To ensure that whiskers generation is not possible (refer to AD.3 for tin
whiskers), including risks with silver materials or other chemical contamination induced
reactions (H2S in air for example) on used materials.
Note 1 : Conductor shall include wires, rings, tracks, brushes, solder joints, any metallic part
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Grounding
•
•
[REQ-TEC 54] The floating metallic parts inside or outside equipment shall be grounded to
SADM housing (with Resistance < 1MΩ)
[REQ-TEC 55] Internal unused electrical circuits inside the equipment shall be grounded
or connected to ground via redundant bleeding resistors, unless they are accessible via an
external connector interface (then grounding will be done via the harness)
Manufacturing, Inspections
•
•
[REQ-TEC 56] Presence of metallic particles / debris inside equipment shall be avoided by
all means during manufacturing, assembly and tests. Dedicated inspection points and
cleanliness operations shall be set-up to ensure it.
[REQ-TEC 57] The following inspections shall be performed as a minimum :
– At finished individual metallic parts level (burrs or debris)
– At finished individual rotating contact level
– At finished non insulated parts (tracks, other metal pieces for traces of corrosion,
identify damages on the insulation barriers between tracks)
– At finished individual sharp metallic edges / tips
– Verification of surface uniformity and sticking to support of the conductive tracks
– Verification (batch basis) of hardness of contact tips and geometry
– Verification of wires bends radius once assembly is complete (or earlier if it cannot be
checked after assembly)
– After each assembly using through hole screws or bolts (check for generated metallic
particles and clean)
– Verify insulating material application process (for example check potting,
polymerisation samples, absence of trapped bubbles, check for installed sleeves, for
sleeves (if any) on brush spring, surface treatments, etc…)
– Verify cleanliness, geometry and wire protections against sharp edges after each
major assembly step, identify any unwanted area with bare conductor.
Equipment Acceptance electrical Tests
•
•
7.8
•
[REQ-TEC 58] Equipment power inputs shall be submitted to isolation tests at 500 V
during one minute minimum
[REQ-TEC 59] A critical pressure test shall be performed on each FM operated under
nominal power conditions
EGSE Double Insulation requirements
[REQ-TEC 60] EGSE areas, including cables, shall be double insulated where a single
insulation failure could propagate through the connected interfaces :
– damaging voltages/currents transmitted from the EGSE to the flight hardware (power and
signals interfaces)
– damaging currents drawn from flight hardware into the EGSE
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MATERIALS FOR USE IN DOUBLE INSULATION
The selection of a rigid or non rigid insulating material is authorised if it is resistant and maintains its
properties whatever the constraints undergone during lifetime (manufacturing processes, AIT
operations, environmental tests, launch, and in-orbit environment operation including exposure to
radiations that may induce mechanical, thermo-optical and electrical degradations in the material
properties).
[REQ-TEC 61] Materials selection used for double insulation shall be submitted to ground
storage and space environment analysis and proved acceptable for the mission conditions
with adequate qualification testing, including for the applicable failure mode operating
conditions. The qualification specimen shall be representative of the intended application,
e.g. manufacturing process and shape and/or assembly constraints.
Data on materials and typical values are provided for guideline information in A1-6 of Annex 1.
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ANNEX 1 – DI IMPLEMENTATION GUIDELINES
This section describes, with more details, some concrete cases of best practices for the
implementation of the double insulation protections. These are not mandatory as far as alternative
compliant solutions are proposed by supplier in response to requirements. In case of doubt, Astrium
shall be consulted for advice.
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Harnesses DI Guidelines
Insulation at Harness installation : (see figures below)
•
•
•
•
•
Kapton tape (50 µm max. to avoid ESD bulk charging) can be directly bonded on
structure under the harness or if not possible, wrapped (only for short distance ie max.
10 cm on power bundles to prevent bundle overheating) around the bundle
Kapton wrapping between wire and MLI (if aluminized face) or kapton applied on MLI
conductive face in front of harness if compliant to thermal requirements
Kapton wrapping or bonded on structure between power wires and structure
Permacel glass tape or kapton between wires and conductive tie-bases
Permacel glass tape or kapton between wires and edges (heatpipes, cut-outs, cable
clamp on circular connectors, backshells, equipment casing, screws,…), however taking
care of keeping efficient bonding of metallic floating parts where it is needed (using
bleeding resistors).
Harness splices or crimps :
•
2 kynar sleeves for all splices or crimps
Connector backside level : (see figures next page – ensuring no "visible" bare metallic area)
•
•
•
Enlarged barrel #18 contacts : 2 kynar sleeves
Other contacts : 1 kynar sleeve (case of TC or TM matrix wires)
Dedicated power connectors : if contact gauge does not allow to insert kynar sleeve
inside the connector body, an additional external protection shall be implemented
(kapton or potting for example)
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ADS
Connector insulation examples :
Case of double insulation within connector :
Contacts inside connector with gap > 1mm :
1. invariable gap due to contact holder piece
2. insulating material is the one provided by the holder piece
Contacts of Sub-D or Sub-D HD (high density) connectors are considered compliant to double
insulation rules if :
- spacing, rigidity and presence of insulator between contacts are guaranteed and
- equipment inspection processes (MIP, KIP, etc.) allow to guarantee both the absence of pollution
inside the equipment and the connector backside. Exceptions for inspection possibility shall be
justified.
Authorized harness cables :
This list may be extended with Prime approval.
Unshielded cables
Shielded cables
ESA/SCC 3901-001
ESA/SCC 3901-002
ESA/SCC 3901-002
ESA/SCC 3901-019
ESA/SCC 3901-019
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Examples of Bus Bars (here Telecom platform items for solar array sections or battery power
distribution)
Vgs Busbars :
Vp Busbars :
Vr and Vcm Busbars :
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A1-2
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Equipments DI Guidelines
The examples below correspond to various cases of DI implementation.
Item
Insulation
case
examples
(see figure)
Comments
Stiffener
Internal tracks
A
B
Housing case (variable gap)
PCB :
External tracks
C or D
Gap + surface coating
Qualified technology as IPC 2221 plus rules
in §7.5)
Opposite insulating materials
Figures for
insulation
example
PCB :
B
Gap (to be qualified functional rules) +
coating (caution with wettability, welding
protection, leads, implementation)
Gap uncontrolled + difficulty for insulating
material implementation. Technology not
allowed in this field of application
Ill-defined routing across PCB tracks
Either PCB coating first and cured (no
emafil contact with PCB), then emafil
covered by additional coating
Or sheath on emafil and PCB coating at
same time
B
Minimum non deformable insulating
material thickness wrt structure (bush,
washer,..)
A : use coating
C : opposite insulating materials or Kynar
sheath (tube)
Wrapping
Emafil
Bus Bar / Shunt mounting:
Mounting
Environment
Power component :
Mounting
A, C or D
B
Environment
A, C or D
Connector crimping
Connector with pins to solder
at PCB (straight or 90° bend)
A
A
External harness
Shield bonding
Conductor Core
Environment
Rigid Flex
B or D
D
D
As Bus Bar mounting
A : use coating
C : opposite insulating materials
C : Kynar sheath (tube)
Use a sheath (tube)
Backside bare metallic contacts to be
coated with potting all along from connector
to PCB
Use insulating material, overwrapped
protections
Use sheath (tube)
Use sheath (tube)
As PCB
Figure A1-2/1
Figure A1-2/1
Figure A1-2/2
Figure A1-2/3
Figure A1-2/2
Figure A1-2/4
Figure A1-2/3
Figure A1-2/3
Figure A1-2/4
Figure A1-2/5
Figure A1-2/8
Figure A1-2/7
Figure A1-2/6
Figure A1-2/6
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Other examples of double insulation implementation with PCB parts mounting :
PCB connections (between solder joints or solder joint and metallic cover) with gap < 1 mm :
- between solder joints :
1. varnish on first joint
2. varnish on second joint
- between solder joint and metallic cover :
1. varnish on solder joint
2. epoxy sheet
Tracks on PCB with gap < 1 mm :
1. epoxy material between tracks
2. varnish on tracks
Relay mounted on PCB with gap > 1 mm between relay case and PCB metallic stiffener :
1. epoxy as insulating material between relay and stiffener
2. invariable gap
3. relay mounting screw insulation and mechanical spacing
Board to board with gap > 1 mm :
1. invariable gap due to metallic PCB stiffener
2. insulation with coating
Relay used to carry primary unprotected power :
1. insulation due to internal relay build
2. double insulation required with rigid insulator between relay housing and mounting
structure. The insulator shall be able to withstand high dissipation, in case of arcing
inside the relay, to prevent propagation.
Diodes and transistors (with insulated case) in power path :
1. insulation due to internal component build
2. double insulation required with rigid insulator between component and mounting
structure. The insulator shall be able to withstand high dissipation to prevent
propagation, in case of component failure.
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The figures below and on the following page, present guidelines for various examples of acceptable
configurations, related to double insulation of component mounting and PCB interfaces.
Figure A1-2/1 : Printed Circuit Board and Mechanical Case
A : between track and rigid structure (unvariable gap >1mm) : apply
coating only
B : between tracks on PCB (rigid spacing) : apply coating
C : between track and non rigid structure : apply coating and rigid
insulation on structure (case gap > 1 mm)
D : between track and non rigid structure : apply coating and rigid
insulation on structure (case gap < 1 mm)
Figure A1-2/3 : Power Components surroundings
A : between track and metal case (unvariable gap >1mm) : apply
coating only
C (gap > 1 mm) :
•
between case and non rigid structure : apply coating and rigid
insulation on structure
•
between case and rigid structure : apply coating on component
case
D : between case and non rigid structure : apply coating and rigid
insulation on structure (case gap < 1 mm)
Notes :
•
ensure additional coating to cover sharp edges of components
•
in case, component has a dissipative failure mode, ensure that at
least one of the insulator materials can withstand the maximum
temperature
Figure A1-2/2 : Power Components Mounting
First barrier : minimum thickness of non deformable materials
(washers, bushes,..) used to mount the component
Second barrier : coating
Figure A1-2/4 : Leads/Structure
Case insulation :
First barrier : rigid insulator materials (bush, washers)
Second barrier : coating (if gaps < 1mm)
Leads insulation :
First barrier : sleeves
Second barrier (if gap < 1mm) : structure anodization for example
Note :
•
underneath transistor, the leads exit through glass beads,
defining an unvariable gap between lead and case. If this gap
is < 1mm, coating is advised providing that it will not generate
damaging constraints to the beads across the unit operational
range
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Figure A1-2/5 : Crimping
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Figure A1-2/6 : Wire with Shield Bonding
First barrier : connector body (pattern A > 1 mm)
Second barrier : overlapping sleeve covering contact body (inside
connector) and wire
In case A<1mm, the back of the connector shall be potted (ex. MDM)
Use sleeves to contain the shielding braids, fold back shield
Figure A1-2/7 : External Harness / Wiring
•
•
•
Wires are overwrapped in areas of fixation (tie-base) or around
sharp edges or where wear out is possible
If the wires are routed closely to a structure element (gap < 1mm
or variable), a kapton tape is placed below the bundle along its
route
If the bundle is unambiguously with a gap > 1mm alond its
length, then the wire insulator itself plus the gap fulfill the double
insulation requirement
Figure A1-2/8 : Connector back insulation protection
•
•
First insulation barrier obtained by coating the contact bare
metallic areas all along its length
Second barrier is due to the mechanical spacing between the
contacts as imposed by the connector build and PCB
Area at risk
•
Secured area
No bare metallic part shall be left exposed, hence the back of
connector contacts shall be coated or sleeved
•
If B < 1mm or variable, kapton tape or insulator shall be applied
along the bundle route below the cables (typically on the
structure item)
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Components design and installation that need specific attention during double insulation analysis :
•
Bus capacitors (possibility of short-circuit if not self healing)
•
Feedthrough capacitors or filters : possible short-circuit or short-circuit to housing
•
Transformers (between leads or between primary and secondary, between windings
depending on design)
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A1-3
PCB Double Insulation rules
The application of the PCB lay-out proximities with the application of screening tests is illustrated by examples
given in the following figures showing :
– Above the green line, no screening test is required
– When red or blue lines are below the green lines, a screening test is required
– Below the red line : forbidden use
Note : in figures below, the blue line (case with a different copper thickness) is hidden exactly behind the red line
respectively above 100V (PCB external) and above 150 V (PCB internal).
PCB Internal (in plane X-Y)
Tracks minimum gaps (µm)
PCB External (In plane X - Y)
Tracks minimum gaps (µm)
1700
1700
1600
1600
1500
1500
Required spacing (µm)
1400
Acceptable zone for
Double Insulation
No screening test
1300
1200
1100
Acceptable zone for
Double Insulation
Screening test
required
1000
900
800
17.5 µm <
track thickness
< 35 µm
1300
Required spacing (µm)
1400
60 µm < track
thickness < 95
µm
Screening limit
(µm)
700
600
500
400
1200
Acceptable zone for
Double Insulation
No screening test
1100
1000
Acceptable zone for
Double Insulation
Screening test
required
800
700
600
35µm < track
thickness < 60 µm
Screening limit
(µm)
500
400
300
300
200
< PCB Standard requirement
Min 120 µm
Š
100
200
E-Fied > 1 kV/mm
100
Min 70 µm Š
0
0
0
100
200
300
400
500
0
100
Voltage (V peak)
200
300
400
500
Voltage (V peak)
Flexible PCB (In plane X-Y)
Tracks minimum gaps (µm)
PCB Internal (Axis Z)
layer to layer
2500
1700
2250
1600
1500
Acceptable zone for
Double Insulation
No screening test
2000
1750
1400
1300
1500
Acceptable zone for
Double Insulation
Screening test
required
1250
1000
Interlayer
requirements
Screening
limit (µm)
750
500
Required spacing (µm)
R eq u ired sp acin g (µ m )
Track thickness
<15 µm
900
Acceptable zone for
Double Insulation
No screening test
1200
1100
1000
900
Acceptable zone for Double
Insulation
Screening test required
800
700
600
500
400
250
< PCB requirement
Min 70 µm Š
0
E-Fied > 1 kV/mm
300
Min 250 µm Š
200
< PCB standard requirement
100
0
100
200
300
400
500
600
700
Voltage (V peak)
0
0
50
100
150
200
250
300
350
400
450
Voltage (V peak)
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Solar Array Double Insulation Guidelines
Power section wiring protection :
•
In case the tie-base is not used for ASW cable grounding, a protection shall be wrapped
around cables at tie-base location (standard harness installation) with a material compatible
with radiation and temperature cycling environments.
In case the tie-base is metallic and is used as a mean to evacuate the wire ESD charges to
the panel structure, the tie-base design or the harness attachment and its process shall be
such that no wire is overlapping over any edge of the tie-base nor is bent over an edge.
Alternatively, "conductive" black kapton wrapping around bundle at tie-base location could
be used.
•
See photo below for some specific bundle attachment acceptance criterion with conductive
tie-base :
At risk areas :
(not acceptable)
Acceptable installation
A1-5
SADM Double Insulation Guidelines
SADM Equipment connector shell grounding :
Two potential options could be proposed :
• SADM housing grounded to Spacecraft structure with connector shells which shall be
grounded to :
– Solar Array side (yoke) for the SA interface connectors
– Unit housing or mounting bracket for the spacecraft interface connectors
or
• For potential increase of the robustness to SADM internal short-circuit to housing, it might
be better to have the SADM insulated from the spacecraft structure and the SADM shall be
grounded to structure through redundant bleeding resistors (on E3000, this would mean
that SADM / SC connector bracket shall also be insulated and grounded via bleeding
resistors).
Equipment Acceptance electrical Tests :
•
Static and rotating Qualification and Acceptance electrical tests shall be run with the
maximum specified current simultaneously applied through all power lines and maximum
specified voltage gradients. Bundle internal temperature shall be monitored. The solar
array interface rotation speed shall not be greater than twice the nominal average
operating speed and a full revolution shall be accomplished for the hot and cold extreme
temperature settings.
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Materials Guidelines
A1-6.1 Materials Selection Guidelines
To be considered as an electrical insulator, the surface/material used for double insulation shall
have :
• Ability to withstand a minimum of 500V DC voltage or two times the peak voltage, whichever is
greater
- for unlimited duration
- with a minimum resistance of 100 Mohms
- with no degradation of its resistance during or after the exposure to such voltage
• Ability to withstand electrical fields up to 107 V/m, i.e. a minimum dielectric strength of 10 kV/mm
• A thickness able to withstand required voltages (depending on dielectric strength)
• A dielectric permittivity εr typically lower than 4 to prevent effects from a too high capacity.
• Ability to prevent ESD risks i.e.
- A surface resistivity lower than 109 Ω.square to prevent from surface dielectric charging
- A bulk resistivity lower than 109 Ω.m for EOS (RD.1) or lower than 1011 Ω.m to 1013 Ω.m
depending on material thickness and location for T (RD.2, RD.3), to prevent from deep dielectric
charging (note that Radiation Induced Conductivity (RIC) must be taken into account for some
materials). The lower values are quite never achievable on most of polymer materials, but polymers
with resistivity lower than 1013 Ω.m are accepted because ESD risks have been noticed to occur but
above this limit.
• A Vickers Hardness high enough to avoid mechanical degradation of the coating barrier
• The ability to sustain the mission radiation doses while keeping its characteristics
Typical characteristics to be considered for the insulating material are summarized in the table
below :
Units
Decisional value (BOL) or
assessment
DC Voltage ability
---
500V unlimited time, >100 MΩ
Dielectric strength
V/m
> 10 kV / mm
ESD risk mitigation ability : Bulk resistivity (1)
Ω.m
Material Parameters
Ability to sustain high dose levels
Dose level
< 109 Ω.m (EOS)
1011 Ω.m < TBD < 1013 Ω.m (T)
Poor / Low / Correct
MRad
Surface or bulk degradation
analysis (2)
Note 1 : the values are for general indication, material geometry or characteristics may lead to variations (ref. AD2)
Note 2 : Surface degradation (example coating) : may affect the thermo-optic properties
Bulk degradation : may affect the mechanical and/or electrical properties
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A1-6.2 Evolution of properties of materials and associated guidelines
Ground storage influence
Even in a controlled environment, ability to withstand humidity (which is the major influence
parameter) during several years storage is mandatory. Ground typical lifetime is 1 or 2 years in a
controlled environment (cleanroom). This lifetime can be extended in some cases to several years
in case of spacecraft storage or manufacturing of several spacecrafts not being launched at the
same time. In that case, humidity can degrade dielectric strength which implies adequate wet
damping tests to demonstrate that material still have acceptable values for required application.
In orbit environment influence
Ability to withstand space environments effects during in orbit lifetime is mandatory.
In orbit typical lifetime is 15 years in for Telecom or meteorological spacecrafts in GEO orbits or 5 to
10 years for Earth Observation satellites in LEO orbits. For satellites in MEO orbits, if no data is
available, the Galileo conditions (RD.9) will be a sufficient first approximation for materials selection
(depending on duration lifetime). For planetary probes or specific scientific missions, a case by case
analysis is needed.
The influence parameters are :
− Vacuum
− Thermal cycling
− Atomic Oxygen (only orbits below 1000 Kms) with effects on materials facing Atox fluxes
o
−
Atox erosion ratio is measured with reaction efficiency parameter in 10-24 cm3/atom
Radiations effects i.e.charged particles and UV :
o
o
Mainly electrons in GEO and protons in LEO (inside radiative belts in that case).
With radiation doses1 depending on material location wrt spacecraft body :
ƒ GEO :
− Highest (greater than 1 GRad) external, facing outer space
− Medium (typ. 300 MRad max.), external under MLI, one side protected by
structure panel
ƒ LEO (standard orbit <900 kms) : Highest external facing outer space, cumulating
around 2.5 MRad/year
ƒ Lowest (typ. some 20 KRad), when shielded.
See example in table below :
PTFE
location
GEO
INTERNAL
Dose analysis
dependant
EXTERNAL
Prohibited 2
LEO
Ground
PET
location
GEO
LEO
Treeing effects
on some PET
INTERNAL
Atox analysis
dependant
EXTERNAL
Ground
Dose analysis
dependant
Atox analysis
dependant
Treeing effects
on some PET
Notes :
1. Radiation dose levels to be considered - either for material degradation analysis or for tests representativity - depend
on depth considered : maximum in surface, lowering when depth increases
2. Shielding of PTFE material may reduce the radiation levels to acceptable values
Effects are the following :
− Mechanical degradation
− Thermo-optical degradation
− Electrical degradation (ESD risk), generally increased by darkness and low temperature.
At system level, the EMC/ESD analysis shall confirm that material does not induce
unacceptable ESD risks
Mainly mechanical and electrical degradation can lead to loss of insulation properties.
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A1-6.3 Example of Materials Selection
Providing the analyses outlined in §8, some materials listed below could be used for insulation.
They have abbreviated acronyms listed hereafter and are sometimes known by their trademark :
ECTFE = Ethylene chlorotrifluoroethlyene (Halar®)
ETFE = ethylene-tetrafluoroethylene-copolymer (Tefzel®)
FEP = fluoroethylene-propylene (Teflon-FEP®)
LCP = liquid crystal polymer
PEEK = Polyetheretherketone (Victrex® PEEK™)
PEI = Polyetherimide (Ultem®)
PET = Polyethylene terephthalate (Mylar®)
PI = Polyimide (Kapton®)
PPS = Polyphenylene sulfide (Ryton®)
PTFE = polytetrafluoroethylene (Teflon-PTFE®) - (usable only if cumulated life radiation dose
is < 1 MRad, after which the mechanical properties are degrading)
PVDF = Polyvinylidene-fluoride (Kynar®) – Only for internal use if not shielded (radiation
sensitive)
TFE = tetrafluoroethylene (Teflon-TFE®)
Some materials are forbidden for space applications and have been identified in RD.4.
The following table and following paragraphs give typical indications of the material BOL
characteristics and known prohibited use. The final selection of materials shall be made after a
mission analysis (on ground and in-orbit) and validation testing if necessary, to take into
account the mission specific combined constraints (electrical and mechanical degradations, ESD
charging,…).
Table legend :
ƒ
ƒ
ƒ
Red : prohibited for some applications
Yellow : acceptable pending analysis
Green : acceptable
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ADS
MATERIALS TYPICAL CHARACTERISTICS
Material
ETFE
Most usual
Chemical name commercial
name
Temperature
range
Ability to
mitigate ESD
risk
Ability to
sustain high
dose levels
Typ. BOL
dielectric
permittivity εr
Typ. BOL
dielectric
strenght
(kV/mm)
Typ. Hardness
(Vickers)
Comments
Use
Ethylenetetrafluoroethylenecopolymer
-100/+155°C
LOW
LOW
2.5
15
10
Charging
observed
GEO external use
risk assesment
-250/+205°C
POOR
POOR
2
20
4
Charging
observed
Not for GEO
external use
?
?
2.5
40
35
GEO external use
risk assesment
3
15
26
GEO external use
risk assesment
FEP
Fluoroethylenepropylene
LCP
Liquid Crystal
Polymer
PEEK
Polyetheretherketone
Tefzel®
Victrex®
max +250°C
LOW
MEDIUM
(TO ANALYSE)
PEI
Polyetherimide
Ultem®
max +170°C
?
LOW
3
20
20
GEO external use
risk assesment
PET
Polyethylene
terephthalate
Mylar®
-75/+125°C
TO ANALYSE
LOW
3.5
40
2
GEO external use
risk assesment
Kapton®
-220/+200°C
TO ANALYSE
CORRECT
4
15
25
Ryton®
max +230°C
LOW
3
15
12
PI
PPS
Polyimide
Polyphenylene
sulfide
MEDIUM
(TO ANALYSE)
PTFE
Polytetrafluoroethyle
ne
Teflon ®
-260/+260°C
POOR
POOR
(OK < 1 Mrad)
2
15
6
PVDF
Polyvinylidenefluoride
Kynar®
-55/+175°C
LOW
LOW
9
10
9
ALL VALUES ARE DERIVED FROM GRANTA (MATERIAL UNIVERSE DATABASE) - TYPICAL VALUES ARE GIVEN FOR AN UNLOADED POLYMER THESE VALUES SHALL NOT BE USED DIRECTLY I.E. WITHOUT VALIDATION ANALYSIS FOR THE MISSION.
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charging effects if
>50µm
GEO external use
risk assesment
GEO external use
risk assesment
Charging
observed
Not for GEO
external use
GEO external use
risk assesment
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Document Nr : ADS.E.1031
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A1-6.3.1 Rigid barrier materials
Thickness data below is for indicative information only.
Polymers materials for wire insulation :
- Wire insulation : PI, TFE, PTFE, ETFE, FEP
- Shrinking sleeve : PVDF
- PPS
Polymers materials that can be used as rigid barrier:
- Insulating epoxy resins or adhesives (as EC2216) only if thickness > 100µm
- Polyimids (PI) ≥ 50 µm (charging effects to be mitigated as necessary)
- Fluoropolymer (Fluoropolymer are forbidden for use outside equipments) : PI, TFE, PTFE,
ETFE, FEP,PVDF, PEEK, LCP only if thickness > 100µm
Note that a too high thickness induces deep dielectric charging and increases ESD risks
Glasses materials that can be used as rigid barrier :
- Glasses and glass fibers
- Glass / Epoxy compound (G11, FR4, Stycas® 2850, …), including the called "pre-peg"
materials
- Glass / PI compound washers only if thickness > 1mm (Vetronite,…)
Ceramics and metallic oxides materials that can be used as rigid barrier :
- Ceramics (if no risk of crack under mechanical or thermo-mechanical constraints in the
assembly)
- Alumina, only when formed by method of MAO (micro-arcs oxidation)
- Beryllium oxide
Rigid barrier materials to be submitted for approval (i.e. considered as rigid on a case by case
basis - after Prime approval) :
- Fluoropolymer if 50µm < thickness < 100µm
- Insulating epoxy resins or adhesives if thickness < 100µm
- Alumina only formed by method of anodic oxidising (OAS/OAD)
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A1-6.3.2 Non-Rigid barrier materials
Thickness data below is for indicative information only.
Materials that can be used as non rigid barriers:
- Fluoropolymer : PI, PTFE, FEP, ETFE, PVDF, PEEK, LCP (with the notable exception of the
TFE if thickness < 50µm)
- Polyimids (PI) < 50 µm (charging effects to be mitigated as necessary)
- Silicone (VMQ)/ fluorosilicone (PVMQ) Polymer (MAPSIL 213, CHO-TERM,…)
- Polyurethane varnishes (Solithane C113, Potting E505,…)
- PET film (Mylar®,…)
- Quartz
- Any insulating varnish or potting, mixed with non conductive filler or not
The use of varnish, resin or any other coating or potting material as an insulating material is
authorised only when :
− its density allows it to cover and to adhere to all surfaces, even the more pointed
(component leads, object corner, sharp edges, etc.)
− its thickness can be controlled
Materials minimum thickness for non rigid barrier materials definition will depend on used material,
values defined for coating in § 4.5 of RD.7 can be used as a first approximation before application is
fully qualified by supplier. It is expected a typical minimum of 50µm coating on flat surfaces (for
example PCB component side) or 200 µm in areas with pointed / component leads.
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ANNEX 2 – APPLICABILITY OF TECHNICAL REQUIREMENTS TO EOS
This section provides an applicability matrix of this document technical requirements for the EOS programmes
depending on their selected quality class (C1, C2 or C3). The C1 class is applicable as the baseline reference
unless another class is explicitely defined to supplier.
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ADS
Requirement
Class 1
(reference)
Class 2
REQ-TEC
1
x
x
REQ-TEC
REQ-TEC
REQ-TEC
2
3
4
x
x
REQ-TEC
5
x
x
x
x
REQ-TEC
REQ-TEC
REQ-TEC
REQ-TEC
REQ-TEC
REQ-TEC
REQ-TEC
REQ-TEC
REQ-TEC
REQ-TEC
REQ-TEC
REQ-TEC
REQ-TEC
REQ-TEC
REQ-TEC
REQ-TEC
REQ-TEC
REQ-TEC
REQ-TEC
REQ-TEC
REQ-TEC
REQ-TEC
REQ-TEC
REQ-TEC
REQ-TEC
REQ-TEC
REQ-TEC
REQ-TEC
REQ-TEC
REQ-TEC
REQ-TEC
REQ-TEC
REQ-TEC
REQ-TEC
REQ-TEC
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Identification
only
x
Guideline
x
x
Guideline
x
x
Class 3
Power
Propagation
Safety
x
x
x
x
Guideline
Guideline
Guideline
Guideline
x
Guideline
Subject
Generic
Requirements
Harnesses
REQ-TEC 5 only
x
x
x
x
x
x
x
Guideline
x
x
x
x
Guideline
Guideline
Guideline
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Electronic
Equipments
x
Printed Circuit
Boards
x
x
x
x
x
x
x
Solar Array
Equipment
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ADS
Requirement
Class 1
(reference)
Class 2
Class 3
Subject
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Solar Array
Drive
Mechanism
Equipment
REQ-TEC
REQ-TEC
REQ-TEC
REQ-TEC
REQ-TEC
REQ-TEC
REQ-TEC
REQ-TEC
REQ-TEC
REQ-TEC
REQ-TEC
REQ-TEC
REQ-TEC
REQ-TEC
REQ-TEC
REQ-TEC
REQ-TEC
REQ-TEC
REQ-TEC
REQ-TEC
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Guideline
REQ-TEC
61
x
x
EGSE
Materials &
Processes
Table Legend :
X : applicable requirement
Guideline : for information and guideline
Void : requirement not applicable
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For Information Only
These information have been generated on the 03/09/2010 10:27:24 and may have been
updated. Please refer to document properties in database for up-to-date information
ADS.E.1031
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Electrical Double Insulation - Technical Requirements
to Suppliers
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ADS.E.1031
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Applicable
Requirements
English
03/08/2010 14:48:58
A. Vaissière / JY. Heloret / JL. Diemunsch
P. Wood
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