International Conference on Electrical, Electronics, and Optimization Techniques (ICEEOT) - 2016
1
1
2
Associate Professor
Department of Electronics and communication.
National institute of Technical Teachers Training and
Research, Chandigarh
AbstractThe demand of transistors is rising in today’s communication system having high data rate. Transistors are used in many applications where high gain is needed by using very low frequency. In today’s communication system amplifier is used in many applications such as low noise amplifier, broadband mixer, distributed amplifier, power amplifier etc. The pair amplifier satisfy all parameters which is required by today’s technology such as-high speed transmission efficiency, less power consumption and less circuitrary to be used pair is used in advanced version of small signal amplifier with additional biasing resistance which improves voltage gain and widening of bandwidth. It also removes poor frequency response of pair amplifier at higher frequency. In this paper, cadence software is used to study the circuit of two-stage amplifier. In this paper after adding biasing resistance in emitter terminal of first transistor we can increase the voltage gain, current gain, output current and output voltage of pair amplifier. GPDK 90nm technology is used in this paper.
frequency response [17]. A pair amplifier has compact chip size and broadband performance that is why it is used in high speed applications. The pair amplifier can be extended up to three transistor cell [14] [9].
Keywords: Pair, Load capacitor, Circuit simulation, Circuit design,
Small signal amplifier, 90nm technology.
I.
I NTRODUCTION
A single transistor is made by putting two transistors inside single packet, which is having high gain, and high input impedance is known as pair amplifier[2][6][9]. Pair amplifier is used in various communication circuits for amplification of small signals [1] [3].
β
D =
β
Q1.
β
Q2
1
In equation 1 β
D
is current gain of whole unit. β
Q1 is current gain of first transistor and β
Q2
is current gain of second transistor [15] [16]. In amplifier, input resistance is very high and output resistance is lower than that of a single stage emitter follower [12] [13]. The main disadvantage of pair amplifier is that at higher frequency, it produces poor
Fig 1. Basic circuit of pair amplifier [6] [9]
It normally consists of two transistors. The Emitter of input transistor is connected directly to the base of the second [16]
[17]. Both collectors are connected together. Two capacitors are used in above circuit one is input capacitor (C second is output capacitor (C o
). One resistance is in emitter of
2 nd u
) and
transistor (R e
) [6] [9]. Two other resistances are also there
R
1
andR
2
.Upper line is V cc
line and lower line is ground. In this way, the base current from the first transistor enters the base of the second [6] [9].
978-1-4673-9939-5/16/$31.00 ©2016 IEEE

International Conference on Electrical, Electronics, and Optimization Techniques (ICEEOT) - 2016
As there are two base emitter junctions, the turn on voltage for the overall pair is twice that of a single transistor [1] [2].
When using a pair configuration in a new electronics
ll. CIRCUIT DIAGRAM design, it is necessary to account for the fact that it has a greater phase shift at higher frequency, than a single transistor.
This can result in the overall circuit having a greater likelihood of becoming unstable if negative feedback is used in the circuit[2][12][13]. Often when making a pair, the output transistor is required to be able to handle high levels of current
[8].
High power transistors typically have lower levels of current gain than the small signal varieties. This means that often the input device is a small signal high gain variety, whereas the output transistor is a high power device with an inherently lower current gain [12] [14] [15]. The main disadvantage of silicon transistor is its low current gain and variations in current gain [2] [6]. Today’s technology requires transistors with large current gain with stability by employing negative feedback. Best solution to remove this problem is pair amplifier, which gives large current gain with large stability [9] [15]. A pair amplifier has potential for high speed applications due to its compact chip size and broadband performance [15].
There are some techniques have been proposed to increase the performance of pair amplifier like The hetero junction bipolar transistor (HBT), high electron mobility (HEMT)
Transistors pair, series inductance, pole zero compensation technique etc.[12][13].
In the present paper, we proposed various modifications in
Fig 2. Schematic diagram of the conventional pair amplifier [2].
In the above figure two NPN transistors is used emitter of
1 st transistor is connected to base of 2 nd transistor. It is a common collector circuit [2] [5] [7]. Some resistances and capacitors are used with different values. One capacitor is used as load capacitor.one input capacitor is also on this circuit [2] [4] [6]. small – signal pair amplifier circuit and calculated some different results that may be useful for various applications.
In comparison to bipolar conventional pair, we can also design a mosfet configuration to reduce supply voltage (v dd
) and dc consumption power (p c
) [14] [15]. If we increases the collector current in pair amplifier, DC consumption power also increases and noise also increases, we can remove this disadvantage by designing a single input single output (SISO) amplifier based on MOSFET pair configuration[14][15].
We can also use pair amplifier in the designing of CMOS operational amplifier, which increases the gain as well as
UGB, by using capacitor technique and proper biasing circuit.
We can use CMOS operational amplifier for wireless communications due to low power consumption, high bandwidth, high gain and high noise immunity [14] [15]16].
Recently, there is rising demand of Darlington products for the high data rate communication system. Darlington transistors are used in applications where a high gain is needed at a low frequency [14]. Recently Darlington cell and
Darlington topology have been reported high gain and good bandwidth for modern application [15] [16].
Fig 3. Shows the schematic diagram of proposed pair amplifier configuration.
This circuit is designed using cadence analog and digital system design tools of GPDK 90nm technology.
In electronics, amplifying signal by using pair is very important. In above circuit, two same bipolar junction transistor in common collector-common emitter connection.
Pair amplifier has large ranges of applications, which varies
978-1-4673-9939-5/16/$31.00 ©2016 IEEE

International Conference on Electrical, Electronics, and Optimization Techniques (ICEEOT) - 2016 from small-signal amplifier to power-amplifier circuits [2] [3]
[10]. Two capacitors are used in the proposed circuit one at the input terminal and one at the output terminal as a load.
One biasing resistance is added at emitter terminal of 1 st transistor. Two nmos transistor is used in this circuit. Some extra resistances and capacitor are used in the circuit [3] [11].
Conventional and proposed amplifiers (Fig.2 and Fig. 3) use NPN transistor in respective units. Other parameters and
DC biasing supply that are used to design respective circuits are shown in Fig.2 and Fig.3. 1.2 v AC input signal are fed to both circuits but respective observations are received as shown later in the table through cadence software.
The performance of pair amplifier is very poor at high frequency. To improve the poor performance of circuit at high frequency, some extra biasing resistor at emitter of first transistor is added [2] [3] [6].
Fig. 5. Shows the comparison of DC response and transient response of schematic in Fig 3.This graph is also obtained from fig 3 on cadence analog and digital system design tools of gpdk 90nm technology
In transients response time is varying with voltage and current, where voltage and current are taken in mv and ma respectively. Blue line indicates R o
minus, purple line indicates R o
plus, green line indicates net10 [v (mv)], orange line indicates net 011 [v (v)]. In case of DC response time is varying with voltage, X-axis represents time and Y-axis represents voltage, that voltage we get around 0.87v.
Fig 4. The result shows the transient response of the above schematic diagram obtained from Fig 3. This figure is obtained after we get simulation and running of referred model in Fig. 3 on cadence analog and digital system design tools of GPDK 90nm technology.
Time is considered on X-axis, time is taken as 25ns, 50 ns,
75 ns and 100ns and voltage is considered on Y-axis. Red color represents input voltage that is 2v; green line indicates output response which shows that output voltage is 2.75v, after that it is a straight line.
Above response shows, that output voltage is in amplified form as compared to input voltage.
Fig. 6. Shows the final layout of schematic diagram shown in Fig. 3. This layout is semicustom. This fig. is also obtained on cadence analog and digital system design tools of GPDK 90nm technology.
In this layout green color represents polysilicon, blue line indicates metal1 and metal 2 , yellow line indicates NPN
978-1-4673-9939-5/16/$31.00 ©2016 IEEE

International Conference on Electrical, Electronics, and Optimization Techniques (ICEEOT) - 2016 transistor, white color represents metal to diffusion contacts , red color is for oxide layer[16][17].
This layout is based on λ rules which states that minimum width between metal diffusion should be 4 λ . The contacts should be 2 λ *2 λ and surrounded by 1 λ on the layers above and below [15] [16] [17].The Width of polysilicon should be 2 λ .
The Polysilicon overlaps diffusion by 2 λ where transistor is desired and has a spacing of 1 λ away where no transistor is
The authors are thankful to Dr. M. P. PUNIA Director
NITTTR, Chandigarh for support during this research. The author would also like to thanks to Dr. Maytre, Professor and head, ECE department, NITTTR Chandigarh for helpful suggestions.
V ACKNOWLEDGEMENTS desired [15] [16].The spacing between two polysilicon and contacts should be 3 λ . The N-well surrounds PMOS transistors by 6 λ and avoids NMOS transistors by 6 λ [16]
[17]. lll. RESULT ANALYSIS
VI REFRENCES
[1] S. Singh, B. B. Soni and P. Gour, “ Review on transistor for recent modern application”, I.J.C.A vol. 112, pp. 10, Feb 2015.
[2] M.H. Ali, and A.S Aminu,” Analysis of Darlington pair in distributed amplifier circuit. IOSR-JEEE. vol.10, pp 77-80. April 2015.
[3] S. N. Sukla, R. Singh, B. Pandey,”Qualitative analysis of pair based modified small-signal amplifier . International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering ”,vol. 4, pp. 2181-
2186, April 2015.
PARAMETER REFERRED
MODEL
PROPOSED
MODEL [4] T. Sood, and R. Mehra,” Design a low power half substractor using .90µm
VOLTAGE
GAIN
CURRENT
GAIN
OUTPUT
VOLTAGE(v)
OUTPUT
CURRENT(µA)
[5] A. Sharma and R. Mehra,” Area and power efficient cmos adder design by
8.1 9.8
16.9 20.2
Communication Technologies (GCCT),
2015 Global Conference. pp 273-276, April 2015
1.6 2.01
[7] A. Sharma , R. Singh and R. Mehra,”Low power TG full adder design using CMOS nano technology”, IEEE, Parallel Distributed and Grid
Table 1. Shows the parameters of referred model and proposed model. These values are calculated by using calculator on cadence analog and digital system design tools of GPDK 90nm technology
Various important parameters of respective amplifiers are calculated based on simulation results and the outcomes are listed in above Table 1 for a fast qualitative comparison. We can say that, voltage gain in referred model is 16.01 and in proposed model it is 20.5. At the same time, we see current gain in referred model is 8.1 and in proposed model it is 9.8.
Respectively, we can see output voltage and output current.
Computing (PDGC), 2012 2nd IEEE International Conference on vol.6, pp
210-213, Dec. 2012.
[8] S. Sukla and B. Pandey,” Two stage small signal amplifier with and szikai pairs, IEEE, pp 13-16. 2014
[9] D.G. Duff and H.C. Poon,” An Analysis of low frequency second-order distortion in bipolar transistors applied to an amplifier, IEEE,Vol.8, pp- 447-
453, 1973.
[10] A. Verma and R. Mehra,” Design and analysis of conventional and ratioed CMOS logic circuit”, IOSR-JVSP, vol-2. pp-25-29, April, 2013.
[11] S. Sharma and R. Mehra,” Area and power efficient design of XNOR-
XOR logic using 65nm technology”, International Journal of Engineering and
Technical Research, , pp-57-60, April. 2014.
[12] A. Papoulis ,”Darlington's synthesis and RMS error evaluation”, IEEE
Circuit Theory, IRE Transactions. vol-8, ,pp-58-60. 1961
, lV CONCLUSION
By analyzing the Table 1, it is concluded that voltage gain and current gain of proposed pair amplifier model is greater than referred model. Output voltage and output current of proposed pair amplifier is greater than referred model. Finally, it is concluded that after adding some biasing resistance in emitter terminal of 1 st transistor we can increase the voltage gain, current gain, output voltage, and output current of pair amplifier. Therefore, we can increase the performance of pair amplifier.
[13] H.J. Motlak ,”Design of low voltage low power (IF) amplifierbased- on
Mosfet configuration”, Circuits and Systems, vol-4(3), pp 269-275. July
2013.
[14] M.A. Schaning and K.A. Kaczmarek,” A high-voltage bipolar transconductance amplifier for electrotactile stimulation,” IEEE Trans Biomed
Eng.
vol.
55(10) pp. 2433-244. October 2009.
[15] S. Shuklaand and S. Susmrita, Small-signal amplifier with three dissimilar active devices in triple darlington topology, International Journal of
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International Conference on Electrical, Electronics, and Optimization Techniques (ICEEOT) - 2016
Advanced Research in Electrical, Electronics and Instrumentation
Engineering, vol. 2(4). pp. 502-508, Dec. 2013.
[16] R. L. Boylestad and L. Nashelsky, “Electronic devices and circuit theory,
New Delhi, India Pearson, 2009.
[17] M. H. Rashid, “Microelectronic circuit analysis and design, Canada
Cengage learning, Inc, 2011.
Er. Rashmi singh: Er . Rashmi Singh is presently a M.E student from National Institute of Technical
Teachers Training and Research, Chandigarh India. She has obtained her B. Tech from U. P. Technical university luck now, India in 2005. She is having seven years of teaching experience. Her areas of interest include Advanced Digital
Signal Processing and optical fiber communication.Mail.id contecter.rashmi@gmail.com.
Dr. Rajesh Mehra: Dr. Mehra is currently associated with Electronics and Communication Engineering
Department of National Institute of Technical Teachers’
Training & Research, Chandigarh, India since 1996. He has received his Doctor of Philosophy in Engineering and
Technology from Panjab University, Chandigarh, India in
2015. Dr. Mehra received his Master of Engineering from
Panjab Univeristy, Chandigarh, India in 2008 and Bachelor of
Technology from NIT, Jalandhar, India in 1994. Dr. Mehra has 20 years of academic and industry experience. He has more than 325 papers to his credit which are published in refereed International Journals and Conferences. Dr. Mehra has guided 75 ME thesis. He is also guiding 02 independent
PhD scholars. He has also authored one book on PLC &
SCADA. He has developed 06 video films in the area of VLSI
Design. His research areas are Advanced Digital Signal
Processing, VLSI Design, FPGA System Design, Embedded
System Design, and Wireless & Mobile Communication. Dr.
Mehra is member of IEEE and ISTE.
978-1-4673-9939-5/16/$31.00 ©2016 IEEE