Capacitive Coupled Contactless Interconnect Design
for 3D ICs
Tony T. Kim and Myat Thu Linn Aung
VIRTUS, School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore
Email: thkim@ntu.edu.sg
Abstract
Data Link (chip A)
Abstract—Through-Silicon-Via (TSV) has been considered as a
promising technology in 3D integration. However, it has several
challenges such as thermal issues, mechanical stress, etc.
Contactless interconnect techniques such as inductive coupling
and capacitive coupling have been investigated as alternative
solutions. In this paper, we present several capacitive coupled
interconnect structures. Various challenges in each interconnect
structure and design techniques are discussed.
(a)
(b)
TxL
Drv.
TxL
Drv.
CC
(c)
Design of Capacitive Coupling Interconnect
A. Conventional capacitive coupled interconnect
Fig. 1(a) illustrates a conventional uni-directional CCI
structure. The coupling capacitor (CC) formed by the parasitic
capacitance between two top metals transfers the data
transition at the driver output to the receiver side [5]. For better
signal integrity, larger CC and smaller parasitic capacitance at
the receiver node are desired. For bi-directional signaling, each
side requires both a driver and a receiver that are controlled
based upon the direction of signal transmission (Fig. 1(b)).
With the same CC, smaller voltage is generated at the receiver
side due to the additional parasitic capacitance coming from
either the unselected receiver or the unselected transmitter [4].
To compensate this signal level degradation, larger
978-1-4673-9308-9/15/$31.00 ©2015 IEEE
Rcv.
RxR
Drv.
TxR
Rcv.
RxR
ENL
ENR
RxL
Rcv.
TxL
Drv.
Keywords-high temperature; 3D ICs; capacitive coupled
interconnect
Introduction
As CMOS technology scaling faces fundamental limitations,
3-dimensional (3D) integration has been considered as a
promising solution to overcome the CMOS scaling limitation.
3D integration can provide various benefits such as short
interconnect, high interconnect density, small form factor, and
heterogeneous integration. Through-Silicon-Via (TSV) is one
of the most effective ways for 3D integration. However, TSVs
are subject to various issues such as mechanical stress,
stringent placement requirement, low yield, and high cost [1].
Alternative interconnect structures utilizing inductive coupling
[2, 3] and capacitive coupling [4-6] have been explored. These
techniques do not require additional complex and precise
processing steps. While the inductor coupling technique can
communicate more than two stacked dies, it requires much
large area due to the on-chip inductor, relatively complex
circuitry for transmitting and receiving data, and higher power
consumption. The capacitive coupling technique can
overcome these issues except that it is only applicable to
face-to-face die stacking. In this paper, several capacitive
coupled interconnect (CCI) structures, their design challenges,
and several circuit solutions are discussed [6-8].
Data Link (chip B)
CC
V clamp
CD
A
RefH
RefL
RxL
Rcv . & Rcvr.
CD
CC
B
TxR
V clamp
RefH
RefL
RxR
Rcv . & Rcvr.
Figure 1. Three different types of capacitive coupling based interconnection
are presented. (a) uni-directional signaling; (b) bi-directional signaling; (c)
proposed simultaneous bi-directional signaling [9].
Figure 2. Multi-level signaling principle of the proposed transceiver. [9]
capacitance needs to be implemented, which increases the
electrode size.
B. Simultaneously bidirectional capacitive interconnect
To improve the data rate per silicon area or channel, a
simultaneously bidirectional capacitive coupled interconnect
was proposed in [9]. Fig. 1(c) depicts the interconnect using
three capacitors in series. The coupling capacitor (CC) is
realized by the parasitic capacitance between two stacked dies
while the driving capacitor (CD) in implemented in each die to
transfer the data transition in each side to the other side through
capacitive coupling. Four voltage levels can be formed at the
floating receiver nodes (A and B) depending upon the data
from both sides. The voltage levels associated with the
transmitting data are illustrated in Fig. 2. When TxL is ‘1’, the
voltage at the receiver node (A) will be formed at a higher level.
Similarly, if TxL is ‘0’, the voltage at A will be at a lower level.
Therefore, the receiver requires two reference levels (RefH
and RefL) to sense the signal swings between ‘00’ and ‘01’ and
between ‘10’ and ‘11’. The dead zone represents the range that
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Figure 3. (a) proposed CCI structure for testing and (b) its input and output
waveform at 28Mbps for probing [9].
C. Capacitive interconnect structure for crosstalk cancellation
High density interconnect is highly required in 3D ICs for
better performance and communication parallelism. However,
when multiple channels are placed closely, crosstalk plays a
critical role in the signal integrity of CCIs. Various techniques
for crosstalk mitigation have been investigated such as GND
shielding and the butterfly differential array structure [7] at the
cost of significant area overhead. To tackle this, we developed
a hybrid CCIs array structure as shown in Fig. 4 [8]. In this
array, both single-ended and differential common-centriod
CCIs are interleaved together. Any crosstalk from differential
CCIs to the surrounding CCIs is cancelled due to the
complementary nature of the noise; whereas differential CCIs
undergo common-mode crosstalk noise from surrounding
single-ended CCIs. The common-mode crosstalk can easily be
suppressed by designing receivers insensitive to the input
common-mode level. Fig. 5 compares the proposed CCI array
with the conventional one. Note that the proposed CCI array
improves the eye-diagram significantly while the conventional
shows no eye opening. Fig. 6 is the receiver used in the
differential CCI. For the common-mode insensitivity, the
receiver input nodes (RX and /RX) are self-biased at VDD/2 and
the input signals (IN and /IN) are transferred to RX and /RX
through bypass capacitors. The receiver detects short pulses
occurring only when signal transitions happen at IN and /IN
(Fig. 7). Consequently, the proposed CCI array enables high
density interconnect without significant power and area
overheads.
Summary
Capacitive coupled interconnect (CCI) can address various
challenges in TSV-based interconnect with low cost and high
reliability. Several CCI schemes such as simultaneously
bidirectional CCI and a hybrid CCI array structure for
crosstalk cancellation are discussed as interconnect solutions
for 3D ICs.
978-1-4673-9308-9/15/$31.00 ©2015 IEEE
Figure 4. Proposed hybrid array structure in 3 × 3 array configuration [8].
Voltage (V)
cannot be used for signaling. This is occurring due to the
parasitic capacitance at the receiver node, which limits the
signal swing like the parasitic capacitance at the conventional
capacitive coupled interconnect. The signal swing can be
improved by reducing the parasitic capacitance or increasing
CC. Fig. 3(a) describes the test structure fabricated for
verification. The tramsmitting data through the data input
(TxL) is recoverd at RxR and used as the transmitting data at
TxR. The finally recovered data at the data output (RxL) shows
the same data pattern as TxL.
(a)
(b)
Figure 5. Eye-diagram comparison: (a) conventional array and (b) proposed
arry (differential CCI output) [8].
Figure 6. Proposed self-biased fully differential receiver [8].
Figure 7. Input and output waveforms of the proposed receiver [8].
Acknowledgement
The authors would like to acknowledge the funding support
from NTU-A*STAR Silicon Technologies Centre of
Excellence under the program grant No. 11235150003.
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