Phase locked loops
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INF4420 Phase locked loops Jørgen Andreas Michaelsen Spring 2013 1 / 55 Outline • • • • Oscillators PLL building blocks PLL loop dynamics Phase noise Spri ng 2013 Pha s e locked l oops 2 2 / 55 INF4420 Spring 2013 Phase locked loops Jørgen Andreas Michaelsen (jorgenam@ifi.uio.no) Introduction Phase locked loops (PLLs) are versatile building blocks used for a range of clocking applications • • • • Synchronization (deskew) Frequency multiplication and synthesis Clock and data recovery (serial data) Demodulation, etc. Spri ng 2013 Pha s e locked l oops 3 3 / 55 Introduction In digital circuits, clocks are used to synchronize computation. Data converters and discrete time systems use clocks to control the sampling. Different applications have very different requirements with respect to accuracy and stability (jitter in sample and hold, timing violations, bit error rate (BER), etc.) Spri ng 2013 Pha s e locked l oops 4 4 / 55 INF4420 Spring 2013 Phase locked loops Jørgen Andreas Michaelsen (jorgenam@ifi.uio.no) Introduction Most applications use a crystal oscillator. Excellent frequency accuracy and stability (noise and temperature), but “low” frequency only and high cost. Recently MEMS based oscillators are emerging. Driven by lower cost and smaller size. Spri ng 2013 Pha s e locked l oops 5 5 / 55 Introduction We begin by discussing voltage controlled oscillators (VCOs). The PLL is a feedback loop that controls the VCO such that its output frequency (or phase) is locked to a reference clock, such as a crystal. Spri ng 2013 Pha s e locked l oops 6 6 / 55 INF4420 Spring 2013 Phase locked loops Jørgen Andreas Michaelsen (jorgenam@ifi.uio.no) Oscillators Several possibilities for implementing oscillators in CMOS, such as switched capacitor, relaxation oscillators, LC oscillators, etc. A popular choice is ring oscillators—n delay elements in series with feedback. No stable state. Delay elements may be single ended (such as inverters) or differential (either pseudo or fully differential). High speed, limited by gate delay. Spri ng 2013 Pha s e locked l oops 7 7 / 55 Oscillators Barkhausen stability criterion • No known sufficient criteria for oscillation • Barkhausen stability criterion is necessary but not sufficicent Spri ng 2013 Pha s e locked l oops 8 8 / 55 INF4420 Spring 2013 Phase locked loops Jørgen Andreas Michaelsen (jorgenam@ifi.uio.no) Ring oscillators A single inverter does not oscillate because its gain is βͺ 1 when the phase shift is 180β Two inverters have two stable operating points Spri ng 2013 Pha s e locked l oops 9 9 / 55 Ring oscillators π0 = Spri ng 2013 Pha s e locked l oops 1 2ππ 10 10 / 55 INF4420 Spring 2013 Phase locked loops Jørgen Andreas Michaelsen (jorgenam@ifi.uio.no) Fully differential ring oscillators • Reject supply and substrate noise (CMRR and PSRR) • Even number of stages possible • No rail to rail swing Spri ng 2013 Pha s e locked l oops 11 11 / 55 Fully differential ring oscillators A popular choice for implementing the fully differential delay cell Spri ng 2013 Pha s e locked l oops 12 12 / 55 INF4420 Spring 2013 Phase locked loops Jørgen Andreas Michaelsen (jorgenam@ifi.uio.no) Voltage controlled oscillators (VCOs) Control voltage, πππ‘π , is used to generate biasing of the oscillator to modulate the output frequency. In most practical cases we are using the control voltage to modulate the biasing current (V/I). Spri ng 2013 Pha s e locked l oops 13 13 / 55 Voltage controlled oscillators (VCOs) Starved inverter VCO example: Spri ng 2013 Pha s e locked l oops 14 14 / 55 INF4420 Spring 2013 Phase locked loops Jørgen Andreas Michaelsen (jorgenam@ifi.uio.no) Voltage controlled oscillators (VCOs) Typical specifications • • • • • • • Tuning range Linearity, πππ’π‘ vs. πππ‘π Amplitude Power consumption CMRR and PSRR Jitter (phase noise) … Spri ng 2013 Pha s e locked l oops 15 15 / 55 Oscillator model We model the oscillator in terms of phase, π. Later when we discuss the full PLL we model the phase response of the system. Without loss of generality, we assume a sine wave output of the oscillator (can be any periodic function) πππ π π‘ = πΈ sin(π0 π‘ + π(π‘)) Free running (fixed) frequency Spri ng 2013 Pha s e locked l oops Instantaneous phase 16 16 / 55 INF4420 Spring 2013 Phase locked loops Jørgen Andreas Michaelsen (jorgenam@ifi.uio.no) Oscillator model Phase is the integral of frequency! (Important) Spri ng 2013 Pha s e locked l oops 17 17 / 55 Oscillator model Instantaneous output frequency ππππ π‘ π‘ = π π0 π‘ + π π‘ ππ‘ = π0 + ππ ππ‘ Deviation from the free running frequency π π‘ ≡ ππππ π‘ π‘ − π0 = Spri ng 2013 Pha s e locked l oops ππ ππ‘ 18 18 / 55 INF4420 Spring 2013 Phase locked loops Jørgen Andreas Michaelsen (jorgenam@ifi.uio.no) Oscillator model π‘ π π‘ =π 0 + π π ππ 0 Arbitrary initial phase Laplace transform: π π = π π πΎππ π πππ‘π π = π π πΎππ π is a mapping from the control voltage to the frequency deviation. Assumed to be constant. Spri ng 2013 Pha s e locked l oops 19 19 / 55 Phase locked loop (PLL) The PLL is a closed loop feedback system that drives the control voltage of the VCO, “locking” its phase to a reference phase, by continuously comparing the phase. πππ is a reference clock. The divider is needed if we want the output frequency multiplied. Spri ng 2013 Pha s e locked l oops 20 20 / 55 INF4420 Spring 2013 Phase locked loops Jørgen Andreas Michaelsen (jorgenam@ifi.uio.no) Phase locked loop (PLL) • Needed because the output frequency of the VCO is unpredictable—sensitive to the PVT condition. Also, noise causes the phase to drift. • I.e. we can not simply “program” a control voltage and know what the output frequency is. • Or needed because we want to synchronize two clocks in some applications (zero crossings occurring at the same time instants) • Or if we want to demodulate the input signal … Spri ng 2013 Pha s e locked l oops 21 21 / 55 Phase locked loop (PLL) We will first study how each PLL building block works and how we can model it in terms of phase • • • • VCO (already covered) Divider Phase detector Loop filter We then model the PLL as a system Spri ng 2013 Pha s e locked l oops 22 22 / 55 INF4420 Spring 2013 Phase locked loops Jørgen Andreas Michaelsen (jorgenam@ifi.uio.no) Clock divider (DIV) Easy to divide by 2π . Fractions are also possible. The division is constant, thus: π π ππππ£ π = π Spri ng 2013 Pha s e locked l oops 23 23 / 55 Phase detector (PD) • Generate an output voltage or current where the (average) value is proportional to the phase difference • Two inputs, the reference clock (REF) and the (divided) VCO clock. Several possibilities for implementing the PD, but the so called charge pump PD is the most common. Many variations of the charge pump PD. Spri ng 2013 Pha s e locked l oops 24 24 / 55 INF4420 Spring 2013 Phase locked loops Jørgen Andreas Michaelsen (jorgenam@ifi.uio.no) Linear PD Multiplying PD, πππ = πΎπ πππ ππππ£ πππ = πΈππ sin ππ‘ ππππ£ = πΈπππ£ cos(ππ‘ − ππ ) sin π΄ + cos π΅ = → πππ ππππ‘π Spri ng 2013 1 2 sin π΄ + π΅ + sin π΄ − π΅ πΈππ πΈπππ£ = πΎπ sin ππ + sin 2ππ‘ − ππ 2 πΈππ πΈπππ£ = πΎππ πΎπ sin ππ ≈ πΎππ πΎππ ππ 2 Pha s e locked l oops 25 25 / 55 Charge pump PD Generate a pulsed output who’s pulse width is equal to the phase difference (ππ ). If REF comes first the VCO must speed up. Otherwise the VCO must slow down. πΌππ = πΌπβ Spri ng 2013 Pha s e locked l oops ππ 2π 26 26 / 55 INF4420 Spring 2013 Phase locked loops Jørgen Andreas Michaelsen (jorgenam@ifi.uio.no) Loop filter (LP) • Smooth out the pulses from the PD • Usually, current input (from the PD) and voltage output (VCO control voltage) → πΉ −1 • Important for the overall PLL transfer function • Again, several possibilities … Active vs. passive, first order vs. second order. Spri ng 2013 Pha s e locked l oops 27 27 / 55 Loop filter (LP) ππππ‘π (π ) π1 (π )π2 (π ) = πΌππ (π ) π1 (π ) + π2 (π ) 1 + πΆ1 π π = π πΆ1 + πΆ2 + πΆ1 πΆ2 π π Simplify this as: De-glitch capacitor πΆ2 βͺ πΆ1 π1 = π + 1 π πΆ1 ππππ‘π (π ) 1 1 + π π πΆ1 = πΎππ π»ππ π ≈ πΌππ (π ) πΆ1 π Spri ng 2013 Pha s e locked l oops π2 = 1 π πΆ2 πΎππ = πΆ1−1 ππ§ = π πΆ1 −1 28 28 / 55 INF4420 Spring 2013 Phase locked loops Jørgen Andreas Michaelsen (jorgenam@ifi.uio.no) Small signal PLL model We now have small signal models for all components. We use this to model the full feedback system in terms of a Laplace description of the phase and derive the system transfer function. Spri ng 2013 Pha s e locked l oops 29 29 / 55 Small signal PLL model ππ (π ) ππ (π ) + + π΄(π ) ππ (π ) − π½ π»π π = Spri ng 2013 ππ π π΄ π = ππ π 1 + π½π΄ π Pha s e locked l oops π»π π = ππ π 1 = ππ π 1 + π½π΄(π ) 30 30 / 55 INF4420 Spring 2013 Phase locked loops Jørgen Andreas Michaelsen (jorgenam@ifi.uio.no) Small signal PLL model πΎππ πΎππ π»ππ π πΎππ π 1 , π½= π π Phase difference (error) transfer function ππ π 1 ππ = = πππ π 1 + π½π΄ π πΎππ πΎππ π»ππ π πΎππ π + ππ π΄ π = Spri ng 2013 Pha s e locked l oops 31 31 / 55 Small signal PLL model The DC gain of ππ πππ is zero: The phase difference converges towards zero, which is what we want. ππππ ≡ πΎππ πΎππ πΎππ π π , πΎππ π»ππ π = πΎππ ππ π 1 = 2 ⋅ πππ π ππππ Spri ng 2013 Pha s e locked l oops 1 π + 1 ππ§ π 2 π π 2 1+ + 2 ππ§ ππππ 32 32 / 55 INF4420 Spring 2013 Phase locked loops Jørgen Andreas Michaelsen (jorgenam@ifi.uio.no) Small signal PLL model Similarly we find the output transfer function π» π = ππΎππ πΎππ π»ππ π πΎππ π π π π΄ π = = πππ π 1 + π½π΄ π πΎππ πΎππ π»ππ π πΎππ π + ππ Second order denominator π π 2 1+ + 2 π0 π π0 π 1+ ππ§ π» π =π π π 2 1+ + 2 ππ§ ππππ Spri ng 2013 Resonant frequency π0 = ππππ ππ§ π= ππππ Pha s e locked l oops 33 33 / 55 Small signal PLL model • ππ§ > ππππ underdamped, transient oscillations • π = 0.5 → π» π = π ππ§ = ππππ 2 π ππ§ 2 π 1+ ππππ 1+ , , π3ππ΅ = 2.5ππππ • π βͺ 0.5, requires a low frequency ππ§ , which implies large passive component values. Spri ng 2013 Pha s e locked l oops 34 34 / 55 INF4420 Spring 2013 Phase locked loops Jørgen Andreas Michaelsen (jorgenam@ifi.uio.no) Small signal PLL model The book outlines a basic design procedure (19.2.3) π = 0.1 and π = 0.5 are reasonable choices, depending on the application. Spri ng 2013 Pha s e locked l oops 35 35 / 55 Small signal PLL model The small signal model does not capture all aspects of the system. We must be aware of the limitations, including • Large signal lock. What happens before the small signal model is valid? How long does it take to achieve lock? Is the PLL able to achieve lock? • The PLL is discrete time, but we model it as continuous time (e.g. the phase detector) Spri ng 2013 Pha s e locked l oops 36 36 / 55 INF4420 Spring 2013 Phase locked loops Jørgen Andreas Michaelsen (jorgenam@ifi.uio.no) Non-ideal circuit properties • The charge pump phase detector does not track when the phase difference is small because of finite rise and fall times • Mismatch in the up and down current due to timing or current source impedance • Power supply coupled noise, random and deterministic jitter • … Spri ng 2013 Pha s e locked l oops 37 37 / 55 Jitter and phase noise Ideally, the π-th zero crossing of the clock is at π‘π = πππ Clock signal is conveyed by the timing of the zero crossings relative to some reference voltage level, or the phase. Spri ng 2013 Pha s e locked l oops 38 38 / 55 INF4420 Spring 2013 Phase locked loops Jørgen Andreas Michaelsen (jorgenam@ifi.uio.no) Jitter and phase noise However, noise introduces a random deviation from the ideal zero crossing time points π‘π = ππ0 + ππ ππ is the absolute jitter. Can also be expressed in radians ππ = ππ Spri ng 2013 2π π0 Pha s e locked l oops 39 39 / 55 Jitter and phase noise We define phase noise, ππ (π), as the power spectral density of the sequence ππ . π0 ππ2 = 2π 2 1 2π0 ππ π ππ 0 rad2 ππ (π) is Hz Spri ng 2013 Pha s e locked l oops 40 40 / 55 INF4420 Spring 2013 Phase locked loops Jørgen Andreas Michaelsen (jorgenam@ifi.uio.no) Period jitter Rather than looking at the jitter in terms of absolute jitter, the absolute time of the zero crossings, we can look at the length of the clock periods: ππ = π‘π+1 − π‘π = π0 + ππ+1 − ππ Spri ng 2013 Pha s e locked l oops 41 41 / 55 Period jitter Deviation of the period from the nominal value, π0 π½π = ππ − π0 = ππ+1 − ππ The period jitter is the differentiation of the absolute jitter, π§ − 1 ππ½2 = Spri ng 2013 π0 π 1 2π0 2 sin2 πππ0 ππ π ππ 0 Pha s e locked l oops 42 42 / 55 INF4420 Spring 2013 Phase locked loops Jørgen Andreas Michaelsen (jorgenam@ifi.uio.no) P-Cycle jitter Rather than looking at the deviation in one clock period, we now look at the variation in a duration defined by P clock periods—P-cycle jitter π½ π π 2 ππ½(π) = Spri ng 2013 = π‘π+π − π‘π − ππ0 = ππ+π − ππ π0 π 1 2π0 2 sin2 ππππ0 ππ π ππ 0 Pha s e locked l oops 43 43 / 55 Adjacent period jitter The difference between the length of two adjacent periods π½π+1 − π½π = ππ+1 − π0 − ππ − π0 This implies double differentiation of the absolute jitter, π§ − 1 2 ππΆ2 = Spri ng 2013 2π0 π 2 Pha s e locked l oops 1 2π0 sin4 πππ0 ππ π ππ 0 44 44 / 55 INF4420 Spring 2013 Phase locked loops Jørgen Andreas Michaelsen (jorgenam@ifi.uio.no) Measuring phase noise • More practical to measure the (estimated) phase noise rather than the jitter • Jitter can be calculated from the phase noise • Phase noise is inferred from the PSD of the clock signal directly, ππ£ (π) • Baseband noise is mixed up by the carrier • Spectrum analyzers usually have a phase noise measurement option Spri ng 2013 Pha s e locked l oops 45 45 / 55 Measuring phase noise ππ£ β Δπ = Spri ng 2013 1 + Δπ π0 , π΄2 2 Pha s e locked l oops β Δπ ≡ ππ Δπ 2 46 46 / 55 INF4420 Spring 2013 Phase locked loops Jørgen Andreas Michaelsen (jorgenam@ifi.uio.no) Oscillator phase noise • The integrating nature of the oscillator accumulates the noise • Flicker noise is now π −3 and white noise is π −2 Spri ng 2013 Pha s e locked l oops 47 47 / 55 Oscillator phase noise in the time domain • In the time domain, the jitter accumulates • A “noise event” remains for all subsequent time. There is no restoring force acting on the oscillator Spri ng 2013 Pha s e locked l oops 48 48 / 55 INF4420 Spring 2013 Phase locked loops Jørgen Andreas Michaelsen (jorgenam@ifi.uio.no) Jitter and phase noise in PLLs All PLL components generate noise and influence the overall PLL jitter, including the reference clock. We use small signal transfer functions to find the noise influence on the PLL output. Spri ng 2013 Pha s e locked l oops 49 49 / 55 Reference and divider phase noise • We already know the transfer function from the PLL input to the PLL output, π»(π ) • Divider output and reference are connected to the PLL input • Lowpass transfer function Spri ng 2013 Pha s e locked l oops 50 50 / 55 INF4420 Spring 2013 Phase locked loops Jørgen Andreas Michaelsen (jorgenam@ifi.uio.no) PLL VCO phase noise π»ππ π π = π π ππ = ππ£ππ π πΎππ πΎππ π»ππ π πΎππ π + ππ The VCO noise transfer function is highpass, thus the VCO phase noise is suppressed inside the PLL bandwidth. I.e. the feedback loop is tracking and correcting the VCO phase noise. Spri ng 2013 Pha s e locked l oops 51 51 / 55 Charge pump and loop filter noise π π ππΎππ π π»π π = = ππ π πΎππ πΎππ π»ππ π πΎππ π + ππ Noise injected at the output of the loop filter is bandpass filtered on the output of the PLL Spri ng 2013 Pha s e locked l oops 52 52 / 55 INF4420 Spring 2013 Phase locked loops Jørgen Andreas Michaelsen (jorgenam@ifi.uio.no) Total PLL phase noise ππ π = ππ,ππ π π» π 2 + ππ2 π π»π π + ππ,ππ π π π»ππ π π 2 Spri ng 2013 2 Pha s e locked l oops 53 53 / 55 Delay locked loop (DLL) In certain applications we can use a delay locked loop instead. Using a delay line rather than a VCO. Phase noise does not accumulate in the delay line, like it does in the VCO. No integration in the delay line, so loop order is one less than the PLL (set by the loop filter). Implications for stability and settling. Spri ng 2013 Pha s e locked l oops 54 54 / 55 INF4420 Spring 2013 Phase locked loops Jørgen Andreas Michaelsen (jorgenam@ifi.uio.no) Further reading Gardner, Phaselock Techniques, Wiley, 2005 Fischette, Dennis Fischette's 1-Stop PLL Center Kundert, Predicting the phase noise and jitter of PLL-based frequency synthesizers, 2012 Spri ng 2013 Pha s e locked l oops 55 55 / 55 INF4420 Spring 2013 Phase locked loops Jørgen Andreas Michaelsen (jorgenam@ifi.uio.no)
