HEF4050B-Q100
The HEF4050B-Q100 provides six non-inverting buffers with high current output capability suitable for driving TTL or high capacitive loads. Voltages in excess of the buffer supply voltage are permitted. This feature allows the buffers to be used to convert logic levels of up to 15 V to standard TTL levels. Their guaranteed fan-out into common bipolar logic
elements is shown in Table 3 .
It operates over a recommended V
DD
power supply range of 3 V to 15 V referenced to V
SS
(usually ground). Unused inputs must be connected to V
DD
, V
SS
, or another input.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 3) and is suitable for use in automotive applications.
 Automotive product qualification in accordance with AEC-Q100 (Grade 3)
 Specified from

40

C to +85

C
 Accepts input voltages in excess of the supply voltage
 Fully static operation
 5 V, 10 V, and 15 V parametric ratings
 Standardized symmetrical output characteristics
 ESD protection:
 MIL-STD-883, method 3015 exceeds 2000 V
 HBM JESD22-A114F exceeds 2000 V
 MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0

)
 Complies with JEDEC standard JESD 13-B
 LOCMOS (Local Oxidation CMOS) to DTL/TTL converter
 HIGH sink current for driving two TTL loads
 HIGH-to-LOW level logic conversion

HEF4050B-Q100
Hex non-inverting buffers
Table 1.
Ordering information
All types operate from

40

C to +85

C.
Type number Package
Name Description
HEF4050BT-Q100 SO16 plastic small outline package; 16 leads; body width 3.9 mm
$
$
$
<
<
<
$
$
<
<
$ <
DDH
Fig 1.
Logic symbol
Version
SOT109-1
LQSXW
$ <
DDH
9
66
DDH
Fig 2.
Logic diagram for one gate Fig 3.
Input protection circuit
$
<
$
9
66
9
''
<
$
<
+()%4
<
$
<
$
QF
<
$
QF
DDD
Fig 4.
Pin configuration
HEF4050B_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 15 June 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
2 of 11

Table 2.
Pin description
Symbol
V
DD
1Y to 6Y
1A to 6A
V
SS n.c.
Pin
1
2, 4, 6, 10, 12, 15
3, 5, 7, 9, 11, 14,
8
13, 16
HEF4050B-Q100
Hex non-inverting buffers
Description supply voltage output input ground supply voltage not connected
Table 3.
Guaranteed fan-out
Driven element
Standard TTL
74 LS
74 L
Guaranteed fan-out
2
9
16
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions
I
DD
T stg
T amb
P tot
P
V
DD
I
IK
V
I
I
OK
I
I/O supply voltage input clamping current input voltage output clamping current input/output current supply current storage temperature ambient temperature total power dissipation power dissipation
V
V
T
I
O
<
<

0.5 V or V amb


0.5 V
40 per output

O
> V
C to +85

C
DD
+ 0.5 V
[1] For SO16 package: P tot
derates linearly with 8 mW/K above 70

C.
[1]
-
-

65

40
-
-
Min

0.5

10

0.5
-
Max
+18
-
+18

10
10
50
+150
+85
500
100
Unit
V mA
V mA mA mA

C

C mW mW
HEF4050B_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 15 June 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
3 of 11

HEF4050B-Q100
Hex non-inverting buffers
Table 5.
Recommended operating conditions
Symbol
V
DD
V
I
T amb
 t/

V
Parameter supply voltage input voltage ambient temperature input transition rise and fall rate
Conditions in free air
V
DD
= 5 V
V
DD
= 10 V
V
DD
= 15 V
Table 6.
Static characteristics
V
SS
= 0 V; V
I
= V
SS
or V
DD
unless otherwise specified.
Symbol Parameter Conditions V
DD
V
IH
V
IL
V
OH
V
OL
I
OH
I
OL
I
I
I
DD
C
I
HIGH-level input voltage

I
O

< 1

A
LOW-level input voltage

I
O

< 1

A
HIGH-level output voltage

I
O

< 1

A
LOW-level output voltage

I
O

< 1

A
HIGH-level output current V
O
= 2.5 V
V
O
= 4.6 V
V
O
= 9.5 V
V
O
= 13.5 V
LOW-level output current V
O
= 0.4 V
V
O
= 0.5 V
V
O
= 1.5 V input leakage current supply current I
O
= 0 A input capacitance
15 V
5 V
5 V
10 V
15 V
4.75 V
10 V
15 V
15 V
5 V
10 V
15 V
5 V
10 V
15 V
5 V
10 V
15 V
5 V
10 V
15 V
5 V
10 V
Min
3
0

40
-
-
-
Max
15
15
+85
3.75
0.5
0.08
Unit
V
V

C
 s/V
 s/V
 s/V
-
3.5
12.0
24.0
-
-
-
-
-
-
-
-
-
-
-
4.95
9.95
14.95
-
-
T amb
=

40

C T amb
= 25

C T amb
= 85

C Unit
Min Max Min Max Min Max
3.5
3.5
3.5
V
7.0
11.0
-
-
-
1.5
7.0
11.0
-
-
-
1.5
7.0
11.0
-
-
-
1.5
V
V
V
3.0
4.0
-
-
-
0.05
0.05
0.05

1.7

0.52

1.3

3.6
-
-
-

0.3
4.0
8.0
16.0
-
-
-
4.95
9.95
14.95
-
-
-
-
-
-
-
2.9
10.0
20.0
-
-
-
-
-
3.0
4.0
-
-
-
0.05
0.05
0.05

1.4

0.44

1.1

3.0
-
-
-

0.3
4.0
8.0
16.0
7.5
4.95
9.95
14.95
-
-
-
-
-
-
-
-
-
2.3
8.0
16.0
-
-
-
-
-
3.0
V
4.0
V
V
-
-
0.05
V
0.05
V
V
V
0.05
V

1.1
mA

0.36 mA

0.9
mA

2.4
mA
mA
mA
mA

1.0

A
30

A
60

A
120

A
pF
HEF4050B_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 15 June 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
4 of 11

HEF4050B-Q100
Hex non-inverting buffers
Table 7.
Dynamic characteristics
V
SS
= 0 V; T amb
= 25

C; unless otherwise specified. for test circuit, see Figure 6 .
Symbol Parameter t
PHL t
PLH t
THL t
TLH
HIGH to LOW propagation delay
LOW to HIGH propagation delay
HIGH to LOW output transition time
LOW to HIGH output transition time
Conditions nA to nY; see
Figure 5
nA to nY; see
Figure 5
see
Figure 5
see
Figure 5
V
DD
5 V
10 V
15 V
5 V
10 V
15 V
5 V
10 V
15 V
5 V
10 V
15 V
Extrapolation formula
[1]
26 ns + (0.18 ns/pF)C
L
16 ns + (0.08 ns/pF)C
L
12 ns + (0.05 ns/pF)C
L
[1]
28 ns + (0.55 ns/pF)C
L
14 ns + (0.23 ns/pF)C
L
[1]
12 ns + (0.16 ns/pF)C
L
7 ns + (0.35 ns/pF)C
L
3 ns + (0.14 ns/pF)C
L
[1]
2 ns + (0.09 ns/pF)C
L
10 ns + (1.00 ns/pF)C
L
9 ns + (0.42 ns/pF)C
L
6 ns + (0.28 ns/pF)C
L
-
-
-
-
-
-
-
-
-
Min Typ Max Unit
35 70 ns
-
20
15
35
30 ns ns
55
25
20
25
110
55
40
50 ns ns ns ns
10
7
60
30
20
20 ns
14 ns
120 ns
60 ns
40 ns
[1] The typical values of the propagation delay and transition times are calculated from the extrapolation formulas shown (C
L
in pF).
Table 8.
Dynamic power dissipation P
D
P
D
can be calculated from the formulas shown. V
SS
= 0 V; t r
= t f

20 ns; T amb
= 25

C.
Symbol Parameter
P
D dynamic power dissipation
V
DD
5 V
10 V
15 V
Typical formula for P
D
(

W)
P
D
= 3800

f i
+

(f o

C
L
)

V
DD
2
P
D
= 11600

f i
+

(f o

C
L
)

V
DD
2
P
D
= 65900

f i
+

(f o

C
L
)

V
DD
2 where: f i
= input frequency in MHz, f o
= output frequency in MHz,
C
L
= output load capacitance in pF,
V
DD
= supply voltage in V,

(f o

C
L
) = sum of the outputs.
HEF4050B_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 15 June 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
5 of 11

HEF4050B-Q100
Hex non-inverting buffers
W
U
W
I
9
,
LQSXW 9
0
9
W
3/+
W
3+/
RXWSXW
9
2+
9
2/
9
0
W
7/+
Measurement points are given in Table 9 .
V
OL
and V
OH
are typical output voltage levels that occur with the output load.
Fig 5.
Input to output propagation delays
W
7+/
DDL
Table 9.
Measurement points
Input
V
M
0.5V
DD
V
I
0 V to V
DD
Output
V
M
0.5V
DD
9
''
9
,
9
2
*
'87
57
&/
DDJ
Test data is given in
Table 10 .
Definitions for test circuit:
C
L
= Load capacitance including jig and probe capacitance.
R
T
= Termination resistance should be equal to output impedance Z o
of the pulse generator.
Fig 6.
Test circuit for measuring switching times
Table 10.
Test data
Supply voltage
5 V to 15 V
Input
V
I
V
DD
V
M
0.5V
I t
 r
, t f
20 ns
Load
C
L
50 pF
HEF4050B_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 15 June 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
6 of 11

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HEF4050B-Q100
Hex non-inverting buffers
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Fig 7.
Package outline SOT109-1 (SO16)
HEF4050B_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 15 June 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
7 of 11

HEF4050B-Q100
Hex non-inverting buffers
Table 11.
Abbreviations
Acronym
DTL
Description
Diode Transistor Logic
DUT
LOCMOS
HBM
ESD
Device Under Test
Local Oxidation CMOS
Human Body Model
ElectroStatic Discharge
MM
MIL
TTL
Machine Model
Military
Transistor-Transistor Logic
Table 12.
Revision history
Document ID
HEF4050B-Q100 v.2
Modifications:
HEF4050B_Q100 v.1
Release date Data sheet status Change notice Supersedes
20160615 Product data sheet HEF4050B-Q100 v.1
Table 4 : condition for input clamping current changed (typo corrected).
Table 5 : maximum value for input voltage changed (typo corrected).
20131111 Product data sheet -
HEF4050B_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 15 June 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
8 of 11

HEF4050B-Q100
Hex non-inverting buffers
Document status
[1][2]
Objective [short] data sheet
Product status
[3]
Development
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
Definition
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com
.
Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the
Product data sheet.
Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof.
Suitability for use in automotive applications — This NXP
Semiconductors product has been qualified for use in automotive applications. Unless otherwise agreed in writing, the product is not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk.
Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products.
NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer.
HEF4050B_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 15 June 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
9 of 11

HEF4050B-Q100
Hex non-inverting buffers
No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities.
Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions.
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
HEF4050B_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 15 June 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
10 of 11

11
12
13
14
7
8
9
10
15
16
16.1
16.2
16.3
16.4
17
18
1
2
3
4
5
6
6.1
6.2
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
Pinning information . . . . . . . . . . . . . . . . . . . . . . 2
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
Functional description . . . . . . . . . . . . . . . . . . . 3
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3
Recommended operating conditions. . . . . . . . 4
Static characteristics . . . . . . . . . . . . . . . . . . . . . 4
Dynamic characteristics . . . . . . . . . . . . . . . . . . 5
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 7
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . 8
Legal information. . . . . . . . . . . . . . . . . . . . . . . . 9
Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 9
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Contact information. . . . . . . . . . . . . . . . . . . . . 10
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
HEF4050B-Q100
Hex non-inverting buffers
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’.
© NXP Semiconductors N.V. 2016.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 15 June 2016
Document identifier: HEF4050B_Q100